Eric Lee / smarc-uboot

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Commit 4d74c02724668c5068519fa37639de2d94aad505

Authored by Marek Vasut
1 parent 5f79d00840
Exists in v2017.01-smarct4x and in 29 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: sockit: Use more relaxed DRAM timings 

The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

Showing 3 changed files with 80 additions and 80 deletions Side-by-side Diff

board/terasic/sockit/qts/iocsr_config.h
Diff comments   View file @ 4d74c02
... ... @@ -181,17 +181,17 @@
181 181 0x00001000,
182 182 0xA0000034,
183 183 0x0D000001,
184   - 0x40680208,
185   - 0x41034051,
186   - 0x12481A00,
187   - 0x802080D0,
188   - 0x34051406,
189   - 0x01A02490,
190   - 0x080D0000,
191   - 0x51406802,
192   - 0x02490340,
  184 + 0xE0680B2C,
  185 + 0x20834038,
  186 + 0x11441A00,
  187 + 0x80B2C0D0,
  188 + 0x34038E06,
  189 + 0x01A00208,
  190 + 0x2C0D0000,
  191 + 0x38E0680B,
  192 + 0x00208340,
193 193 0xD000001A,
194   - 0x0680A280,
  194 + 0x0680B2C0,
195 195 0x10040000,
196 196 0x00200000,
197 197 0x10040000,
198 198  
... ... @@ -255,17 +255,17 @@
255 255 0x00001000,
256 256 0xA0000034,
257 257 0x0D000001,
258   - 0x40680208,
259   - 0x49034051,
260   - 0x12481A02,
261   - 0x80A280D0,
262   - 0x34030C06,
  258 + 0xE0680B2C,
  259 + 0x20834038,
  260 + 0x11441A00,
  261 + 0x80B2C0D0,
  262 + 0x34038E06,
263 263 0x01A00040,
264   - 0x280D0002,
265   - 0x5140680A,
266   - 0x02490340,
267   - 0xD012481A,
268   - 0x0680A280,
  264 + 0x2C0D0002,
  265 + 0x38E0680B,
  266 + 0x00208340,
  267 + 0xD001041A,
  268 + 0x0680B2C0,
269 269 0x10040000,
270 270 0x00200000,
271 271 0x10040000,
272 272  
... ... @@ -330,18 +330,18 @@
330 330 0x14F3690D,
331 331 0x1A041414,
332 332 0x00D00000,
333   - 0x04864000,
334   - 0x59647A01,
335   - 0xD32CA3DE,
336   - 0xF551451E,
337   - 0x034CD348,
  333 + 0x18864000,
  334 + 0x49247A06,
  335 + 0xABCF23D7,
  336 + 0xF7DE791E,
  337 + 0x0356E388,
338 338 0x821A0000,
339 339 0x0000D000,
340   - 0x05140680,
341   - 0xD669A47A,
342   - 0x1ED32CA3,
343   - 0x48F55E79,
344   - 0x00034C92,
  340 + 0x05960680,
  341 + 0xD749247A,
  342 + 0x1EABCF23,
  343 + 0x88F7DE79,
  344 + 0x000356E3,
345 345 0x00080200,
346 346 0x00001000,
347 347 0x00080200,
348 348  
... ... @@ -404,18 +404,18 @@
404 404 0x14F3690D,
405 405 0x1A041414,
406 406 0x00D00000,
407   - 0x14864000,
408   - 0x59647A05,
409   - 0x9228A3DE,
410   - 0xF65E791E,
411   - 0x034CD348,
412   - 0x821A0186,
  407 + 0x18864000,
  408 + 0x49247A06,
  409 + 0xABCF23D7,
  410 + 0xF7DE791E,
  411 + 0x0356E388,
  412 + 0x821A01C7,
413 413 0x0000D000,
414 414 0x00000680,
415   - 0xD669A47A,
416   - 0x1E9228A3,
417   - 0x48F65E79,
418   - 0x00034CD3,
  415 + 0xD749247A,
  416 + 0x1EABCF23,
  417 + 0x88F7DE79,
  418 + 0x000356E3,
419 419 0x00080200,
420 420 0x00001000,
421 421 0x00080200,
422 422  
... ... @@ -478,18 +478,18 @@
478 478 0x14F3690D,
479 479 0x1A041414,
480 480 0x00D00000,
481   - 0x0C864000,
482   - 0x79E47A03,
483   - 0xB2AAA3D1,
484   - 0xF551451E,
485   - 0x035CD348,
  481 + 0x18864000,
  482 + 0x49247A06,
  483 + 0xABCF23D7,
  484 + 0xF7DE791E,
  485 + 0x0356E388,
486 486 0x821A0000,
487 487 0x0000D000,
488 488 0x00000680,
489   - 0xD159647A,
490   - 0x1ED32CA3,
491   - 0x48F55145,
492   - 0x00035CD3,
  489 + 0xD749247A,
  490 + 0x1EABCF23,
  491 + 0x88F7DE79,
  492 + 0x000356E3,
493 493 0x00080200,
494 494 0x00001000,
495 495 0x00080200,
496 496  
... ... @@ -552,18 +552,18 @@
552 552 0x14F1690D,
553 553 0x1A041414,
554 554 0x00D00000,
555   - 0x04864000,
556   - 0x69A47A01,
557   - 0x9228A3D6,
558   - 0xF65E791E,
559   - 0x034C9248,
  555 + 0x18864000,
  556 + 0x49247A06,
  557 + 0xABCF23D7,
  558 + 0xF7DE791E,
  559 + 0x0356E388,
560 560 0x821A0000,
561 561 0x0000D000,
562 562 0x00000680,
563   - 0xDE59647A,
564   - 0x1ED32CA3,
565   - 0x48F55E79,
566   - 0x00034CD3,
  563 + 0xD749247A,
  564 + 0x1EABCF23,
  565 + 0x88F7DE79,
  566 + 0x000356E3,
567 567 0x00080200,
568 568 0x00001000,
569 569 0x00080200,
board/terasic/sockit/qts/pll_config.h
Diff comments   View file @ 4d74c02
... ... @@ -10,13 +10,13 @@
10 10 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
11 11  
12 12 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
13   -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
  13 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
14 14 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
15 15 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
16 16 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
17   -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
  17 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
18 18 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
19   -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
  19 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
20 20 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
21 21 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
22 22 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
... ... @@ -61,7 +61,7 @@
61 61 #define CONFIG_HPS_CLK_OSC2_HZ 25000000
62 62 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
63 63 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
64   -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
  64 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
65 65 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
66 66 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
67 67 #define CONFIG_HPS_CLK_EMAC0_HZ 1953125
... ... @@ -69,7 +69,7 @@
69 69 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
70 70 #define CONFIG_HPS_CLK_NAND_HZ 50000000
71 71 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
72   -#define CONFIG_HPS_CLK_QSPI_HZ 370000000
  72 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000
73 73 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
74 74 #define CONFIG_HPS_CLK_CAN0_HZ 12500000
75 75 #define CONFIG_HPS_CLK_CAN1_HZ 12500000
... ... @@ -78,8 +78,8 @@
78 78 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
79 79  
80 80 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1
81   -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
82   -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
  81 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
  82 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
83 83  
84 84  
85 85 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
board/terasic/sockit/qts/sdram_config.h
Diff comments   View file @ 4d74c02
... ... @@ -32,11 +32,11 @@
32 32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
34 34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
35   -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
36   -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
  35 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
  36 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
37 37 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
38 38 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
39   -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
  39 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
40 40 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
41 41 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
42 42 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
... ... @@ -46,7 +46,7 @@
46 46 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
47 47 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
48 48 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
49   -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
  49 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
50 50 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
51 51 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
52 52 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
... ... @@ -127,8 +127,8 @@
127 127  
128 128 /* Sequencer defines configuration */
129 129 #define AFI_RATE_RATIO 1
130   -#define CALIB_LFIFO_OFFSET 8
131   -#define CALIB_VFIFO_OFFSET 6
  130 +#define CALIB_LFIFO_OFFSET 12
  131 +#define CALIB_VFIFO_OFFSET 10
132 132 #define ENABLE_SUPER_QUICK_CALIBRATION 0
133 133 #define IO_DELAY_PER_DCHAIN_TAP 25
134 134 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
... ... @@ -147,7 +147,7 @@
147 147 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
148 148 #define MAX_LATENCY_COUNT_WIDTH 5
149 149 #define READ_VALID_FIFO_SIZE 16
150   -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
  150 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
151 151 #define RW_MGR_MEM_ADDRESS_MIRRORING 0
152 152 #define RW_MGR_MEM_DATA_MASK_WIDTH 4
153 153 #define RW_MGR_MEM_DATA_WIDTH 32
154 154  
... ... @@ -171,16 +171,16 @@
171 171 const u32 ac_rom_init[] = {
172 172 0x20700000,
173 173 0x20780000,
174   - 0x10080431,
175   - 0x10080530,
176   - 0x10090044,
177   - 0x100a0008,
  174 + 0x10080471,
  175 + 0x10080570,
  176 + 0x10090006,
  177 + 0x100a0218,
178 178 0x100b0000,
179 179 0x10380400,
180   - 0x10080449,
181   - 0x100804c8,
182   - 0x100a0024,
183   - 0x10090010,
  180 + 0x10080469,
  181 + 0x100804e8,
  182 + 0x100a0006,
  183 + 0x10090218,
184 184 0x100b0000,
185 185 0x30780000,
186 186 0x38780000,