spi: Zap ftssp010_spi driver

Zap ftssp010_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Axel Lin <axel.lin@ingics.com>

spi: Zap ftssp010_spi driver
Zap ftssp010_spi driver since the boards used this driver is no longer been active. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Axel Lin <axel.lin@ingics.com>
Jagan Teki
1 parent 4ad479e3d6
Showing 2 changed files with 0 additions and 499 deletions Side-by-side Diff
drivers/spi/Makefile
drivers/spi/ftssp010_spi.c
@@ -28,7 +28,6 @@
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
-obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
-/*
- * (C) Copyright 2013
- * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
- * Kuo-Jung Su <dantesu@gmail.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/compat.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <spi.h>
-
-#ifndef CONFIG_FTSSP010_BASE_LIST
-#define CONFIG_FTSSP010_BASE_LIST   { CONFIG_FTSSP010_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_BASE
-#define CONFIG_FTSSP010_GPIO_BASE   0
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_LIST
-#define CONFIG_FTSSP010_GPIO_LIST   { CONFIG_FTSSP010_GPIO_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_CLOCK
-#define CONFIG_FTSSP010_CLOCK       clk_get_rate("SSP");
-#endif
-
-#ifndef CONFIG_FTSSP010_TIMEOUT
-#define CONFIG_FTSSP010_TIMEOUT     100
-#endif
-
-/* FTSSP010 chip registers */
-struct ftssp010_regs {
-	uint32_t cr[3];/* control register */
-	uint32_t sr;   /* status register */
-	uint32_t icr;  /* interrupt control register */
-	uint32_t isr;  /* interrupt status register */
-	uint32_t dr;   /* data register */
-	uint32_t rsvd[17];
-	uint32_t revr; /* revision register */
-	uint32_t fear; /* feature register */
-};
-
-/* Control Register 0  */
-#define CR0_FFMT_MASK       (7 << 12)
-#define CR0_FFMT_SSP        (0 << 12)
-#define CR0_FFMT_SPI        (1 << 12)
-#define CR0_FFMT_MICROWIRE  (2 << 12)
-#define CR0_FFMT_I2S        (3 << 12)
-#define CR0_FFMT_AC97       (4 << 12)
-#define CR0_FLASH           (1 << 11)
-#define CR0_FSDIST(x)       (((x) & 0x03) << 8)
-#define CR0_LOOP            (1 << 7)  /* loopback mode */
-#define CR0_LSB             (1 << 6)  /* LSB */
-#define CR0_FSPO            (1 << 5)  /* fs atcive low (I2S only) */
-#define CR0_FSJUSTIFY       (1 << 4)
-#define CR0_OPM_SLAVE       (0 << 2)
-#define CR0_OPM_MASTER      (3 << 2)
-#define CR0_OPM_I2S_MSST    (3 << 2)  /* master stereo mode */
-#define CR0_OPM_I2S_MSMO    (2 << 2)  /* master mono mode */
-#define CR0_OPM_I2S_SLST    (1 << 2)  /* slave stereo mode */
-#define CR0_OPM_I2S_SLMO    (0 << 2)  /* slave mono mode */
-#define CR0_SCLKPO          (1 << 1)  /* clock polarity */
-#define CR0_SCLKPH          (1 << 0)  /* clock phase */
-
-/* Control Register 1 */
-#define CR1_PDL(x)   (((x) & 0xff) << 24) /* padding length */
-#define CR1_SDL(x)   ((((x) - 1) & 0x1f) << 16) /* data length */
-#define CR1_DIV(x)   (((x) - 1) & 0xffff) /* clock divider */
-
-/* Control Register 2 */
-#define CR2_CS(x)    (((x) & 3) << 10) /* CS/FS select */
-#define CR2_FS       (1 << 9) /* CS/FS signal level */
-#define CR2_TXEN     (1 << 8) /* tx enable */
-#define CR2_RXEN     (1 << 7) /* rx enable */
-#define CR2_RESET    (1 << 6) /* chip reset */
-#define CR2_TXFC     (1 << 3) /* tx fifo Clear */
-#define CR2_RXFC     (1 << 2) /* rx fifo Clear */
-#define CR2_TXDOE    (1 << 1) /* tx data output enable */
-#define CR2_EN       (1 << 0) /* chip enable */
-
-/* Status Register */
-#define SR_RFF       (1 << 0) /* rx fifo full */
-#define SR_TFNF      (1 << 1) /* tx fifo not full */
-#define SR_BUSY      (1 << 2) /* chip busy */
-#define SR_RFVE(reg) (((reg) >> 4) & 0x1f)  /* rx fifo valid entries */
-#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
-
-/* Feature Register */
-#define FEAR_BITS(reg)   ((((reg) >>  0) & 0xff) + 1) /* data width */
-#define FEAR_RFSZ(reg)   ((((reg) >>  8) & 0xff) + 1) /* rx fifo size */
-#define FEAR_TFSZ(reg)   ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
-#define FEAR_AC97        (1 << 24)
-#define FEAR_I2S         (1 << 25)
-#define FEAR_SPI_MWR     (1 << 26)
-#define FEAR_SSP         (1 << 27)
-#define FEAR_SPDIF       (1 << 28)
-
-/* FTGPIO010 chip registers */
-struct ftgpio010_regs {
-	uint32_t out;     /* 0x00: Data Output */
-	uint32_t in;      /* 0x04: Data Input */
-	uint32_t dir;     /* 0x08: Direction */
-	uint32_t bypass;  /* 0x0c: Bypass */
-	uint32_t set;     /* 0x10: Data Set */
-	uint32_t clr;     /* 0x14: Data Clear */
-	uint32_t pull_up; /* 0x18: Pull-Up Enabled */
-	uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
-};
-
-struct ftssp010_gpio {
-	struct ftgpio010_regs *regs;
-	uint32_t pin;
-};
-
-struct ftssp010_spi {
-	struct spi_slave slave;
-	struct ftssp010_gpio gpio;
-	struct ftssp010_regs *regs;
-	uint32_t fifo;
-	uint32_t mode;
-	uint32_t div;
-	uint32_t clk;
-	uint32_t speed;
-	uint32_t revision;
-};
-
-static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct ftssp010_spi, slave);
-}
-
-static int get_spi_chip(int bus, struct ftssp010_spi *chip)
-{
-	uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
-
-	if (bus >= ARRAY_SIZE(base) || !base[bus])
-		return -1;
-
-	chip->regs = (struct ftssp010_regs *)base[bus];
-
-	chip->revision = readl(&chip->regs->revr);
-
-	fear = readl(&chip->regs->fear);
-	chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
-
-	return 0;
-}
-
-static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
-{
-	uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
-
-	if (bus >= ARRAY_SIZE(base) || !base[bus])
-		return -1;
-
-	chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
-	chip->pin = base[bus] & 0x1f;
-
-	/* make it an output pin */
-	setbits_le32(&chip->regs->dir, 1 << chip->pin);
-
-	return 0;
-}
-
-static int ftssp010_wait(struct ftssp010_spi *chip)
-{
-	struct ftssp010_regs *regs = chip->regs;
-	ulong t;
-
-	/* wait until device idle */
-	for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
-		if (!(readl(&regs->sr) & SR_BUSY))
-			return 0;
-	}
-
-	puts("ftspi010: busy timeout\n");
-
-	return -1;
-}
-
-static int ftssp010_wait_tx(struct ftssp010_spi *chip)
-{
-	struct ftssp010_regs *regs = chip->regs;
-	ulong t;
-
-	/* wait until tx fifo not full */
-	for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
-		if (readl(&regs->sr) & SR_TFNF)
-			return 0;
-	}
-
-	puts("ftssp010: tx timeout\n");
-
-	return -1;
-}
-
-static int ftssp010_wait_rx(struct ftssp010_spi *chip)
-{
-	struct ftssp010_regs *regs = chip->regs;
-	ulong t;
-
-	/* wait until rx fifo not empty */
-	for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
-		if (SR_RFVE(readl(&regs->sr)))
-			return 0;
-	}
-
-	puts("ftssp010: rx timeout\n");
-
-	return -1;
-}
-
-static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
-	const void *tx_buf, void *rx_buf, int len, uint flags)
-{
-	struct ftssp010_regs *regs = chip->regs;
-	const uint8_t *txb = tx_buf;
-	uint8_t       *rxb = rx_buf;
-
-	while (len > 0) {
-		int i, depth = min(chip->fifo >> 2, len);
-		uint32_t xmsk = 0;
-
-		if (tx_buf) {
-			for (i = 0; i < depth; ++i) {
-				ftssp010_wait_tx(chip);
-				writel(*txb++, &regs->dr);
-			}
-			xmsk |= CR2_TXEN | CR2_TXDOE;
-			if ((readl(&regs->cr[2]) & xmsk) != xmsk)
-				setbits_le32(&regs->cr[2], xmsk);
-		}
-		if (rx_buf) {
-			xmsk |= CR2_RXEN;
-			if ((readl(&regs->cr[2]) & xmsk) != xmsk)
-				setbits_le32(&regs->cr[2], xmsk);
-			for (i = 0; i < depth; ++i) {
-				ftssp010_wait_rx(chip);
-				*rxb++ = (uint8_t)readl(&regs->dr);
-			}
-		}
-
-		len -= depth;
-	}
-
-	return 0;
-}
-
-static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
-	const void *tx_buf, void *rx_buf, int len, uint flags)
-{
-	struct ftssp010_regs *regs = chip->regs;
-	const uint8_t *txb = tx_buf;
-	uint8_t       *rxb = rx_buf;
-
-	while (len > 0) {
-		int i, depth = min(chip->fifo >> 2, len);
-		uint32_t tmp;
-
-		for (i = 0; i < depth; ++i) {
-			ftssp010_wait_tx(chip);
-			writel(txb ? (*txb++) : 0, &regs->dr);
-		}
-		for (i = 0; i < depth; ++i) {
-			ftssp010_wait_rx(chip);
-			tmp = readl(&regs->dr);
-			if (rxb)
-				*rxb++ = (uint8_t)tmp;
-		}
-
-		len -= depth;
-	}
-
-	return 0;
-}
-
-static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
-{
-	struct ftssp010_regs *regs = chip->regs;
-	struct ftssp010_gpio *gpio = &chip->gpio;
-	uint32_t mask;
-
-	/* cs pull high/low */
-	if (chip->revision >= 0x11900) {
-		mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
-		writel(mask, &regs->cr[2]);
-	} else if (gpio->regs) {
-		mask = 1 << gpio->pin;
-		if (high)
-			writel(mask, &gpio->regs->set);
-		else
-			writel(mask, &gpio->regs->clr);
-	}
-
-	/* extra delay for signal propagation */
-	udelay_masked(1);
-}
-
-/*
- * Determine if a SPI chipselect is valid.
- * This function is provided by the board if the low-level SPI driver
- * needs it to determine if a given chipselect is actually valid.
- *
- * Returns: 1 if bus:cs identifies a valid chip on this board, 0
- * otherwise.
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	struct ftssp010_spi chip;
-
-	if (get_spi_chip(bus, &chip))
-		return 0;
-
-	if (!cs)
-		return 1;
-	else if ((cs < 4) && (chip.revision >= 0x11900))
-		return 1;
-
-	return 0;
-}
-
-/*
- * Activate a SPI chipselect.
- * This function is provided by the board code when using a driver
- * that can't control its chipselects automatically (e.g.
- * common/soft_spi.c). When called, it should activate the chip select
- * to the device identified by "slave".
- */
-void spi_cs_activate(struct spi_slave *slave)
-{
-	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-	struct ftssp010_regs *regs = chip->regs;
-
-	/* cs pull */
-	if (chip->mode & SPI_CS_HIGH)
-		ftssp010_cs_set(chip, 1);
-	else
-		ftssp010_cs_set(chip, 0);
-
-	/* chip enable + fifo clear */
-	setbits_le32(&regs->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
-}
-
-/*
- * Deactivate a SPI chipselect.
- * This function is provided by the board code when using a driver
- * that can't control its chipselects automatically (e.g.
- * common/soft_spi.c). When called, it should deactivate the chip
- * select to the device identified by "slave".
- */
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-
-	/* wait until chip idle */
-	ftssp010_wait(chip);
-
-	/* cs pull */
-	if (chip->mode & SPI_CS_HIGH)
-		ftssp010_cs_set(chip, 0);
-	else
-		ftssp010_cs_set(chip, 1);
-}
-
-void spi_init(void)
-{
-	/* nothing to do */
-}
-
-struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
-{
-	struct ftssp010_spi *chip;
-
-	if (mode & SPI_3WIRE) {
-		puts("ftssp010: can't do 3-wire\n");
-		return NULL;
-	}
-
-	if (mode & SPI_SLAVE) {
-		puts("ftssp010: can't do slave mode\n");
-		return NULL;
-	}
-
-	if (mode & SPI_PREAMBLE) {
-		puts("ftssp010: can't skip preamble bytes\n");
-		return NULL;
-	}
-
-	if (!spi_cs_is_valid(bus, cs)) {
-		puts("ftssp010: invalid (bus, cs)\n");
-		return NULL;
-	}
-
-	chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
-	if (!chip)
-		return NULL;
-
-	if (get_spi_chip(bus, chip))
-		goto free_out;
-
-	if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
-		puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
-		"controlled by tx engine which is not synced with rx engine,\n"
-		"so the clock & cs might be shutdown before rx engine\n"
-		"finishs its jobs.\n"
-		"If possible, please add a dedicated gpio for it.\n");
-	}
-
-	chip->mode = mode;
-	chip->clk = CONFIG_FTSSP010_CLOCK;
-	chip->div = 2;
-	if (max_hz) {
-		while (chip->div < 0xffff) {
-			if ((chip->clk / (2 * chip->div)) <= max_hz)
-				break;
-			chip->div += 1;
-		}
-	}
-	chip->speed = chip->clk / (2 * chip->div);
-
-	return &chip->slave;
-
-free_out:
-	free(chip);
-	return NULL;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-
-	free(chip);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-	struct ftssp010_regs *regs = chip->regs;
-
-	writel(CR1_SDL(8) | CR1_DIV(chip->div), &regs->cr[1]);
-
-	if (chip->revision >= 0x11900) {
-		writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
-		       &regs->cr[0]);
-		writel(CR2_TXFC | CR2_RXFC,
-		       &regs->cr[2]);
-	} else {
-		writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
-		       &regs->cr[0]);
-		writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
-		       &regs->cr[2]);
-	}
-
-	if (chip->mode & SPI_LOOP)
-		setbits_le32(&regs->cr[0], CR0_LOOP);
-
-	if (chip->mode & SPI_CPOL)
-		setbits_le32(&regs->cr[0], CR0_SCLKPO);
-
-	if (chip->mode & SPI_CPHA)
-		setbits_le32(&regs->cr[0], CR0_SCLKPH);
-
-	spi_cs_deactivate(slave);
-
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-	struct ftssp010_regs *regs = chip->regs;
-
-	writel(0, &regs->cr[2]);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-			 const void *dout, void *din, unsigned long flags)
-{
-	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
-	uint32_t len = bitlen >> 3;
-
-	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
-
-	if (chip->revision >= 0x11900)
-		ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
-	else
-		ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
-
-	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
-
-	return 0;
-}
...	...	@@ -28,7 +28,6 @@
28	28	obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
29	29	obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
30	30	obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
31		-obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
32	31	obj-$(CONFIG_ICH_SPI) += ich.o
33	32	obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
34	33	obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
1		-/*
2		- * (C) Copyright 2013
3		- * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
4		- * Kuo-Jung Su <dantesu@gmail.com>
5		- *
6		- * SPDX-License-Identifier: GPL-2.0+
7		- */
8		-
9		-#include <common.h>
10		-#include <linux/compat.h>
11		-#include <asm/io.h>
12		-#include <malloc.h>
13		-#include <spi.h>
14		-
15		-#ifndef CONFIG_FTSSP010_BASE_LIST
16		-#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
17		-#endif
18		-
19		-#ifndef CONFIG_FTSSP010_GPIO_BASE
20		-#define CONFIG_FTSSP010_GPIO_BASE 0
21		-#endif
22		-
23		-#ifndef CONFIG_FTSSP010_GPIO_LIST
24		-#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
25		-#endif
26		-
27		-#ifndef CONFIG_FTSSP010_CLOCK
28		-#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP");
29		-#endif
30		-
31		-#ifndef CONFIG_FTSSP010_TIMEOUT
32		-#define CONFIG_FTSSP010_TIMEOUT 100
33		-#endif
34		-
35		-/* FTSSP010 chip registers */
36		-struct ftssp010_regs {
37		- uint32_t cr[3];/* control register */
38		- uint32_t sr; /* status register */
39		- uint32_t icr; /* interrupt control register */
40		- uint32_t isr; /* interrupt status register */
41		- uint32_t dr; /* data register */
42		- uint32_t rsvd[17];
43		- uint32_t revr; /* revision register */
44		- uint32_t fear; /* feature register */
45		-};
46		-
47		-/* Control Register 0 */
48		-#define CR0_FFMT_MASK (7 << 12)
49		-#define CR0_FFMT_SSP (0 << 12)
50		-#define CR0_FFMT_SPI (1 << 12)
51		-#define CR0_FFMT_MICROWIRE (2 << 12)
52		-#define CR0_FFMT_I2S (3 << 12)
53		-#define CR0_FFMT_AC97 (4 << 12)
54		-#define CR0_FLASH (1 << 11)
55		-#define CR0_FSDIST(x) (((x) & 0x03) << 8)
56		-#define CR0_LOOP (1 << 7) /* loopback mode */
57		-#define CR0_LSB (1 << 6) /* LSB */
58		-#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */
59		-#define CR0_FSJUSTIFY (1 << 4)
60		-#define CR0_OPM_SLAVE (0 << 2)
61		-#define CR0_OPM_MASTER (3 << 2)
62		-#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */
63		-#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */
64		-#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */
65		-#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */
66		-#define CR0_SCLKPO (1 << 1) /* clock polarity */
67		-#define CR0_SCLKPH (1 << 0) /* clock phase */
68		-
69		-/* Control Register 1 */
70		-#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */
71		-#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */
72		-#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */
73		-
74		-/* Control Register 2 */
75		-#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */
76		-#define CR2_FS (1 << 9) /* CS/FS signal level */
77		-#define CR2_TXEN (1 << 8) /* tx enable */
78		-#define CR2_RXEN (1 << 7) /* rx enable */
79		-#define CR2_RESET (1 << 6) /* chip reset */
80		-#define CR2_TXFC (1 << 3) /* tx fifo Clear */
81		-#define CR2_RXFC (1 << 2) /* rx fifo Clear */
82		-#define CR2_TXDOE (1 << 1) /* tx data output enable */
83		-#define CR2_EN (1 << 0) /* chip enable */
84		-
85		-/* Status Register */
86		-#define SR_RFF (1 << 0) /* rx fifo full */
87		-#define SR_TFNF (1 << 1) /* tx fifo not full */
88		-#define SR_BUSY (1 << 2) /* chip busy */
89		-#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */
90		-#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
91		-
92		-/* Feature Register */
93		-#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */
94		-#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */
95		-#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
96		-#define FEAR_AC97 (1 << 24)
97		-#define FEAR_I2S (1 << 25)
98		-#define FEAR_SPI_MWR (1 << 26)
99		-#define FEAR_SSP (1 << 27)
100		-#define FEAR_SPDIF (1 << 28)
101		-
102		-/* FTGPIO010 chip registers */
103		-struct ftgpio010_regs {
104		- uint32_t out; /* 0x00: Data Output */
105		- uint32_t in; /* 0x04: Data Input */
106		- uint32_t dir; /* 0x08: Direction */
107		- uint32_t bypass; /* 0x0c: Bypass */
108		- uint32_t set; /* 0x10: Data Set */
109		- uint32_t clr; /* 0x14: Data Clear */
110		- uint32_t pull_up; /* 0x18: Pull-Up Enabled */
111		- uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
112		-};
113		-
114		-struct ftssp010_gpio {
115		- struct ftgpio010_regs *regs;
116		- uint32_t pin;
117		-};
118		-
119		-struct ftssp010_spi {
120		- struct spi_slave slave;
121		- struct ftssp010_gpio gpio;
122		- struct ftssp010_regs *regs;
123		- uint32_t fifo;
124		- uint32_t mode;
125		- uint32_t div;
126		- uint32_t clk;
127		- uint32_t speed;
128		- uint32_t revision;
129		-};
130		-
131		-static inline struct ftssp010_spi to_ftssp010_spi(struct spi_slave slave)
132		-{
133		- return container_of(slave, struct ftssp010_spi, slave);
134		-}
135		-
136		-static int get_spi_chip(int bus, struct ftssp010_spi *chip)
137		-{
138		- uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
139		-
140		- if (bus >= ARRAY_SIZE(base) \|\| !base[bus])
141		- return -1;
142		-
143		- chip->regs = (struct ftssp010_regs *)base[bus];
144		-
145		- chip->revision = readl(&chip->regs->revr);
146		-
147		- fear = readl(&chip->regs->fear);
148		- chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
149		-
150		- return 0;
151		-}
152		-
153		-static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
154		-{
155		- uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
156		-
157		- if (bus >= ARRAY_SIZE(base) \|\| !base[bus])
158		- return -1;
159		-
160		- chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
161		- chip->pin = base[bus] & 0x1f;
162		-
163		- /* make it an output pin */
164		- setbits_le32(&chip->regs->dir, 1 << chip->pin);
165		-
166		- return 0;
167		-}
168		-
169		-static int ftssp010_wait(struct ftssp010_spi *chip)
170		-{
171		- struct ftssp010_regs *regs = chip->regs;
172		- ulong t;
173		-
174		- /* wait until device idle */
175		- for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
176		- if (!(readl(&regs->sr) & SR_BUSY))
177		- return 0;
178		- }
179		-
180		- puts("ftspi010: busy timeout\n");
181		-
182		- return -1;
183		-}
184		-
185		-static int ftssp010_wait_tx(struct ftssp010_spi *chip)
186		-{
187		- struct ftssp010_regs *regs = chip->regs;
188		- ulong t;
189		-
190		- /* wait until tx fifo not full */
191		- for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
192		- if (readl(&regs->sr) & SR_TFNF)
193		- return 0;
194		- }
195		-
196		- puts("ftssp010: tx timeout\n");
197		-
198		- return -1;
199		-}
200		-
201		-static int ftssp010_wait_rx(struct ftssp010_spi *chip)
202		-{
203		- struct ftssp010_regs *regs = chip->regs;
204		- ulong t;
205		-
206		- /* wait until rx fifo not empty */
207		- for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
208		- if (SR_RFVE(readl(&regs->sr)))
209		- return 0;
210		- }
211		-
212		- puts("ftssp010: rx timeout\n");
213		-
214		- return -1;
215		-}
216		-
217		-static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
218		- const void tx_buf, void rx_buf, int len, uint flags)
219		-{
220		- struct ftssp010_regs *regs = chip->regs;
221		- const uint8_t *txb = tx_buf;
222		- uint8_t *rxb = rx_buf;
223		-
224		- while (len > 0) {
225		- int i, depth = min(chip->fifo >> 2, len);
226		- uint32_t xmsk = 0;
227		-
228		- if (tx_buf) {
229		- for (i = 0; i < depth; ++i) {
230		- ftssp010_wait_tx(chip);
231		- writel(*txb++, &regs->dr);
232		- }
233		- xmsk \|= CR2_TXEN \| CR2_TXDOE;
234		- if ((readl(&regs->cr[2]) & xmsk) != xmsk)
235		- setbits_le32(&regs->cr[2], xmsk);
236		- }
237		- if (rx_buf) {
238		- xmsk \|= CR2_RXEN;
239		- if ((readl(&regs->cr[2]) & xmsk) != xmsk)
240		- setbits_le32(&regs->cr[2], xmsk);
241		- for (i = 0; i < depth; ++i) {
242		- ftssp010_wait_rx(chip);
243		- *rxb++ = (uint8_t)readl(&regs->dr);
244		- }
245		- }
246		-
247		- len -= depth;
248		- }
249		-
250		- return 0;
251		-}
252		-
253		-static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
254		- const void tx_buf, void rx_buf, int len, uint flags)
255		-{
256		- struct ftssp010_regs *regs = chip->regs;
257		- const uint8_t *txb = tx_buf;
258		- uint8_t *rxb = rx_buf;
259		-
260		- while (len > 0) {
261		- int i, depth = min(chip->fifo >> 2, len);
262		- uint32_t tmp;
263		-
264		- for (i = 0; i < depth; ++i) {
265		- ftssp010_wait_tx(chip);
266		- writel(txb ? (*txb++) : 0, &regs->dr);
267		- }
268		- for (i = 0; i < depth; ++i) {
269		- ftssp010_wait_rx(chip);
270		- tmp = readl(&regs->dr);
271		- if (rxb)
272		- *rxb++ = (uint8_t)tmp;
273		- }
274		-
275		- len -= depth;
276		- }
277		-
278		- return 0;
279		-}
280		-
281		-static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
282		-{
283		- struct ftssp010_regs *regs = chip->regs;
284		- struct ftssp010_gpio *gpio = &chip->gpio;
285		- uint32_t mask;
286		-
287		- /* cs pull high/low */
288		- if (chip->revision >= 0x11900) {
289		- mask = CR2_CS(chip->slave.cs) \| (high ? CR2_FS : 0);
290		- writel(mask, &regs->cr[2]);
291		- } else if (gpio->regs) {
292		- mask = 1 << gpio->pin;
293		- if (high)
294		- writel(mask, &gpio->regs->set);
295		- else
296		- writel(mask, &gpio->regs->clr);
297		- }
298		-
299		- /* extra delay for signal propagation */
300		- udelay_masked(1);
301		-}
302		-
303		-/*
304		- * Determine if a SPI chipselect is valid.
305		- * This function is provided by the board if the low-level SPI driver
306		- * needs it to determine if a given chipselect is actually valid.
307		- *
308		- * Returns: 1 if bus:cs identifies a valid chip on this board, 0
309		- * otherwise.
310		- */
311		-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
312		-{
313		- struct ftssp010_spi chip;
314		-
315		- if (get_spi_chip(bus, &chip))
316		- return 0;
317		-
318		- if (!cs)
319		- return 1;
320		- else if ((cs < 4) && (chip.revision >= 0x11900))
321		- return 1;
322		-
323		- return 0;
324		-}
325		-
326		-/*
327		- * Activate a SPI chipselect.
328		- * This function is provided by the board code when using a driver
329		- * that can't control its chipselects automatically (e.g.
330		- * common/soft_spi.c). When called, it should activate the chip select
331		- * to the device identified by "slave".
332		- */
333		-void spi_cs_activate(struct spi_slave *slave)
334		-{
335		- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
336		- struct ftssp010_regs *regs = chip->regs;
337		-
338		- /* cs pull */
339		- if (chip->mode & SPI_CS_HIGH)
340		- ftssp010_cs_set(chip, 1);
341		- else
342		- ftssp010_cs_set(chip, 0);
343		-
344		- /* chip enable + fifo clear */
345		- setbits_le32(&regs->cr[2], CR2_EN \| CR2_TXFC \| CR2_RXFC);
346		-}
347		-
348		-/*
349		- * Deactivate a SPI chipselect.
350		- * This function is provided by the board code when using a driver
351		- * that can't control its chipselects automatically (e.g.
352		- * common/soft_spi.c). When called, it should deactivate the chip
353		- * select to the device identified by "slave".
354		- */
355		-void spi_cs_deactivate(struct spi_slave *slave)
356		-{
357		- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
358		-
359		- /* wait until chip idle */
360		- ftssp010_wait(chip);
361		-
362		- /* cs pull */
363		- if (chip->mode & SPI_CS_HIGH)
364		- ftssp010_cs_set(chip, 0);
365		- else
366		- ftssp010_cs_set(chip, 1);
367		-}
368		-
369		-void spi_init(void)
370		-{
371		- /* nothing to do */
372		-}
373		-
374		-struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
375		-{
376		- struct ftssp010_spi *chip;
377		-
378		- if (mode & SPI_3WIRE) {
379		- puts("ftssp010: can't do 3-wire\n");
380		- return NULL;
381		- }
382		-
383		- if (mode & SPI_SLAVE) {
384		- puts("ftssp010: can't do slave mode\n");
385		- return NULL;
386		- }
387		-
388		- if (mode & SPI_PREAMBLE) {
389		- puts("ftssp010: can't skip preamble bytes\n");
390		- return NULL;
391		- }
392		-
393		- if (!spi_cs_is_valid(bus, cs)) {
394		- puts("ftssp010: invalid (bus, cs)\n");
395		- return NULL;
396		- }
397		-
398		- chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
399		- if (!chip)
400		- return NULL;
401		-
402		- if (get_spi_chip(bus, chip))
403		- goto free_out;
404		-
405		- if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
406		- puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
407		- "controlled by tx engine which is not synced with rx engine,\n"
408		- "so the clock & cs might be shutdown before rx engine\n"
409		- "finishs its jobs.\n"
410		- "If possible, please add a dedicated gpio for it.\n");
411		- }
412		-
413		- chip->mode = mode;
414		- chip->clk = CONFIG_FTSSP010_CLOCK;
415		- chip->div = 2;
416		- if (max_hz) {
417		- while (chip->div < 0xffff) {
418		- if ((chip->clk / (2 * chip->div)) <= max_hz)
419		- break;
420		- chip->div += 1;
421		- }
422		- }
423		- chip->speed = chip->clk / (2 * chip->div);
424		-
425		- return &chip->slave;
426		-
427		-free_out:
428		- free(chip);
429		- return NULL;
430		-}
431		-
432		-void spi_free_slave(struct spi_slave *slave)
433		-{
434		- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
435		-
436		- free(chip);
437		-}
438		-
439		-int spi_claim_bus(struct spi_slave *slave)
440		-{
441		- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
442		- struct ftssp010_regs *regs = chip->regs;
443		-
444		- writel(CR1_SDL(8) \| CR1_DIV(chip->div), &regs->cr[1]);
445		-
446		- if (chip->revision >= 0x11900) {
447		- writel(CR0_OPM_MASTER \| CR0_FFMT_SPI \| CR0_FSPO \| CR0_FLASH,
448		- &regs->cr[0]);
449		- writel(CR2_TXFC \| CR2_RXFC,
450		- &regs->cr[2]);
451		- } else {
452		- writel(CR0_OPM_MASTER \| CR0_FFMT_SPI \| CR0_FSPO,
453		- &regs->cr[0]);
454		- writel(CR2_TXFC \| CR2_RXFC \| CR2_EN \| CR2_TXDOE,
455		- &regs->cr[2]);
456		- }
457		-
458		- if (chip->mode & SPI_LOOP)
459		- setbits_le32(&regs->cr[0], CR0_LOOP);
460		-
461		- if (chip->mode & SPI_CPOL)
462		- setbits_le32(&regs->cr[0], CR0_SCLKPO);
463		-
464		- if (chip->mode & SPI_CPHA)
465		- setbits_le32(&regs->cr[0], CR0_SCLKPH);
466		-
467		- spi_cs_deactivate(slave);
468		-
469		- return 0;
470		-}
471		-
472		-void spi_release_bus(struct spi_slave *slave)
473		-{
474		- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
475		- struct ftssp010_regs *regs = chip->regs;
476		-
477		- writel(0, &regs->cr[2]);
478		-}
479		-
480		-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
481		- const void dout, void din, unsigned long flags)
482		-{
483		- struct ftssp010_spi *chip = to_ftssp010_spi(slave);
484		- uint32_t len = bitlen >> 3;
485		-
486		- if (flags & SPI_XFER_BEGIN)
487		- spi_cs_activate(slave);
488		-
489		- if (chip->revision >= 0x11900)
490		- ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
491		- else
492		- ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
493		-
494		- if (flags & SPI_XFER_END)
495		- spi_cs_deactivate(slave);
496		-
497		- return 0;
498		-}