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Commit 4e190b03aaf2309bd2e025d1187a2ca880fedc95

Authored by Haiying Wang
Committed by Scott Wood
1 parent 695c130e4b
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Make Freescale local bus registers available for both 83xx and 85xx. 

- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
  can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
  files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
  85xx can share them.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Showing 12 changed files with 157 additions and 152 deletions Side-by-side Diff

board/freescale/mpc8313erdb/sdram.c
Diff comments   View file @ 4e190b0
... ... @@ -110,7 +110,7 @@
110 110 phys_size_t initdram(int board_type)
111 111 {
112 112 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
113   - volatile lbus83xx_t *lbc = &im->lbus;
  113 + volatile fsl_lbus_t *lbc = &im->lbus;
114 114 u32 msize;
115 115  
116 116 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
board/freescale/mpc8349emds/mpc8349emds.c
Diff comments   View file @ 4e190b0
... ... @@ -192,7 +192,7 @@
192 192 void sdram_init(void)
193 193 {
194 194 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
195   - volatile lbus83xx_t *lbc= &immap->lbus;
  195 + volatile fsl_lbus_t *lbc = &immap->lbus;
196 196 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
197 197  
198 198 /*
board/freescale/mpc8349itx/mpc8349itx.c
Diff comments   View file @ 4e190b0
... ... @@ -221,7 +221,7 @@
221 221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
222 222 };
223 223 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
224   - volatile lbus83xx_t *lbus = &immap->lbus;
  224 + volatile fsl_lbus_t *lbus = &immap->lbus;
225 225  
226 226 lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
227 227 lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
board/freescale/mpc8360emds/mpc8360emds.c
Diff comments   View file @ 4e190b0
... ... @@ -227,7 +227,7 @@
227 227 static int sdram_init(unsigned int base)
228 228 {
229 229 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
230   - volatile lbus83xx_t *lbc = &immap->lbus;
  230 + volatile fsl_lbus_t *lbc = &immap->lbus;
231 231 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
232 232 int rem = base % sdram_size;
233 233 uint *sdram_addr;
board/sbc8349/sbc8349.c
Diff comments   View file @ 4e190b0
... ... @@ -160,7 +160,7 @@
160 160 void sdram_init(void)
161 161 {
162 162 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
163   - volatile lbus83xx_t *lbc= &immap->lbus;
  163 + volatile fsl_lbus_t *lbc = &immap->lbus;
164 164 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
165 165  
166 166 puts("\n SDRAM on Local Bus: ");
... ... @@ -148,7 +148,7 @@
148 148 void upmconfig (uint upm, uint *table, uint size)
149 149 {
150 150 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
151   - volatile lbus83xx_t *lbus = &immap->lbus;
  151 + volatile fsl_lbus_t *lbus = &immap->lbus;
152 152 volatile uchar *dummy = NULL;
153 153 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
154 154 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
drivers/mtd/nand/fsl_elbc_nand.c
Diff comments   View file @ 4e190b0
... ... @@ -75,7 +75,7 @@
75 75 struct fsl_elbc_mtd *chips[MAX_BANKS];
76 76  
77 77 /* device info */
78   - lbus83xx_t *regs;
  78 + fsl_lbus_t *regs;
79 79 u8 __iomem *addr; /* Address of assigned FCM buffer */
80 80 unsigned int page; /* Last page written to / read from */
81 81 unsigned int read_bytes; /* Number of bytes read during command */
... ... @@ -171,7 +171,7 @@
171 171 struct nand_chip *chip = mtd->priv;
172 172 struct fsl_elbc_mtd *priv = chip->priv;
173 173 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
174   - lbus83xx_t *lbc = ctrl->regs;
  174 + fsl_lbus_t *lbc = ctrl->regs;
175 175 int buf_num;
176 176  
177 177 ctrl->page = page_addr;
... ... @@ -211,7 +211,7 @@
211 211 struct nand_chip *chip = mtd->priv;
212 212 struct fsl_elbc_mtd *priv = chip->priv;
213 213 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
214   - lbus83xx_t *lbc = ctrl->regs;
  214 + fsl_lbus_t *lbc = ctrl->regs;
215 215 long long end_tick;
216 216 u32 ltesr;
217 217  
... ... @@ -261,7 +261,7 @@
261 261 {
262 262 struct fsl_elbc_mtd *priv = chip->priv;
263 263 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
264   - lbus83xx_t *lbc = ctrl->regs;
  264 + fsl_lbus_t *lbc = ctrl->regs;
265 265  
266 266 if (priv->page_size) {
267 267 out_be32(&lbc->fir,
... ... @@ -295,7 +295,7 @@
295 295 struct nand_chip *chip = mtd->priv;
296 296 struct fsl_elbc_mtd *priv = chip->priv;
297 297 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
298   - lbus83xx_t *lbc = ctrl->regs;
  298 + fsl_lbus_t *lbc = ctrl->regs;
299 299  
300 300 ctrl->use_mdr = 0;
301 301  
... ... @@ -633,7 +633,7 @@
633 633 {
634 634 struct fsl_elbc_mtd *priv = chip->priv;
635 635 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
636   - lbus83xx_t *lbc = ctrl->regs;
  636 + fsl_lbus_t *lbc = ctrl->regs;
637 637  
638 638 if (ctrl->status != LTESR_CC)
639 639 return NAND_STATUS_FAIL;
640 640  
... ... @@ -693,13 +693,15 @@
693 693  
694 694 static void fsl_elbc_ctrl_init(void)
695 695 {
696   - immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
697   -
698 696 elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
699 697 if (!elbc_ctrl)
700 698 return;
701 699  
702   - elbc_ctrl->regs = &im->lbus;
  700 +#ifdef CONFIG_MPC85xx
  701 + elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
  702 +#else
  703 + elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
  704 +#endif
703 705  
704 706 /* clear event registers */
705 707 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
include/asm-ppc/fsl_lbc.h
Diff comments   View file @ 4e190b0
... ... @@ -307,5 +307,135 @@
307 307 #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
308 308 #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
309 309  
  310 +/* FMR - Flash Mode Register
  311 + */
  312 +#define FMR_CWTO 0x0000F000
  313 +#define FMR_CWTO_SHIFT 12
  314 +#define FMR_BOOT 0x00000800
  315 +#define FMR_ECCM 0x00000100
  316 +#define FMR_AL 0x00000030
  317 +#define FMR_AL_SHIFT 4
  318 +#define FMR_OP 0x00000003
  319 +#define FMR_OP_SHIFT 0
  320 +
  321 +/* FIR - Flash Instruction Register
  322 + */
  323 +#define FIR_OP0 0xF0000000
  324 +#define FIR_OP0_SHIFT 28
  325 +#define FIR_OP1 0x0F000000
  326 +#define FIR_OP1_SHIFT 24
  327 +#define FIR_OP2 0x00F00000
  328 +#define FIR_OP2_SHIFT 20
  329 +#define FIR_OP3 0x000F0000
  330 +#define FIR_OP3_SHIFT 16
  331 +#define FIR_OP4 0x0000F000
  332 +#define FIR_OP4_SHIFT 12
  333 +#define FIR_OP5 0x00000F00
  334 +#define FIR_OP5_SHIFT 8
  335 +#define FIR_OP6 0x000000F0
  336 +#define FIR_OP6_SHIFT 4
  337 +#define FIR_OP7 0x0000000F
  338 +#define FIR_OP7_SHIFT 0
  339 +#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
  340 +#define FIR_OP_CA 0x1 /* Issue current column address */
  341 +#define FIR_OP_PA 0x2 /* Issue current block+page address */
  342 +#define FIR_OP_UA 0x3 /* Issue user defined address */
  343 +#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
  344 +#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
  345 +#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
  346 +#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
  347 +#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
  348 +#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
  349 +#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
  350 +#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
  351 +#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
  352 +#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
  353 +#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
  354 +#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
  355 +
  356 +/* FCR - Flash Command Register
  357 + */
  358 +#define FCR_CMD0 0xFF000000
  359 +#define FCR_CMD0_SHIFT 24
  360 +#define FCR_CMD1 0x00FF0000
  361 +#define FCR_CMD1_SHIFT 16
  362 +#define FCR_CMD2 0x0000FF00
  363 +#define FCR_CMD2_SHIFT 8
  364 +#define FCR_CMD3 0x000000FF
  365 +#define FCR_CMD3_SHIFT 0
  366 +/* FBAR - Flash Block Address Register
  367 + */
  368 +#define FBAR_BLK 0x00FFFFFF
  369 +
  370 +/* FPAR - Flash Page Address Register
  371 + */
  372 +#define FPAR_SP_PI 0x00007C00
  373 +#define FPAR_SP_PI_SHIFT 10
  374 +#define FPAR_SP_MS 0x00000200
  375 +#define FPAR_SP_CI 0x000001FF
  376 +#define FPAR_SP_CI_SHIFT 0
  377 +#define FPAR_LP_PI 0x0003F000
  378 +#define FPAR_LP_PI_SHIFT 12
  379 +#define FPAR_LP_MS 0x00000800
  380 +#define FPAR_LP_CI 0x000007FF
  381 +#define FPAR_LP_CI_SHIFT 0
  382 +
  383 +/* LTESR - Transfer Error Status Register
  384 + */
  385 +#define LTESR_BM 0x80000000
  386 +#define LTESR_FCT 0x40000000
  387 +#define LTESR_PAR 0x20000000
  388 +#define LTESR_WP 0x04000000
  389 +#define LTESR_ATMW 0x00800000
  390 +#define LTESR_ATMR 0x00400000
  391 +#define LTESR_CS 0x00080000
  392 +#define LTESR_CC 0x00000001
  393 +
  394 +#ifndef __ASSEMBLY__
  395 +/*
  396 + * Local Bus Controller Registers.
  397 + */
  398 +typedef struct lbus_bank {
  399 + u32 br; /* Base Register */
  400 + u32 or; /* Option Register */
  401 +} lbus_bank_t;
  402 +
  403 +typedef struct fsl_lbus {
  404 + lbus_bank_t bank[8];
  405 + u8 res0[0x28];
  406 + u32 mar; /* UPM Address Register */
  407 + u8 res1[0x4];
  408 + u32 mamr; /* UPMA Mode Register */
  409 + u32 mbmr; /* UPMB Mode Register */
  410 + u32 mcmr; /* UPMC Mode Register */
  411 + u8 res2[0x8];
  412 + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
  413 + u32 mdr; /* UPM Data Register */
  414 + u8 res3[0x4];
  415 + u32 lsor; /* Special Operation Initiation Register */
  416 + u32 lsdmr; /* SDRAM Mode Register */
  417 + u8 res4[0x8];
  418 + u32 lurt; /* UPM Refresh Timer */
  419 + u32 lsrt; /* SDRAM Refresh Timer */
  420 + u8 res5[0x8];
  421 + u32 ltesr; /* Transfer Error Status Register */
  422 + u32 ltedr; /* Transfer Error Disable Register */
  423 + u32 lteir; /* Transfer Error Interrupt Register */
  424 + u32 lteatr; /* Transfer Error Attributes Register */
  425 + u32 ltear; /* Transfer Error Address Register */
  426 + u8 res6[0xC];
  427 + u32 lbcr; /* Configuration Register */
  428 + u32 lcrr; /* Clock Ratio Register */
  429 + u8 res7[0x8];
  430 + u32 fmr; /* Flash Mode Register */
  431 + u32 fir; /* Flash Instruction Register */
  432 + u32 fcr; /* Flash Command Register */
  433 + u32 fbar; /* Flash Block Addr Register */
  434 + u32 fpar; /* Flash Page Addr Register */
  435 + u32 fbcr; /* Flash Byte Count Register */
  436 + u8 res8[0xF08];
  437 +} fsl_lbus_t;
  438 +#endif /* __ASSEMBLY__ */
  439 +
310 440 #endif /* __ASM_PPC_FSL_LBC_H */
include/asm-ppc/immap_83xx.h
Diff comments   View file @ 4e190b0
... ... @@ -31,6 +31,7 @@
31 31 #include <asm/types.h>
32 32 #include <asm/fsl_i2c.h>
33 33 #include <asm/mpc8xxx_spi.h>
  34 +#include <asm/fsl_lbc.h>
34 35  
35 36 /*
36 37 * Local Access Window
... ... @@ -343,50 +344,6 @@
343 344 } duart83xx_t;
344 345  
345 346 /*
346   - * Local Bus Controller Registers
347   - */
348   -typedef struct lbus_bank {
349   - u32 br; /* Base Register */
350   - u32 or; /* Option Register */
351   -} lbus_bank_t;
352   -
353   -typedef struct lbus83xx {
354   - lbus_bank_t bank[8];
355   - u8 res0[0x28];
356   - u32 mar; /* UPM Address Register */
357   - u8 res1[0x4];
358   - u32 mamr; /* UPMA Mode Register */
359   - u32 mbmr; /* UPMB Mode Register */
360   - u32 mcmr; /* UPMC Mode Register */
361   - u8 res2[0x8];
362   - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
363   - u32 mdr; /* UPM Data Register */
364   - u8 res3[0x4];
365   - u32 lsor; /* Special Operation Initiation Register */
366   - u32 lsdmr; /* SDRAM Mode Register */
367   - u8 res4[0x8];
368   - u32 lurt; /* UPM Refresh Timer */
369   - u32 lsrt; /* SDRAM Refresh Timer */
370   - u8 res5[0x8];
371   - u32 ltesr; /* Transfer Error Status Register */
372   - u32 ltedr; /* Transfer Error Disable Register */
373   - u32 lteir; /* Transfer Error Interrupt Register */
374   - u32 lteatr; /* Transfer Error Attributes Register */
375   - u32 ltear; /* Transfer Error Address Register */
376   - u8 res6[0xC];
377   - u32 lbcr; /* Configuration Register */
378   - u32 lcrr; /* Clock Ratio Register */
379   - u8 res7[0x8];
380   - u32 fmr; /* Flash Mode Register */
381   - u32 fir; /* Flash Instruction Register */
382   - u32 fcr; /* Flash Command Register */
383   - u32 fbar; /* Flash Block Addr Register */
384   - u32 fpar; /* Flash Page Addr Register */
385   - u32 fbcr; /* Flash Byte Count Register */
386   - u8 res8[0xF08];
387   -} lbus83xx_t;
388   -
389   -/*
390 347 * DMA/Messaging Unit
391 348 */
392 349 typedef struct dma83xx {
... ... @@ -614,7 +571,7 @@
614 571 u8 res2[0x1300];
615 572 duart83xx_t duart[2]; /* DUART */
616 573 u8 res3[0x900];
617   - lbus83xx_t lbus; /* Local Bus Controller Registers */
  574 + fsl_lbus_t lbus; /* Local Bus Controller Registers */
618 575 u8 res4[0x1000];
619 576 spi8xxx_t spi; /* Serial Peripheral Interface */
620 577 dma83xx_t dma; /* DMA */
... ... @@ -648,7 +605,7 @@
648 605 u8 res1[0x1300];
649 606 duart83xx_t duart[2]; /* DUART */
650 607 u8 res2[0x900];
651   - lbus83xx_t lbus; /* Local Bus Controller Registers */
  608 + fsl_lbus_t lbus; /* Local Bus Controller Registers */
652 609 u8 res3[0x1000];
653 610 spi8xxx_t spi; /* Serial Peripheral Interface */
654 611 dma83xx_t dma; /* DMA */
... ... @@ -683,7 +640,7 @@
683 640 u8 res1[0x1300];
684 641 duart83xx_t duart[2]; /* DUART */
685 642 u8 res2[0x900];
686   - lbus83xx_t lbus; /* Local Bus Controller Registers */
  643 + fsl_lbus_t lbus; /* Local Bus Controller Registers */
687 644 u8 res3[0x1000];
688 645 spi8xxx_t spi; /* Serial Peripheral Interface */
689 646 dma83xx_t dma; /* DMA */
... ... @@ -728,7 +685,7 @@
728 685 u8 res1[0x1300];
729 686 duart83xx_t duart[2]; /* DUART */
730 687 u8 res2[0x900];
731   - lbus83xx_t lbus; /* Local Bus Controller Registers */
  688 + fsl_lbus_t lbus; /* Local Bus Controller Registers */
732 689 u8 res3[0x1000];
733 690 spi8xxx_t spi; /* Serial Peripheral Interface */
734 691 dma83xx_t dma; /* DMA */
... ... @@ -778,7 +735,7 @@
778 735 u8 res4[0x1300];
779 736 duart83xx_t duart[2]; /* DUART */
780 737 u8 res5[0x900];
781   - lbus83xx_t lbus; /* Local Bus Controller Registers */
  738 + fsl_lbus_t lbus; /* Local Bus Controller Registers */
782 739 u8 res6[0x2000];
783 740 dma83xx_t dma; /* DMA */
784 741 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
... ... @@ -817,7 +774,7 @@
817 774 u8 res3[0x1300];
818 775 duart83xx_t duart[2]; /* DUART */
819 776 u8 res4[0x900];
820   - lbus83xx_t lbus; /* Local Bus Controller Registers */
  777 + fsl_lbus_t lbus; /* Local Bus Controller Registers */
821 778 u8 res5[0x2000];
822 779 dma83xx_t dma; /* DMA */
823 780 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
include/asm-ppc/immap_85xx.h
Diff comments   View file @ 4e190b0
... ... @@ -13,6 +13,7 @@
13 13  
14 14 #include <asm/types.h>
15 15 #include <asm/fsl_i2c.h>
  16 +#include <asm/fsl_lbc.h>
16 17  
17 18 /*
18 19 * Local-Access Registers and ECM Registers(0x0000-0x2000)
... ... @@ -1147,91 +1147,6 @@
1147 1147 */
1148 1148 #define PMCCR1_POWER_OFF 0x00000020
1149 1149  
1150   -/* FMR - Flash Mode Register
1151   - */
1152   -#define FMR_CWTO 0x0000F000
1153   -#define FMR_CWTO_SHIFT 12
1154   -#define FMR_BOOT 0x00000800
1155   -#define FMR_ECCM 0x00000100
1156   -#define FMR_AL 0x00000030
1157   -#define FMR_AL_SHIFT 4
1158   -#define FMR_OP 0x00000003
1159   -#define FMR_OP_SHIFT 0
1160   -
1161   -/* FIR - Flash Instruction Register
1162   - */
1163   -#define FIR_OP0 0xF0000000
1164   -#define FIR_OP0_SHIFT 28
1165   -#define FIR_OP1 0x0F000000
1166   -#define FIR_OP1_SHIFT 24
1167   -#define FIR_OP2 0x00F00000
1168   -#define FIR_OP2_SHIFT 20
1169   -#define FIR_OP3 0x000F0000
1170   -#define FIR_OP3_SHIFT 16
1171   -#define FIR_OP4 0x0000F000
1172   -#define FIR_OP4_SHIFT 12
1173   -#define FIR_OP5 0x00000F00
1174   -#define FIR_OP5_SHIFT 8
1175   -#define FIR_OP6 0x000000F0
1176   -#define FIR_OP6_SHIFT 4
1177   -#define FIR_OP7 0x0000000F
1178   -#define FIR_OP7_SHIFT 0
1179   -#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
1180   -#define FIR_OP_CA 0x1 /* Issue current column address */
1181   -#define FIR_OP_PA 0x2 /* Issue current block+page address */
1182   -#define FIR_OP_UA 0x3 /* Issue user defined address */
1183   -#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
1184   -#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
1185   -#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
1186   -#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
1187   -#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
1188   -#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
1189   -#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
1190   -#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
1191   -#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
1192   -#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
1193   -#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
1194   -#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
1195   -
1196   -/* FCR - Flash Command Register
1197   - */
1198   -#define FCR_CMD0 0xFF000000
1199   -#define FCR_CMD0_SHIFT 24
1200   -#define FCR_CMD1 0x00FF0000
1201   -#define FCR_CMD1_SHIFT 16
1202   -#define FCR_CMD2 0x0000FF00
1203   -#define FCR_CMD2_SHIFT 8
1204   -#define FCR_CMD3 0x000000FF
1205   -#define FCR_CMD3_SHIFT 0
1206   -
1207   -/* FBAR - Flash Block Address Register
1208   - */
1209   -#define FBAR_BLK 0x00FFFFFF
1210   -
1211   -/* FPAR - Flash Page Address Register
1212   - */
1213   -#define FPAR_SP_PI 0x00007C00
1214   -#define FPAR_SP_PI_SHIFT 10
1215   -#define FPAR_SP_MS 0x00000200
1216   -#define FPAR_SP_CI 0x000001FF
1217   -#define FPAR_SP_CI_SHIFT 0
1218   -#define FPAR_LP_PI 0x0003F000
1219   -#define FPAR_LP_PI_SHIFT 12
1220   -#define FPAR_LP_MS 0x00000800
1221   -#define FPAR_LP_CI 0x000007FF
1222   -#define FPAR_LP_CI_SHIFT 0
1223   -
1224   -/* LTESR - Transfer Error Status Register
1225   - */
1226   -#define LTESR_BM 0x80000000
1227   -#define LTESR_FCT 0x40000000
1228   -#define LTESR_PAR 0x20000000
1229   -#define LTESR_WP 0x04000000
1230   -#define LTESR_ATMW 0x00800000
1231   -#define LTESR_ATMR 0x00400000
1232   -#define LTESR_CS 0x00080000
1233   -#define LTESR_CC 0x00000001
1234   -
1235 1150 /* DDRCDR - DDR Control Driver Register
1236 1151 */
1237 1152 #define DDRCDR_DHC_EN 0x80000000
nand_spl/nand_boot_fsl_elbc.c
Diff comments   View file @ 4e190b0
... ... @@ -33,7 +33,7 @@
33 33  
34 34 static void nand_wait(void)
35 35 {
36   - lbus83xx_t *regs = (lbus83xx_t *)(CONFIG_SYS_IMMR + 0x5000);
  36 + fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
37 37  
38 38 for (;;) {
39 39 uint32_t status = in_be32(&regs->ltesr);
... ... @@ -50,7 +50,7 @@
50 50  
51 51 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
52 52 {
53   - lbus83xx_t *regs = (lbus83xx_t *)(CONFIG_SYS_IMMR + 0x5000);
  53 + fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
54 54 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
55 55 int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
56 56 int block_shift = large ? 17 : 14;