mpc5xxx: Add structure definition for several more register blocks.

Signed-off-by: Detlev Zundel <dzu@denx.de>

mpc5xxx: Add structure definition for several more register blocks.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Detlev Zundel · Wolfgang Denk
1 parent 739b0e5946
Showing 1 changed file with 124 additions and 0 deletions Side-by-side Diff
include/mpc5xxx.h
@@ -30,6 +30,8 @@
 #ifndef __ASMPPC_MPC5XXX_H
 #define __ASMPPC_MPC5XXX_H
  
+#include <asm/types.h>
+
 /* Processor name */
 #if defined(CONFIG_MPC5200)
 #define CPU_ID_STR	"MPC5200"
@@ -217,6 +219,12 @@
 #define MPC5XXX_GPIO_SIMPLE_PSC1_1   0x00000002UL
 #define MPC5XXX_GPIO_SIMPLE_PSC1_0   0x00000001UL
  
+#define MPC5XXX_GPIO_SINT_ETH_16     0x80
+#define MPC5XXX_GPIO_SINT_ETH_15     0x40
+#define MPC5XXX_GPIO_SINT_ETH_14     0x20
+#define MPC5XXX_GPIO_SINT_ETH_13     0x10
+#define MPC5XXX_GPIO_SINT_USB1_9     0x08
+#define MPC5XXX_GPIO_SINT_PSC3_8     0x04
 #define MPC5XXX_GPIO_SINT_PSC3_5     0x02
 #define MPC5XXX_GPIO_SINT_PSC3_4     0x01
  
@@ -454,6 +462,99 @@
 							   IORDY protocol */
  
 #ifndef __ASSEMBLY__
+/* Memory map registers */
+struct mpc5xxx_mmap_ctl {
+	volatile u32	mbar;
+	volatile u32	cs0_start;	/* 0x0004 */
+	volatile u32	cs0_stop;
+	volatile u32	cs1_start;	/* 0x000c */
+	volatile u32	cs1_stop;
+	volatile u32	cs2_start;	/* 0x0014 */
+	volatile u32	cs2_stop;
+	volatile u32	cs3_start;	/* 0x001c */
+	volatile u32	cs3_stop;
+	volatile u32	cs4_start;	/* 0x0024 */
+	volatile u32	cs4_stop;
+	volatile u32	cs5_start;	/* 0x002c */
+	volatile u32	cs5_stop;
+#if defined(CONFIG_MGT5100)
+	volatile u32	sdram_start;	/* 0x0034 */
+	volatile u32	sdram_stop;	/* 0x0038 */
+	volatile u32	pci1_start;	/* 0x003c */
+	volatile u32	pci1_stop;	/* 0x0040 */
+	volatile u32	pci2_start;	/* 0x0044 */
+	volatile u32	pci2_stop;	/* 0x0048 */
+#elif defined(CONFIG_MPC5200)
+	volatile u32	sdram0;		/* 0x0034 */
+	volatile u32	sdram1;		/* 0x0038 */
+	volatile u32	dummy1[4];	/* 0x003c */
+#endif
+	volatile u32	boot_start;	/* 0x004c */
+	volatile u32	boot_stop;
+#if defined(CONFIG_MGT5100)
+	volatile u32	addecr;		/* 0x0054 */
+#elif defined(CONFIG_MPC5200)
+	volatile u32	ipbi_ws_ctrl;	/* 0x0054 */
+#endif
+#if defined(CONFIG_MPC5200)
+	volatile u32	cs6_start;	/* 0x0058 */
+	volatile u32	cs6_stop;
+	volatile u32	cs7_start;	/* 0x0060 */
+	volatile u32	cs7_stop;
+#endif
+};
+
+/* Clock distribution module */
+struct mpc5xxx_cdm {
+	volatile u32	jtagid;		/* 0x0000 */
+	volatile u32	porcfg;
+	volatile u32	brdcrmb;	/* 0x0008 */
+	volatile u32	cfg;
+	volatile u32	fourtyeight_fdc;/* 0x0010 */
+	volatile u32	clock_enable;
+	volatile u32	system_osc;	/* 0x0018 */
+	volatile u32	ccscr;
+	volatile u32	sreset;		/* 0x0020 */
+	volatile u32	pll_status;
+	volatile u32	psc1_mccr;	/* 0x0028 */
+	volatile u32	psc2_mccr;
+	volatile u32	psc3_mccr;	/* 0x0030 */
+	volatile u32	psc6_mccr;
+};
+
+/* SDRAM controller */
+struct mpc5xxx_sdram {
+	volatile u32	mode;
+	volatile u32	ctrl;
+	volatile u32	config1;
+	volatile u32	config2;
+#if defined(CONFIG_MGT5100)
+	volatile u32	xlbsel;
+	volatile u32    dummy[31];
+#else
+	volatile u32	dummy[32];
+#endif
+	volatile u32	sdelay;
+};
+
+struct mpc5xxx_lpb {
+	volatile u32	cs0_cfg;
+	volatile u32	cs1_cfg;
+	volatile u32	cs2_cfg;
+	volatile u32	cs3_cfg;
+	volatile u32	cs4_cfg;
+	volatile u32	cs5_cfg;
+	volatile u32	cs_ctrl;
+	volatile u32	cs_status;
+#if defined(CONFIG_MPC5200)
+	volatile u32	cs6_cfg;
+	volatile u32	cs7_cfg;
+	volatile u32	cs_burst;
+	volatile u32	cs_deadcycle;
+#endif
+};
+
+
 struct mpc5xxx_psc {
 	volatile u8	mode;		/* PSC + 0x00 */
 	volatile u8	reserved0[3];
@@ -594,6 +695,29 @@
 	volatile u8 sint_ival;		/* GPIO + 0x3d */
 	volatile u8 bus_errs;		/* GPIO + 0x3e */
 	volatile u8 reserved10;		/* GPIO + 0x3f */
+};
+
+struct mpc5xxx_wu_gpio {
+	volatile u8 enable;		/* WU_GPIO + 0x00 */
+	volatile u8 reserved1[3];	/* WU_GPIO + 0x01 */
+	volatile u8 ode;		/* WU_GPIO + 0x04 */
+	volatile u8 reserved2[3];	/* WU_GPIO + 0x05 */
+	volatile u8 ddr;		/* WU_GPIO + 0x08 */
+	volatile u8 reserved3[3];	/* WU_GPIO + 0x09 */
+	volatile u8 dvo;		/* WU_GPIO + 0x0c */
+	volatile u8 reserved4[3];	/* WU_GPIO + 0x0d */
+	volatile u8 inten;		/* WU_GPIO + 0x10 */
+	volatile u8 reserved5[3];	/* WU_GPIO + 0x11 */
+	volatile u8 iinten;		/* WU_GPIO + 0x14 */
+	volatile u8 reserved6[3];	/* WU_GPIO + 0x15 */
+	volatile u16 itype;		/* WU_GPIO + 0x18 */
+	volatile u8 reserved7[2];	/* WU_GPIO + 0x1a */
+	volatile u8 master_enable;	/* WU_GPIO + 0x1c */
+	volatile u8 reserved8[3];	/* WU_GPIO + 0x1d */
+	volatile u8 ival;		/* WU_GPIO + 0x20 */
+	volatile u8 reserved9[3];	/* WU_GPIO + 0x21 */
+	volatile u8 status;		/* WU_GPIO + 0x24 */
+	volatile u8 reserved10[3];	/* WU_GPIO + 0x25 */
 };
  
 struct mpc5xxx_sdma {
...	...	@@ -30,6 +30,8 @@
30	30	#ifndef __ASMPPC_MPC5XXX_H
31	31	#define __ASMPPC_MPC5XXX_H
32	32
	33	+#include <asm/types.h>
	34	+
33	35	/* Processor name */
34	36	#if defined(CONFIG_MPC5200)
35	37	#define CPU_ID_STR "MPC5200"
...	...	@@ -217,6 +219,12 @@
217	219	#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
218	220	#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
219	221
	222	+#define MPC5XXX_GPIO_SINT_ETH_16 0x80
	223	+#define MPC5XXX_GPIO_SINT_ETH_15 0x40
	224	+#define MPC5XXX_GPIO_SINT_ETH_14 0x20
	225	+#define MPC5XXX_GPIO_SINT_ETH_13 0x10
	226	+#define MPC5XXX_GPIO_SINT_USB1_9 0x08
	227	+#define MPC5XXX_GPIO_SINT_PSC3_8 0x04
220	228	#define MPC5XXX_GPIO_SINT_PSC3_5 0x02
221	229	#define MPC5XXX_GPIO_SINT_PSC3_4 0x01
222	230
...	...	@@ -454,6 +462,99 @@
454	462	IORDY protocol */
455	463
456	464	#ifndef __ASSEMBLY__
	465	+/* Memory map registers */
	466	+struct mpc5xxx_mmap_ctl {
	467	+ volatile u32 mbar;
	468	+ volatile u32 cs0_start; /* 0x0004 */
	469	+ volatile u32 cs0_stop;
	470	+ volatile u32 cs1_start; /* 0x000c */
	471	+ volatile u32 cs1_stop;
	472	+ volatile u32 cs2_start; /* 0x0014 */
	473	+ volatile u32 cs2_stop;
	474	+ volatile u32 cs3_start; /* 0x001c */
	475	+ volatile u32 cs3_stop;
	476	+ volatile u32 cs4_start; /* 0x0024 */
	477	+ volatile u32 cs4_stop;
	478	+ volatile u32 cs5_start; /* 0x002c */
	479	+ volatile u32 cs5_stop;
	480	+#if defined(CONFIG_MGT5100)
	481	+ volatile u32 sdram_start; /* 0x0034 */
	482	+ volatile u32 sdram_stop; /* 0x0038 */
	483	+ volatile u32 pci1_start; /* 0x003c */
	484	+ volatile u32 pci1_stop; /* 0x0040 */
	485	+ volatile u32 pci2_start; /* 0x0044 */
	486	+ volatile u32 pci2_stop; /* 0x0048 */
	487	+#elif defined(CONFIG_MPC5200)
	488	+ volatile u32 sdram0; /* 0x0034 */
	489	+ volatile u32 sdram1; /* 0x0038 */
	490	+ volatile u32 dummy1[4]; /* 0x003c */
	491	+#endif
	492	+ volatile u32 boot_start; /* 0x004c */
	493	+ volatile u32 boot_stop;
	494	+#if defined(CONFIG_MGT5100)
	495	+ volatile u32 addecr; /* 0x0054 */
	496	+#elif defined(CONFIG_MPC5200)
	497	+ volatile u32 ipbi_ws_ctrl; /* 0x0054 */
	498	+#endif
	499	+#if defined(CONFIG_MPC5200)
	500	+ volatile u32 cs6_start; /* 0x0058 */
	501	+ volatile u32 cs6_stop;
	502	+ volatile u32 cs7_start; /* 0x0060 */
	503	+ volatile u32 cs7_stop;
	504	+#endif
	505	+};
	506	+
	507	+/* Clock distribution module */
	508	+struct mpc5xxx_cdm {
	509	+ volatile u32 jtagid; /* 0x0000 */
	510	+ volatile u32 porcfg;
	511	+ volatile u32 brdcrmb; /* 0x0008 */
	512	+ volatile u32 cfg;
	513	+ volatile u32 fourtyeight_fdc;/* 0x0010 */
	514	+ volatile u32 clock_enable;
	515	+ volatile u32 system_osc; /* 0x0018 */
	516	+ volatile u32 ccscr;
	517	+ volatile u32 sreset; /* 0x0020 */
	518	+ volatile u32 pll_status;
	519	+ volatile u32 psc1_mccr; /* 0x0028 */
	520	+ volatile u32 psc2_mccr;
	521	+ volatile u32 psc3_mccr; /* 0x0030 */
	522	+ volatile u32 psc6_mccr;
	523	+};
	524	+
	525	+/* SDRAM controller */
	526	+struct mpc5xxx_sdram {
	527	+ volatile u32 mode;
	528	+ volatile u32 ctrl;
	529	+ volatile u32 config1;
	530	+ volatile u32 config2;
	531	+#if defined(CONFIG_MGT5100)
	532	+ volatile u32 xlbsel;
	533	+ volatile u32 dummy[31];
	534	+#else
	535	+ volatile u32 dummy[32];
	536	+#endif
	537	+ volatile u32 sdelay;
	538	+};
	539	+
	540	+struct mpc5xxx_lpb {
	541	+ volatile u32 cs0_cfg;
	542	+ volatile u32 cs1_cfg;
	543	+ volatile u32 cs2_cfg;
	544	+ volatile u32 cs3_cfg;
	545	+ volatile u32 cs4_cfg;
	546	+ volatile u32 cs5_cfg;
	547	+ volatile u32 cs_ctrl;
	548	+ volatile u32 cs_status;
	549	+#if defined(CONFIG_MPC5200)
	550	+ volatile u32 cs6_cfg;
	551	+ volatile u32 cs7_cfg;
	552	+ volatile u32 cs_burst;
	553	+ volatile u32 cs_deadcycle;
	554	+#endif
	555	+};
	556	+
	557	+
457	558	struct mpc5xxx_psc {
458	559	volatile u8 mode; /* PSC + 0x00 */
459	560	volatile u8 reserved0[3];
...	...	@@ -594,6 +695,29 @@
594	695	volatile u8 sint_ival; /* GPIO + 0x3d */
595	696	volatile u8 bus_errs; /* GPIO + 0x3e */
596	697	volatile u8 reserved10; /* GPIO + 0x3f */
	698	+};
	699	+
	700	+struct mpc5xxx_wu_gpio {
	701	+ volatile u8 enable; /* WU_GPIO + 0x00 */
	702	+ volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */
	703	+ volatile u8 ode; /* WU_GPIO + 0x04 */
	704	+ volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */
	705	+ volatile u8 ddr; /* WU_GPIO + 0x08 */
	706	+ volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */
	707	+ volatile u8 dvo; /* WU_GPIO + 0x0c */
	708	+ volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */
	709	+ volatile u8 inten; /* WU_GPIO + 0x10 */
	710	+ volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */
	711	+ volatile u8 iinten; /* WU_GPIO + 0x14 */
	712	+ volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */
	713	+ volatile u16 itype; /* WU_GPIO + 0x18 */
	714	+ volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */
	715	+ volatile u8 master_enable; /* WU_GPIO + 0x1c */
	716	+ volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */
	717	+ volatile u8 ival; /* WU_GPIO + 0x20 */
	718	+ volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */
	719	+ volatile u8 status; /* WU_GPIO + 0x24 */
	720	+ volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */
597	721	};
598	722
599	723	struct mpc5xxx_sdma {