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Commit 4e736869c6e0df7a955fd000681d6ceea636928c

Authored by Pavel Machek 2014-09-08 20:08:45 +0800

Committed by Marek Vasut 2014-10-06 23:46:49 +0800

Exists in v2017.01-smarct4x and in 37 other branches

arm: socfpga: misc: Add SD controller init

Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 13 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/misc.c

arch/arm/cpu/armv7/socfpga/misc.c

Diff comments View file @ 4e73686

 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/dwmmc.h>
 DECLARE_GLOBAL_DATA_PTR;
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 /*
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_DESIGNWARE_ETH
 int cpu_eth_init(bd_t *bis)
 {
 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
 	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
 	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
 #else
 #error "Incorrect CONFIG_EMAC_BASE value!"
 #endif
 	/* Initialize EMAC. This needs to be done at least once per boot. */
 	/*
 	 * Putting the EMAC controller to reset when configuring the PHY
 	 * interface select at System Manager
 	 */
 	socfpga_emac_reset(1);
 	/* Clearing emac0 PHY interface select to 0 */
 	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
 		     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
 	/* configure to PHY interface select choosed */
 	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
 		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
 	/* Release the EMAC controller from reset */
 	socfpga_emac_reset(0);
 	/* initialize and register the emac */
 	return designware_initialize(CONFIG_EMAC_BASE,
 				     CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
+				  CONFIG_HPS_SDMMC_BUSWIDTH, 0);
 }
 #endif
 #if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
  */
 int print_cpuinfo(void)
 {
 	puts("CPU   : Altera SOCFPGA Platform\n");
 	return 0;
 }
 #endif
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 int overwrite_console(void)
 {
 	return 0;
 }
 #endif
 int arch_cpu_init(void)
 {
 	/*
 	 * If the HW watchdog is NOT enabled, make sure it is not running,
 	 * for example because it was enabled in the preloader. This might
 	 * trigger a watchdog-triggered reboot of Linux kernel later.
 	 */
 #ifndef CONFIG_HW_WATCHDOG
 	socfpga_watchdog_reset();
 #endif
 	return 0;
 }
 int misc_init_r(void)
 {
 	return 0;
 }