arm: socfpga: misc: Add proper ethernet initialization

Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>

arm: socfpga: misc: Add proper ethernet initialization
Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
Pavel Machek · Marek Vasut
1 parent e9d6a20034
Showing 2 changed files with 52 additions and 15 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/misc.c
arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -9,15 +9,58 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
  
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error "Incorrect CONFIG_EMAC_BASE value!"
+#endif
+
+	/* Initialize EMAC. This needs to be done at least once per boot. */
+
+	/*
+	 * Putting the EMAC controller to reset when configuring the PHY
+	 * interface select at System Manager
+	 */
+	socfpga_emac_reset(1);
+
+	/* Clearing emac0 PHY interface select to 0 */
+	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
+
+	/* configure to PHY interface select choosed */
+	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+
+	/* Release the EMAC controller from reset */
+	socfpga_emac_reset(0);
+
+	/* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
@@ -53,20 +96,5 @@
 int misc_init_r(void)
 {
 	return 0;
-}
-
-
-/*
- * DesignWare Ethernet initialization
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
-       /* initialize and register the emac */
-	return designware_initialize(CONFIG_EMAC_BASE,
-				     CONFIG_PHY_INTERFACE_MODE);
-#else
-	return 0;
-#endif
 }
@@ -134,5 +134,14 @@
 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
 	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
  
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
 #endif /* _SYSTEM_MANAGER_H_ */
...	...	@@ -9,15 +9,58 @@
9	9	#include <miiphy.h>
10	10	#include <netdev.h>
11	11	#include <asm/arch/reset_manager.h>
	12	+#include <asm/arch/system_manager.h>
12	13
13	14	DECLARE_GLOBAL_DATA_PTR;
14	15
	16	+static struct socfpga_system_manager *sysmgr_regs =
	17	+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
	18	+
15	19	int dram_init(void)
16	20	{
17	21	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
18	22	return 0;
19	23	}
20	24
	25	+/*
	26	+ * DesignWare Ethernet initialization
	27	+ */
	28	+#ifdef CONFIG_DESIGNWARE_ETH
	29	+int cpu_eth_init(bd_t *bis)
	30	+{
	31	+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
	32	+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
	33	+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
	34	+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
	35	+#else
	36	+#error "Incorrect CONFIG_EMAC_BASE value!"
	37	+#endif
	38	+
	39	+ /* Initialize EMAC. This needs to be done at least once per boot. */
	40	+
	41	+ /*
	42	+ * Putting the EMAC controller to reset when configuring the PHY
	43	+ * interface select at System Manager
	44	+ */
	45	+ socfpga_emac_reset(1);
	46	+
	47	+ /* Clearing emac0 PHY interface select to 0 */
	48	+ clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
	49	+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
	50	+
	51	+ /* configure to PHY interface select choosed */
	52	+ setbits_le32(&sysmgr_regs->emacgrp_ctrl,
	53	+ SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
	54	+
	55	+ /* Release the EMAC controller from reset */
	56	+ socfpga_emac_reset(0);
	57	+
	58	+ /* initialize and register the emac */
	59	+ return designware_initialize(CONFIG_EMAC_BASE,
	60	+ CONFIG_PHY_INTERFACE_MODE);
	61	+}
	62	+#endif
	63	+
21	64	#if defined(CONFIG_DISPLAY_CPUINFO)
22	65	/*
23	66	* Print CPU information
...	...	@@ -53,20 +96,5 @@
53	96	int misc_init_r(void)
54	97	{
55	98	return 0;
56		-}
57		-
58		-
59		-/*
60		- * DesignWare Ethernet initialization
61		- */
62		-int cpu_eth_init(bd_t *bis)
63		-{
64		-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
65		- /* initialize and register the emac */
66		- return designware_initialize(CONFIG_EMAC_BASE,
67		- CONFIG_PHY_INTERFACE_MODE);
68		-#else
69		- return 0;
70		-#endif
71	99	}
...	...	@@ -134,5 +134,14 @@
134	134	#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
135	135	((((drvsel) << 0) & 0x7) \| (((smplsel) << 3) & 0x38))
136	136
	137	+/* EMAC Group Bit definitions */
	138	+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
	139	+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
	140	+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
	141	+
	142	+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
	143	+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
	144	+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
	145	+
137	146	#endif /* _SYSTEM_MANAGER_H_ */