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Commit 4efd69250f6118ebd783867b3809001a1886ce9e

Authored by Marek Vasut
1 parent 67decc71ed
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: pxa: Fix OneNAND window access on VPAC270 

Access the OneNAND 1KiB window on the VPAC270 as an SRAM instead of accessing
it as a burst-RAM. This fixes a problem where the board failed to reboot
sometimes as the CPU couldn't start executing from the OneNAND 1KiB window.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

include/configs/vpac270.h
Diff comments   View file @ 4efd692
1 /* 1 /*
2 * Voipac PXA270 configuration file 2 * Voipac PXA270 configuration file
3 * 3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef __CONFIG_H 9 #ifndef __CONFIG_H
10 #define __CONFIG_H 10 #define __CONFIG_H
11 11
12 /* 12 /*
13 * High Level Board Configuration Options 13 * High Level Board Configuration Options
14 */ 14 */
15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16 #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ 16 #define CONFIG_VPAC270 1 /* Voipac PXA270 board */
17 #define CONFIG_SYS_TEXT_BASE 0xa0000000 17 #define CONFIG_SYS_TEXT_BASE 0xa0000000
18 18
19 #ifdef CONFIG_ONENAND 19 #ifdef CONFIG_ONENAND
20 #define CONFIG_SPL 20 #define CONFIG_SPL
21 #define CONFIG_SPL_ONENAND_SUPPORT 21 #define CONFIG_SPL_ONENAND_SUPPORT
22 #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 22 #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000
23 #define CONFIG_SPL_ONENAND_LOAD_SIZE \ 23 #define CONFIG_SPL_ONENAND_LOAD_SIZE \
24 (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) 24 (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
25 #define CONFIG_SPL_TEXT_BASE 0x5c000000 25 #define CONFIG_SPL_TEXT_BASE 0x5c000000
26 #define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds" 26 #define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds"
27 #endif 27 #endif
28 28
29 /* 29 /*
30 * Environment settings 30 * Environment settings
31 */ 31 */
32 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_ENV_OVERWRITE
33 #define CONFIG_SYS_MALLOC_LEN (128*1024) 33 #define CONFIG_SYS_MALLOC_LEN (128*1024)
34 #define CONFIG_ARCH_CPU_INIT 34 #define CONFIG_ARCH_CPU_INIT
35 #define CONFIG_BOOTCOMMAND \ 35 #define CONFIG_BOOTCOMMAND \
36 "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ 36 "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
37 "bootm 0xa4000000; " \ 37 "bootm 0xa4000000; " \
38 "fi; " \ 38 "fi; " \
39 "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ 39 "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
40 "bootm 0xa4000000; " \ 40 "bootm 0xa4000000; " \
41 "fi; " \ 41 "fi; " \
42 "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ 42 "if ide reset && fatload ide 0 0xa4000000 uImage; then " \
43 "bootm 0xa4000000; " \ 43 "bootm 0xa4000000; " \
44 "fi; " \ 44 "fi; " \
45 "bootm 0x60000;" 45 "bootm 0x60000;"
46 46
47 #define CONFIG_EXTRA_ENV_SETTINGS \ 47 #define CONFIG_EXTRA_ENV_SETTINGS \
48 "update_onenand=" \ 48 "update_onenand=" \
49 "onenand erase 0x0 0x80000 ; " \ 49 "onenand erase 0x0 0x80000 ; " \
50 "onenand write 0xa0000000 0x0 0x80000" 50 "onenand write 0xa0000000 0x0 0x80000"
51 51
52 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" 52 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
53 #define CONFIG_TIMESTAMP 53 #define CONFIG_TIMESTAMP
54 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 54 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */
55 #define CONFIG_CMDLINE_TAG 55 #define CONFIG_CMDLINE_TAG
56 #define CONFIG_SETUP_MEMORY_TAGS 56 #define CONFIG_SETUP_MEMORY_TAGS
57 #define CONFIG_LZMA /* LZMA compression support */ 57 #define CONFIG_LZMA /* LZMA compression support */
58 #define CONFIG_OF_LIBFDT 58 #define CONFIG_OF_LIBFDT
59 59
60 /* 60 /*
61 * Serial Console Configuration 61 * Serial Console Configuration
62 */ 62 */
63 #define CONFIG_PXA_SERIAL 63 #define CONFIG_PXA_SERIAL
64 #define CONFIG_FFUART 1 64 #define CONFIG_FFUART 1
65 #define CONFIG_CONS_INDEX 3 65 #define CONFIG_CONS_INDEX 3
66 #define CONFIG_BAUDRATE 115200 66 #define CONFIG_BAUDRATE 115200
67 67
68 /* 68 /*
69 * Bootloader Components Configuration 69 * Bootloader Components Configuration
70 */ 70 */
71 #include <config_cmd_default.h> 71 #include <config_cmd_default.h>
72 72
73 #define CONFIG_CMD_NET 73 #define CONFIG_CMD_NET
74 #define CONFIG_CMD_ENV 74 #define CONFIG_CMD_ENV
75 #undef CONFIG_CMD_IMLS 75 #undef CONFIG_CMD_IMLS
76 #define CONFIG_CMD_MMC 76 #define CONFIG_CMD_MMC
77 #define CONFIG_CMD_USB 77 #define CONFIG_CMD_USB
78 #undef CONFIG_LCD 78 #undef CONFIG_LCD
79 #define CONFIG_CMD_IDE 79 #define CONFIG_CMD_IDE
80 80
81 #ifdef CONFIG_ONENAND 81 #ifdef CONFIG_ONENAND
82 #undef CONFIG_CMD_FLASH 82 #undef CONFIG_CMD_FLASH
83 #define CONFIG_CMD_ONENAND 83 #define CONFIG_CMD_ONENAND
84 #else 84 #else
85 #define CONFIG_CMD_FLASH 85 #define CONFIG_CMD_FLASH
86 #undef CONFIG_CMD_ONENAND 86 #undef CONFIG_CMD_ONENAND
87 #endif 87 #endif
88 88
89 /* 89 /*
90 * Networking Configuration 90 * Networking Configuration
91 * chip on the Voipac PXA270 board 91 * chip on the Voipac PXA270 board
92 */ 92 */
93 #ifdef CONFIG_CMD_NET 93 #ifdef CONFIG_CMD_NET
94 #define CONFIG_CMD_PING 94 #define CONFIG_CMD_PING
95 #define CONFIG_CMD_DHCP 95 #define CONFIG_CMD_DHCP
96 96
97 #define CONFIG_DRIVER_DM9000 1 97 #define CONFIG_DRIVER_DM9000 1
98 #define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ 98 #define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
99 #define DM9000_IO (CONFIG_DM9000_BASE) 99 #define DM9000_IO (CONFIG_DM9000_BASE)
100 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 100 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
101 #define CONFIG_NET_RETRY_COUNT 10 101 #define CONFIG_NET_RETRY_COUNT 10
102 102
103 #define CONFIG_BOOTP_BOOTFILESIZE 103 #define CONFIG_BOOTP_BOOTFILESIZE
104 #define CONFIG_BOOTP_BOOTPATH 104 #define CONFIG_BOOTP_BOOTPATH
105 #define CONFIG_BOOTP_GATEWAY 105 #define CONFIG_BOOTP_GATEWAY
106 #define CONFIG_BOOTP_HOSTNAME 106 #define CONFIG_BOOTP_HOSTNAME
107 #endif 107 #endif
108 108
109 /* 109 /*
110 * MMC Card Configuration 110 * MMC Card Configuration
111 */ 111 */
112 #ifdef CONFIG_CMD_MMC 112 #ifdef CONFIG_CMD_MMC
113 #define CONFIG_MMC 113 #define CONFIG_MMC
114 #define CONFIG_GENERIC_MMC 114 #define CONFIG_GENERIC_MMC
115 #define CONFIG_PXA_MMC_GENERIC 115 #define CONFIG_PXA_MMC_GENERIC
116 #define CONFIG_SYS_MMC_BASE 0xF0000000 116 #define CONFIG_SYS_MMC_BASE 0xF0000000
117 #define CONFIG_CMD_FAT 117 #define CONFIG_CMD_FAT
118 #define CONFIG_CMD_EXT2 118 #define CONFIG_CMD_EXT2
119 #define CONFIG_DOS_PARTITION 119 #define CONFIG_DOS_PARTITION
120 #endif 120 #endif
121 121
122 /* 122 /*
123 * KGDB 123 * KGDB
124 */ 124 */
125 #ifdef CONFIG_CMD_KGDB 125 #ifdef CONFIG_CMD_KGDB
126 #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ 126 #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
127 #endif 127 #endif
128 128
129 /* 129 /*
130 * HUSH Shell Configuration 130 * HUSH Shell Configuration
131 */ 131 */
132 #define CONFIG_SYS_HUSH_PARSER 1 132 #define CONFIG_SYS_HUSH_PARSER 1
133 133
134 #define CONFIG_SYS_LONGHELP 134 #define CONFIG_SYS_LONGHELP
135 #ifdef CONFIG_SYS_HUSH_PARSER 135 #ifdef CONFIG_SYS_HUSH_PARSER
136 #define CONFIG_SYS_PROMPT "$ " 136 #define CONFIG_SYS_PROMPT "$ "
137 #else 137 #else
138 #endif 138 #endif
139 #define CONFIG_SYS_CBSIZE 256 139 #define CONFIG_SYS_CBSIZE 256
140 #define CONFIG_SYS_PBSIZE \ 140 #define CONFIG_SYS_PBSIZE \
141 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 141 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
142 #define CONFIG_SYS_MAXARGS 16 142 #define CONFIG_SYS_MAXARGS 16
143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
144 #define CONFIG_SYS_DEVICE_NULLDEV 1 144 #define CONFIG_SYS_DEVICE_NULLDEV 1
145 #define CONFIG_CMDLINE_EDITING 1 145 #define CONFIG_CMDLINE_EDITING 1
146 #define CONFIG_AUTO_COMPLETE 1 146 #define CONFIG_AUTO_COMPLETE 1
147 147
148 /* 148 /*
149 * Clock Configuration 149 * Clock Configuration
150 */ 150 */
151 #define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ 151 #define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
152 152
153 153
154 /* 154 /*
155 * DRAM Map 155 * DRAM Map
156 */ 156 */
157 #define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ 157 #define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
158 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 158 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
159 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 159 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
160 160
161 #ifdef CONFIG_RAM_256M 161 #ifdef CONFIG_RAM_256M
162 #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ 162 #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
163 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 163 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
164 #endif 164 #endif
165 165
166 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 166 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
167 #ifdef CONFIG_RAM_256M 167 #ifdef CONFIG_RAM_256M
168 #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ 168 #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
169 #else 169 #else
170 #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ 170 #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
171 #endif 171 #endif
172 172
173 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 173 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
174 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 174 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
175 175
176 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 176 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
178 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 178 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
179 179
180 /* 180 /*
181 * NOR FLASH 181 * NOR FLASH
182 */ 182 */
183 #define CONFIG_SYS_MONITOR_BASE 0x0 183 #define CONFIG_SYS_MONITOR_BASE 0x0
184 #define CONFIG_SYS_MONITOR_LEN 0x80000 184 #define CONFIG_SYS_MONITOR_LEN 0x80000
185 #define CONFIG_ENV_ADDR \ 185 #define CONFIG_ENV_ADDR \
186 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 186 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
187 #define CONFIG_ENV_SIZE 0x20000 187 #define CONFIG_ENV_SIZE 0x20000
188 #define CONFIG_ENV_SECT_SIZE 0x20000 188 #define CONFIG_ENV_SECT_SIZE 0x20000
189 189
190 #if defined(CONFIG_CMD_FLASH) /* NOR */ 190 #if defined(CONFIG_CMD_FLASH) /* NOR */
191 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 191 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
192 192
193 #ifdef CONFIG_RAM_256M 193 #ifdef CONFIG_RAM_256M
194 #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ 194 #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
195 #endif 195 #endif
196 196
197 #define CONFIG_SYS_FLASH_CFI 197 #define CONFIG_SYS_FLASH_CFI
198 #define CONFIG_FLASH_CFI_DRIVER 1 198 #define CONFIG_FLASH_CFI_DRIVER 1
199 199
200 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) 200 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
201 #ifdef CONFIG_RAM_256M 201 #ifdef CONFIG_RAM_256M
202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 202 #define CONFIG_SYS_MAX_FLASH_BANKS 2
203 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } 203 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
204 #else 204 #else
205 #define CONFIG_SYS_MAX_FLASH_BANKS 1 205 #define CONFIG_SYS_MAX_FLASH_BANKS 1
206 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 206 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
207 #endif 207 #endif
208 208
209 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) 209 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
210 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) 210 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
211 211
212 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 212 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
213 #define CONFIG_SYS_FLASH_PROTECTION 1 213 #define CONFIG_SYS_FLASH_PROTECTION 1
214 214
215 #define CONFIG_ENV_IS_IN_FLASH 1 215 #define CONFIG_ENV_IS_IN_FLASH 1
216 216
217 #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ 217 #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
218 #define CONFIG_SYS_NO_FLASH 218 #define CONFIG_SYS_NO_FLASH
219 #define CONFIG_SYS_ONENAND_BASE 0x00000000 219 #define CONFIG_SYS_ONENAND_BASE 0x00000000
220 220
221 #define CONFIG_ENV_IS_IN_ONENAND 1 221 #define CONFIG_ENV_IS_IN_ONENAND 1
222 222
223 #else /* No flash */ 223 #else /* No flash */
224 #define CONFIG_SYS_NO_FLASH 224 #define CONFIG_SYS_NO_FLASH
225 #define CONFIG_SYS_ENV_IS_NOWHERE 225 #define CONFIG_SYS_ENV_IS_NOWHERE
226 #endif 226 #endif
227 227
228 /* 228 /*
229 * IDE 229 * IDE
230 */ 230 */
231 #ifdef CONFIG_CMD_IDE 231 #ifdef CONFIG_CMD_IDE
232 #define CONFIG_LBA48 232 #define CONFIG_LBA48
233 #undef CONFIG_IDE_LED 233 #undef CONFIG_IDE_LED
234 #undef CONFIG_IDE_RESET 234 #undef CONFIG_IDE_RESET
235 235
236 #define __io 236 #define __io
237 237
238 #define CONFIG_SYS_IDE_MAXBUS 1 238 #define CONFIG_SYS_IDE_MAXBUS 1
239 #define CONFIG_SYS_IDE_MAXDEVICE 1 239 #define CONFIG_SYS_IDE_MAXDEVICE 1
240 240
241 #define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 241 #define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
242 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 242 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
243 243
244 #define CONFIG_SYS_ATA_DATA_OFFSET 0x120 244 #define CONFIG_SYS_ATA_DATA_OFFSET 0x120
245 #define CONFIG_SYS_ATA_REG_OFFSET 0x120 245 #define CONFIG_SYS_ATA_REG_OFFSET 0x120
246 #define CONFIG_SYS_ATA_ALT_OFFSET 0x120 246 #define CONFIG_SYS_ATA_ALT_OFFSET 0x120
247 247
248 #define CONFIG_SYS_ATA_STRIDE 2 248 #define CONFIG_SYS_ATA_STRIDE 2
249 #endif 249 #endif
250 250
251 /* 251 /*
252 * GPIO settings 252 * GPIO settings
253 */ 253 */
254 #define CONFIG_SYS_GPSR0_VAL 0x01308800 254 #define CONFIG_SYS_GPSR0_VAL 0x01308800
255 #define CONFIG_SYS_GPSR1_VAL 0x00cf0000 255 #define CONFIG_SYS_GPSR1_VAL 0x00cf0000
256 #define CONFIG_SYS_GPSR2_VAL 0x922ac000 256 #define CONFIG_SYS_GPSR2_VAL 0x922ac000
257 #define CONFIG_SYS_GPSR3_VAL 0x0161e800 257 #define CONFIG_SYS_GPSR3_VAL 0x0161e800
258 258
259 #define CONFIG_SYS_GPCR0_VAL 0x00010000 259 #define CONFIG_SYS_GPCR0_VAL 0x00010000
260 #define CONFIG_SYS_GPCR1_VAL 0x0 260 #define CONFIG_SYS_GPCR1_VAL 0x0
261 #define CONFIG_SYS_GPCR2_VAL 0x0 261 #define CONFIG_SYS_GPCR2_VAL 0x0
262 #define CONFIG_SYS_GPCR3_VAL 0x0 262 #define CONFIG_SYS_GPCR3_VAL 0x0
263 263
264 #define CONFIG_SYS_GPDR0_VAL 0xcbb18800 264 #define CONFIG_SYS_GPDR0_VAL 0xcbb18800
265 #define CONFIG_SYS_GPDR1_VAL 0xfccfa981 265 #define CONFIG_SYS_GPDR1_VAL 0xfccfa981
266 #define CONFIG_SYS_GPDR2_VAL 0x922affff 266 #define CONFIG_SYS_GPDR2_VAL 0x922affff
267 #define CONFIG_SYS_GPDR3_VAL 0x0161e904 267 #define CONFIG_SYS_GPDR3_VAL 0x0161e904
268 268
269 #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 269 #define CONFIG_SYS_GAFR0_L_VAL 0x00100000
270 #define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 270 #define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
271 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a 271 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
272 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa 272 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
273 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 273 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
274 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 274 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
275 #define CONFIG_SYS_GAFR3_L_VAL 0x54010310 275 #define CONFIG_SYS_GAFR3_L_VAL 0x54010310
276 #define CONFIG_SYS_GAFR3_U_VAL 0x00025401 276 #define CONFIG_SYS_GAFR3_U_VAL 0x00025401
277 277
278 #define CONFIG_SYS_PSSR_VAL 0x30 278 #define CONFIG_SYS_PSSR_VAL 0x30
279 279
280 /* 280 /*
281 * Clock settings 281 * Clock settings
282 */ 282 */
283 #define CONFIG_SYS_CKEN 0x00500240 283 #define CONFIG_SYS_CKEN 0x00500240
284 #define CONFIG_SYS_CCCR 0x02000290 284 #define CONFIG_SYS_CCCR 0x02000290
285 285
286 /* 286 /*
287 * Memory settings 287 * Memory settings
288 */ 288 */
289 #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa 289 #define CONFIG_SYS_MSC0_VAL 0x3ffc95f9
290 #define CONFIG_SYS_MSC1_VAL 0x02ccf974 290 #define CONFIG_SYS_MSC1_VAL 0x02ccf974
291 #define CONFIG_SYS_MSC2_VAL 0x00000000 291 #define CONFIG_SYS_MSC2_VAL 0x00000000
292 #ifdef CONFIG_RAM_256M 292 #ifdef CONFIG_RAM_256M
293 #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 293 #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
294 #else 294 #else
295 #define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 295 #define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
296 #endif 296 #endif
297 #define CONFIG_SYS_MDREFR_VAL 0x201fe01e 297 #define CONFIG_SYS_MDREFR_VAL 0x201fe01e
298 #define CONFIG_SYS_MDMRS_VAL 0x00000000 298 #define CONFIG_SYS_MDMRS_VAL 0x00000000
299 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 299 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
300 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 300 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
301 #define CONFIG_SYS_MEM_BUF_IMP 0x0f 301 #define CONFIG_SYS_MEM_BUF_IMP 0x0f
302 302
303 /* 303 /*
304 * PCMCIA and CF Interfaces 304 * PCMCIA and CF Interfaces
305 */ 305 */
306 #define CONFIG_SYS_MECR_VAL 0x00000001 306 #define CONFIG_SYS_MECR_VAL 0x00000001
307 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 307 #define CONFIG_SYS_MCMEM0_VAL 0x00014307
308 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 308 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
309 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 309 #define CONFIG_SYS_MCATT0_VAL 0x0001c787
310 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 310 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
311 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 311 #define CONFIG_SYS_MCIO0_VAL 0x0001430f
312 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 312 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
313 313
314 /* 314 /*
315 * LCD 315 * LCD
316 */ 316 */
317 #ifdef CONFIG_LCD 317 #ifdef CONFIG_LCD
318 #define CONFIG_VOIPAC_LCD 318 #define CONFIG_VOIPAC_LCD
319 #endif 319 #endif
320 320
321 /* 321 /*
322 * USB 322 * USB
323 */ 323 */
324 #ifdef CONFIG_CMD_USB 324 #ifdef CONFIG_CMD_USB
325 #define CONFIG_USB_OHCI_NEW 325 #define CONFIG_USB_OHCI_NEW
326 #define CONFIG_SYS_USB_OHCI_CPU_INIT 326 #define CONFIG_SYS_USB_OHCI_CPU_INIT
327 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 327 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
328 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 328 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
329 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 329 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
330 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" 330 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
331 #define CONFIG_USB_STORAGE 331 #define CONFIG_USB_STORAGE
332 #endif 332 #endif
333 333
334 #endif /* __CONFIG_H */ 334 #endif /* __CONFIG_H */
335 335