Commit 4f68678b1941af7d75f391d1189c776fb434dc08

Authored by Marek Vasut
1 parent 58ec63d6bc

net: dwc: Fix cache alignment issues

Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 4 additions and 2 deletions Side-by-side Diff

drivers/net/designware.c
... ... @@ -303,7 +303,8 @@
303 303  
304 304 /* Flush data to be sent */
305 305 flush_dcache_range((unsigned long)desc_p->dmamac_addr,
306   - (unsigned long)desc_p->dmamac_addr + length);
  306 + (unsigned long)desc_p->dmamac_addr +
  307 + roundup(length, ARCH_DMA_MINALIGN));
307 308  
308 309 #if defined(CONFIG_DW_ALTDESCRIPTOR)
309 310 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
... ... @@ -372,7 +373,8 @@
372 373 /* Flush only status field - others weren't changed */
373 374 flush_dcache_range((unsigned long)&desc_p->txrx_status,
374 375 (unsigned long)&desc_p->txrx_status +
375   - sizeof(desc_p->txrx_status));
  376 + roundup(sizeof(desc_p->txrx_status),
  377 + ARCH_DMA_MINALIGN));
376 378  
377 379 /* Test the wrap-around condition. */
378 380 if (++desc_num >= CONFIG_RX_DESCR_NUM)