imx: mx6sabre common: Factorize the Pfuze init function

Since the Pfuze initializations are similar on various mx6 SABRE boards. Factorize the initialization to a common function in file board/freescale/common/pfuze.c. So that all SABRE boards BSP can share the function. Signed-off-by: Ye.Li <B37916@freescale.com>

imx: mx6sabre common: Factorize the Pfuze init function
Since the Pfuze initializations are similar on various mx6 SABRE boards. Factorize the initialization to a common function in file board/freescale/common/pfuze.c. So that all SABRE boards BSP can share the function. Signed-off-by: Ye.Li <B37916@freescale.com>
Ye.Li · Stefano Babic
1 parent 36523e9b0a
Showing 3 changed files with 67 additions and 0 deletions Side-by-side Diff
board/freescale/common/Makefile
board/freescale/common/pfuze.c
board/freescale/common/pfuze.h
@@ -53,6 +53,7 @@
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
 obj-$(CONFIG_ZM7300)		+= zm7300.o
+obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
  
 # deal with common files for P-series corenet based devices
 obj-$(CONFIG_P2041RDB)	+= p_corenet/
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+struct pmic *pfuze_common_init(unsigned char i2cbus)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(i2cbus);
+	if (ret)
+		return NULL;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return NULL;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return p;
+}
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PFUZE_BOARD_HELPER__
+#define __PFUZE_BOARD_HELPER__
+
+struct pmic *pfuze_common_init(unsigned char i2cbus);
+
+#endif
...	...	@@ -53,6 +53,7 @@
53	53	obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
54	54	obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
55	55	obj-$(CONFIG_ZM7300) += zm7300.o
	56	+obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
56	57
57	58	# deal with common files for P-series corenet based devices
58	59	obj-$(CONFIG_P2041RDB) += p_corenet/
	1	+/*
	2	+ * Copyright 2014 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <power/pmic.h>
	9	+#include <power/pfuze100_pmic.h>
	10	+
	11	+struct pmic *pfuze_common_init(unsigned char i2cbus)
	12	+{
	13	+ struct pmic *p;
	14	+ int ret;
	15	+ unsigned int reg;
	16	+
	17	+ ret = power_pfuze100_init(i2cbus);
	18	+ if (ret)
	19	+ return NULL;
	20	+
	21	+ p = pmic_get("PFUZE100");
	22	+ ret = pmic_probe(p);
	23	+ if (ret)
	24	+ return NULL;
	25	+
	26	+ pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
	27	+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
	28	+
	29	+ /* Set SW1AB stanby volage to 0.975V */
	30	+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
	31	+ reg &= ~SW1x_STBY_MASK;
	32	+ reg \|= SW1x_0_975V;
	33	+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
	34	+
	35	+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	36	+ pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
	37	+ reg &= ~SW1xCONF_DVSSPEED_MASK;
	38	+ reg \|= SW1xCONF_DVSSPEED_4US;
	39	+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
	40	+
	41	+ /* Set SW1C standby voltage to 0.975V */
	42	+ pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
	43	+ reg &= ~SW1x_STBY_MASK;
	44	+ reg \|= SW1x_0_975V;
	45	+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
	46	+
	47	+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
	48	+ pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
	49	+ reg &= ~SW1xCONF_DVSSPEED_MASK;
	50	+ reg \|= SW1xCONF_DVSSPEED_4US;
	51	+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
	52	+
	53	+ return p;
	54	+}