Commit 5066e62847bddf6030262ade2aa3e7bcdc930037
Committed by
York Sun
York Sun
1 parent
373762c34c
Exists in
v2017.01-smarct4x
and in
34 other branches
T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 2 changed files with 16 additions and 0 deletions Side-by-side Diff
drivers/pci/fsl_pci_init.c
| ... | ... | @@ -444,6 +444,21 @@ |
| 444 | 444 | ltssm = (in_be32(&pci->pex_csr0) |
| 445 | 445 | & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; |
| 446 | 446 | enabled = (ltssm == 0x11) ? 1 : 0; |
| 447 | +#ifdef CONFIG_FSL_PCIE_RESET | |
| 448 | + int i; | |
| 449 | + /* assert PCIe reset */ | |
| 450 | + setbits_be32(&pci->pdb_stat, 0x08000000); | |
| 451 | + (void) in_be32(&pci->pdb_stat); | |
| 452 | + udelay(1000); | |
| 453 | + /* clear PCIe reset */ | |
| 454 | + clrbits_be32(&pci->pdb_stat, 0x08000000); | |
| 455 | + asm("sync;isync"); | |
| 456 | + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { | |
| 457 | + pci_hose_read_config_word(hose, dev, PCI_LTSSM, | |
| 458 | + <ssm); | |
| 459 | + udelay(1000); | |
| 460 | + } | |
| 461 | +#endif | |
| 447 | 462 | } else { |
| 448 | 463 | /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ |
| 449 | 464 | /* enabled = ltssm >= PCI_LTSSM_L0; */ |
include/configs/T208xQDS.h
| ... | ... | @@ -575,6 +575,7 @@ |
| 575 | 575 | #define CONFIG_PCIE2 /* PCIE controler 2 */ |
| 576 | 576 | #define CONFIG_PCIE3 /* PCIE controler 3 */ |
| 577 | 577 | #define CONFIG_PCIE4 /* PCIE controler 4 */ |
| 578 | +#define CONFIG_FSL_PCIE_RESET | |
| 578 | 579 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 579 | 580 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 580 | 581 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |