arm: socfpga: Split SoCFPGA configuration

Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Split SoCFPGA configuration
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Pavel Machek · Marek Vasut
1 parent 47f9b4e1f3
Showing 2 changed files with 207 additions and 200 deletions Side-by-side Diff
include/configs/socfpga_common.h
include/configs/socfpga_cyclone5.h
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SOCFPGA
+
+/*
+ * High level configuration
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CLOCKS
+
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x0
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+#define CONFIG_SYS_INIT_SP_ADDR					\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -	\
+	GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Cache
+ */
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * Ethernet on SoC (EMAC)
+ */
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_GIGE
+#endif
+
+/*
+ * FPGA Driver
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_SOCFPGA
+#define CONFIG_FPGA_COUNT		1
+#endif
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE		2400000
+#else
+#define CONFIG_SYS_TIMER_RATE		25000000
+#endif
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
+#endif
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
+/* FIXME */
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
+#endif
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_NS16550_CLK		1000000
+#else
+#define CONFIG_SYS_NS16550_CLK		100000000
+#endif
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * U-Boot environment
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)	/* FIXME */
+#define CONFIG_SYS_SPL_MALLOC_START	((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(&__malloc_end - &__malloc_start)
+
+#define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
 /*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
  
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
 #include "../../board/altera/socfpga/iocsr_config.h"
 #include "../../board/altera/socfpga/pll_config.h"
  
-#define CONFIG_SYS_GENERIC_BOARD
-
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
-#define CONFIG_ARMV7
-#define CONFIG_SYS_THUMB_BUILD
-
-#define CONFIG_SOCFPGA
-
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
 #include <config_cmd_default.h>
  
  
@@ -45,45 +35,9 @@
  
 #define CONFIG_REGEX			/* Enable regular expression support */
  
-/*
- * High level configuration
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_CLOCKS
-
-#define CONFIG_FIT
-#define CONFIG_OF_LIBFDT
-#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * Memory configurations
- */
+/* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x0
-#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
  
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
-#define CONFIG_SYS_INIT_SP_ADDR					\
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -	\
-	GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE		0x08000040
-#else
-#define CONFIG_SYS_TEXT_BASE		0x01000040
-#endif
-
 /* Booting Linux */
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
@@ -96,42 +50,8 @@
 #define CONFIG_LOADADDR		0x8000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
  
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
-#define CONFIG_SYS_PBSIZE	\
-	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-						/* Print buffer size */
-#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-						/* Boot argument buffer size */
-#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
-#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
-#define CONFIG_CMDLINE_EDITING			/* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Cache
- */
-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_SYS_L2_PL310
-#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
-
-/*
- * Ethernet on SoC (EMAC)
- */
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_NET_MULTI
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_MII
-#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_GIGE
-
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
 #define CONFIG_EMAC_BASE		SOCFPGA_EMAC0_ADDRESS
 #define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
 #define CONFIG_EPHY0_PHY_ADDR		0
  
@@ -147,93 +67,9 @@
  
 #endif
  
-/*
- * FPGA Driver
- */
-#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
-#define CONFIG_FPGA_COUNT		1
-#endif
+/* Extra Environment */
+#define CONFIG_HOSTNAME		socfpga_cyclone5
  
-/*
- * L4 OSC1 Timer 0
- */
-/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
-#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE		2400000
-#else
-#define CONFIG_SYS_TIMER_RATE		25000000
-#endif
-
-/*
- * L4 Watchdog
- */
-#ifdef CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
-#define CONFIG_DW_WDT_CLOCK_KHZ		25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
-#endif
-
-/*
- * MMC Driver
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
-#define CONFIG_SOCFPGA_DWMMC
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
-/* FIXME */
-/* using smaller max blk cnt to avoid flooding the limited stack we have */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
-#endif
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_NS16550_CLK		1000000
-#else
-#define CONFIG_SYS_NS16550_CLK		100000000
-#endif
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/*
- * USB
- * Ungate USB:
- * mw 0xffd05014 0x01bef032
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_OTG
-/*#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000*/
-#define CONFIG_USB_DWC2_REG_ADDR 0xffb40000
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * U-Boot environment
- */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_HOSTNAME			socfpga_cyclone5
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  
@@ -257,33 +93,8 @@
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
  
-/*
- * SPL
- */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
-#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)	/* FIXME */
-#define CONFIG_SYS_SPL_MALLOC_START	((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE	(&__malloc_end - &__malloc_start)
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
  
-#define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
-#define CONFIG_CRC32_VERIFY
-
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
-#endif
-
-#endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_H__ */
	1	+/*
	2	+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
	7	+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
	8	+
	9	+#define CONFIG_SYS_GENERIC_BOARD
	10	+
	11	+/* Virtual target or real hardware */
	12	+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
	13	+
	14	+#define CONFIG_ARMV7
	15	+#define CONFIG_SYS_THUMB_BUILD
	16	+
	17	+#define CONFIG_SOCFPGA
	18	+
	19	+/*
	20	+ * High level configuration
	21	+ */
	22	+#define CONFIG_DISPLAY_CPUINFO
	23	+#define CONFIG_DISPLAY_BOARDINFO
	24	+#define CONFIG_BOARD_EARLY_INIT_F
	25	+#define CONFIG_MISC_INIT_R
	26	+#define CONFIG_SYS_NO_FLASH
	27	+#define CONFIG_CLOCKS
	28	+
	29	+#define CONFIG_FIT
	30	+#define CONFIG_OF_LIBFDT
	31	+#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
	32	+
	33	+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	34	+
	35	+/*
	36	+ * Memory configurations
	37	+ */
	38	+#define CONFIG_NR_DRAM_BANKS 1
	39	+#define PHYS_SDRAM_1 0x0
	40	+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	41	+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	42	+#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
	43	+
	44	+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
	45	+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
	46	+#define CONFIG_SYS_INIT_SP_ADDR \
	47	+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
	48	+ GENERATED_GBL_DATA_SIZE)
	49	+
	50	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	51	+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	52	+#define CONFIG_SYS_TEXT_BASE 0x08000040
	53	+#else
	54	+#define CONFIG_SYS_TEXT_BASE 0x01000040
	55	+#endif
	56	+
	57	+/*
	58	+ * U-Boot general configurations
	59	+ */
	60	+#define CONFIG_SYS_LONGHELP
	61	+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
	62	+#define CONFIG_SYS_PBSIZE \
	63	+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	64	+ /* Print buffer size */
	65	+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	66	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	67	+ /* Boot argument buffer size */
	68	+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
	69	+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
	70	+#define CONFIG_CMDLINE_EDITING /* Command history etc */
	71	+#define CONFIG_SYS_HUSH_PARSER
	72	+
	73	+/*
	74	+ * Cache
	75	+ */
	76	+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
	77	+#define CONFIG_SYS_CACHELINE_SIZE 32
	78	+#define CONFIG_SYS_L2_PL310
	79	+#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	80	+
	81	+/*
	82	+ * Ethernet on SoC (EMAC)
	83	+ */
	84	+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
	85	+#define CONFIG_DESIGNWARE_ETH
	86	+#define CONFIG_NET_MULTI
	87	+#define CONFIG_DW_ALTDESCRIPTOR
	88	+#define CONFIG_MII
	89	+#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
	90	+#define CONFIG_PHYLIB
	91	+#define CONFIG_PHY_GIGE
	92	+#endif
	93	+
	94	+/*
	95	+ * FPGA Driver
	96	+ */
	97	+#ifdef CONFIG_CMD_FPGA
	98	+#define CONFIG_FPGA
	99	+#define CONFIG_FPGA_ALTERA
	100	+#define CONFIG_FPGA_SOCFPGA
	101	+#define CONFIG_FPGA_COUNT 1
	102	+#endif
	103	+
	104	+/*
	105	+ * L4 OSC1 Timer 0
	106	+ */
	107	+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
	108	+#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	109	+#define CONFIG_SYS_TIMER_COUNTS_DOWN
	110	+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	111	+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	112	+#define CONFIG_SYS_TIMER_RATE 2400000
	113	+#else
	114	+#define CONFIG_SYS_TIMER_RATE 25000000
	115	+#endif
	116	+
	117	+/*
	118	+ * L4 Watchdog
	119	+ */
	120	+#ifdef CONFIG_HW_WATCHDOG
	121	+#define CONFIG_DESIGNWARE_WATCHDOG
	122	+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	123	+#define CONFIG_DW_WDT_CLOCK_KHZ 25000
	124	+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
	125	+#endif
	126	+
	127	+/*
	128	+ * MMC Driver
	129	+ */
	130	+#ifdef CONFIG_CMD_MMC
	131	+#define CONFIG_MMC
	132	+#define CONFIG_BOUNCE_BUFFER
	133	+#define CONFIG_GENERIC_MMC
	134	+#define CONFIG_DWMMC
	135	+#define CONFIG_SOCFPGA_DWMMC
	136	+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
	137	+#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
	138	+#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
	139	+/* FIXME */
	140	+/* using smaller max blk cnt to avoid flooding the limited stack we have */
	141	+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	142	+#endif
	143	+
	144	+/*
	145	+ * Serial Driver
	146	+ */
	147	+#define CONFIG_SYS_NS16550
	148	+#define CONFIG_SYS_NS16550_SERIAL
	149	+#define CONFIG_SYS_NS16550_REG_SIZE -4
	150	+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
	151	+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	152	+#define CONFIG_SYS_NS16550_CLK 1000000
	153	+#else
	154	+#define CONFIG_SYS_NS16550_CLK 100000000
	155	+#endif
	156	+#define CONFIG_CONS_INDEX 1
	157	+#define CONFIG_BAUDRATE 115200
	158	+
	159	+/*
	160	+ * U-Boot environment
	161	+ */
	162	+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	163	+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	164	+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
	165	+#define CONFIG_ENV_IS_NOWHERE
	166	+#define CONFIG_ENV_SIZE 4096
	167	+
	168	+/*
	169	+ * SPL
	170	+ */
	171	+#define CONFIG_SPL_FRAMEWORK
	172	+#define CONFIG_SPL_BOARD_INIT
	173	+#define CONFIG_SPL_RAM_DEVICE
	174	+#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
	175	+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
	176	+#define CONFIG_SPL_STACK_SIZE (4 * 1024)
	177	+#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
	178	+#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
	179	+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
	180	+
	181	+#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
	182	+#define CONFIG_CRC32_VERIFY
	183	+
	184	+/* Linker script for SPL */
	185	+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
	186	+
	187	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	188	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	189	+#define CONFIG_SPL_WATCHDOG_SUPPORT
	190	+#define CONFIG_SPL_SERIAL_SUPPORT
	191	+
	192	+#ifdef CONFIG_SPL_BUILD
	193	+#undef CONFIG_PARTITIONS
	194	+#endif
	195	+
	196	+#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
1	1	/*
2		- * Copyright (C) 2012 Altera Corporation <www.altera.com>
	2	+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3	3	*
4	4	* SPDX-License-Identifier: GPL-2.0+
5	5	*/
6		-#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
7		-#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
	6	+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
	7	+#define __CONFIG_SOCFPGA_CYCLONE5_H__
8	8
9	9	#include <asm/arch/socfpga_base_addrs.h>
10	10	#include "../../board/altera/socfpga/pinmux_config.h"
11	11	#include "../../board/altera/socfpga/iocsr_config.h"
12	12	#include "../../board/altera/socfpga/pll_config.h"
13	13
14		-#define CONFIG_SYS_GENERIC_BOARD
15		-
16		-/* Virtual target or real hardware */
17		-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
18		-
19		-#define CONFIG_ARMV7
20		-#define CONFIG_SYS_THUMB_BUILD
21		-
22		-#define CONFIG_SOCFPGA
23		-
24	14	/* U-Boot Commands */
25	15	#define CONFIG_SYS_NO_FLASH
26	16	#include <config_cmd_default.h>
27	17
28	18
...	...	@@ -45,45 +35,9 @@
45	35
46	36	#define CONFIG_REGEX /* Enable regular expression support */
47	37
48		-/*
49		- * High level configuration
50		- */
51		-#define CONFIG_DISPLAY_CPUINFO
52		-#define CONFIG_DISPLAY_BOARDINFO
53		-#define CONFIG_BOARD_EARLY_INIT_F
54		-#define CONFIG_MISC_INIT_R
55		-#define CONFIG_SYS_NO_FLASH
56		-#define CONFIG_CLOCKS
57		-
58		-#define CONFIG_FIT
59		-#define CONFIG_OF_LIBFDT
60		-#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
61		-
62		-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
63		-
64		-/*
65		- * Memory configurations
66		- */
	38	+/* Memory configurations */
67	39	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
68		-#define CONFIG_NR_DRAM_BANKS 1
69		-#define PHYS_SDRAM_1 0x0
70		-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
71		-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
72		-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
73	40
74		-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
75		-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
76		-#define CONFIG_SYS_INIT_SP_ADDR \
77		- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
78		- GENERATED_GBL_DATA_SIZE)
79		-
80		-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
81		-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
82		-#define CONFIG_SYS_TEXT_BASE 0x08000040
83		-#else
84		-#define CONFIG_SYS_TEXT_BASE 0x01000040
85		-#endif
86		-
87	41	/* Booting Linux */
88	42	#define CONFIG_BOOTDELAY 3
89	43	#define CONFIG_BOOTFILE "zImage"
...	...	@@ -96,42 +50,8 @@
96	50	#define CONFIG_LOADADDR 0x8000
97	51	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
98	52
99		-/*
100		- * U-Boot general configurations
101		- */
102		-#define CONFIG_SYS_LONGHELP
103		-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
104		-#define CONFIG_SYS_PBSIZE \
105		- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
106		- /* Print buffer size */
107		-#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
108		-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
109		- /* Boot argument buffer size */
110		-#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
111		-#define CONFIG_AUTO_COMPLETE /* Command auto complete */
112		-#define CONFIG_CMDLINE_EDITING /* Command history etc */
113		-#define CONFIG_SYS_HUSH_PARSER
114		-
115		-/*
116		- * Cache
117		- */
118		-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
119		-#define CONFIG_SYS_CACHELINE_SIZE 32
120		-#define CONFIG_SYS_L2_PL310
121		-#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
122		-
123		-/*
124		- * Ethernet on SoC (EMAC)
125		- */
126		-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
127		-#define CONFIG_DESIGNWARE_ETH
128		-#define CONFIG_NET_MULTI
129		-#define CONFIG_DW_ALTDESCRIPTOR
130		-#define CONFIG_MII
131		-#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
132		-#define CONFIG_PHYLIB
133		-#define CONFIG_PHY_GIGE
134		-
	53	+/* Ethernet on SoC (EMAC) */
	54	+#if defined(CONFIG_CMD_NET)
135	55	#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
136	56	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
137	57	#define CONFIG_EPHY0_PHY_ADDR 0
138	58
...	...	@@ -147,93 +67,9 @@
147	67
148	68	#endif
149	69
150		-/*
151		- * FPGA Driver
152		- */
153		-#ifdef CONFIG_CMD_FPGA
154		-#define CONFIG_FPGA
155		-#define CONFIG_FPGA_ALTERA
156		-#define CONFIG_FPGA_SOCFPGA
157		-#define CONFIG_FPGA_COUNT 1
158		-#endif
	70	+/* Extra Environment */
	71	+#define CONFIG_HOSTNAME socfpga_cyclone5
159	72
160		-/*
161		- * L4 OSC1 Timer 0
162		- */
163		-/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
164		-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
165		-#define CONFIG_SYS_TIMER_COUNTS_DOWN
166		-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
167		-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
168		-#define CONFIG_SYS_TIMER_RATE 2400000
169		-#else
170		-#define CONFIG_SYS_TIMER_RATE 25000000
171		-#endif
172		-
173		-/*
174		- * L4 Watchdog
175		- */
176		-#ifdef CONFIG_HW_WATCHDOG
177		-#define CONFIG_DESIGNWARE_WATCHDOG
178		-#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
179		-#define CONFIG_DW_WDT_CLOCK_KHZ 25000
180		-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
181		-#endif
182		-
183		-/*
184		- * MMC Driver
185		- */
186		-#ifdef CONFIG_CMD_MMC
187		-#define CONFIG_MMC
188		-#define CONFIG_BOUNCE_BUFFER
189		-#define CONFIG_GENERIC_MMC
190		-#define CONFIG_DWMMC
191		-#define CONFIG_SOCFPGA_DWMMC
192		-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
193		-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
194		-#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
195		-/* FIXME */
196		-/* using smaller max blk cnt to avoid flooding the limited stack we have */
197		-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
198		-#endif
199		-
200		-/*
201		- * Serial Driver
202		- */
203		-#define CONFIG_SYS_NS16550
204		-#define CONFIG_SYS_NS16550_SERIAL
205		-#define CONFIG_SYS_NS16550_REG_SIZE -4
206		-#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
207		-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
208		-#define CONFIG_SYS_NS16550_CLK 1000000
209		-#else
210		-#define CONFIG_SYS_NS16550_CLK 100000000
211		-#endif
212		-#define CONFIG_CONS_INDEX 1
213		-#define CONFIG_BAUDRATE 115200
214		-
215		-/*
216		- * USB
217		- * Ungate USB:
218		- * mw 0xffd05014 0x01bef032
219		- */
220		-#ifdef CONFIG_CMD_USB
221		-#define CONFIG_USB_DWC2_OTG
222		-/#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000/
223		-#define CONFIG_USB_DWC2_REG_ADDR 0xffb40000
224		-#define CONFIG_USB_STORAGE
225		-#endif
226		-
227		-/*
228		- * U-Boot environment
229		- */
230		-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
231		-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
232		-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
233		-#define CONFIG_ENV_IS_NOWHERE
234		-#define CONFIG_ENV_SIZE 4096
235		-#define CONFIG_HOSTNAME socfpga_cyclone5
236		-
237	73	#define CONFIG_EXTRA_ENV_SETTINGS \
238	74	"verify=n\0" \
239	75	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
240	76
...	...	@@ -257,33 +93,8 @@
257	93	" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
258	94	"bootm ${loadaddr} - ${fdt_addr}\0"
259	95
260		-/*
261		- * SPL
262		- */
263		-#define CONFIG_SPL_FRAMEWORK
264		-#define CONFIG_SPL_BOARD_INIT
265		-#define CONFIG_SPL_RAM_DEVICE
266		-#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
267		-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
268		-#define CONFIG_SPL_STACK_SIZE (4 * 1024)
269		-#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
270		-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
271		-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
	96	+/* The rest of the configuration is shared */
	97	+#include <configs/socfpga_common.h>
272	98
273		-#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
274		-#define CONFIG_CRC32_VERIFY
275		-
276		-/* Linker script for SPL */
277		-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
278		-
279		-#define CONFIG_SPL_LIBCOMMON_SUPPORT
280		-#define CONFIG_SPL_LIBGENERIC_SUPPORT
281		-#define CONFIG_SPL_WATCHDOG_SUPPORT
282		-#define CONFIG_SPL_SERIAL_SUPPORT
283		-
284		-#ifdef CONFIG_SPL_BUILD
285		-#undef CONFIG_PARTITIONS
286		-#endif
287		-
288		-#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
	99	+#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */