Eric Lee / smarc-uboot

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Commit 50a082a88c54975eaa6b6ae39b50936802783387

Authored by Adrian Alonso
Committed by Stefano Babic
1 parent ab09e72866
Exists in v2017.01-smarct4x and in 33 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: imx: imx-common: init: move arch init common setup 

Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>

Showing 5 changed files with 108 additions and 88 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 50a082a
... ... @@ -183,65 +183,6 @@
183 183 }
184 184 #endif
185 185  
186   -void init_aips(void)
187   -{
188   - struct aipstz_regs *aips1, *aips2;
189   -#ifdef CONFIG_MX6SX
190   - struct aipstz_regs *aips3;
191   -#endif
192   -
193   - aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
194   - aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
195   -#ifdef CONFIG_MX6SX
196   - aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
197   -#endif
198   -
199   - /*
200   - * Set all MPROTx to be non-bufferable, trusted for R/W,
201   - * not forced to user-mode.
202   - */
203   - writel(0x77777777, &aips1->mprot0);
204   - writel(0x77777777, &aips1->mprot1);
205   - writel(0x77777777, &aips2->mprot0);
206   - writel(0x77777777, &aips2->mprot1);
207   -
208   - /*
209   - * Set all OPACRx to be non-bufferable, not require
210   - * supervisor privilege level for access,allow for
211   - * write access and untrusted master access.
212   - */
213   - writel(0x00000000, &aips1->opacr0);
214   - writel(0x00000000, &aips1->opacr1);
215   - writel(0x00000000, &aips1->opacr2);
216   - writel(0x00000000, &aips1->opacr3);
217   - writel(0x00000000, &aips1->opacr4);
218   - writel(0x00000000, &aips2->opacr0);
219   - writel(0x00000000, &aips2->opacr1);
220   - writel(0x00000000, &aips2->opacr2);
221   - writel(0x00000000, &aips2->opacr3);
222   - writel(0x00000000, &aips2->opacr4);
223   -
224   -#ifdef CONFIG_MX6SX
225   - /*
226   - * Set all MPROTx to be non-bufferable, trusted for R/W,
227   - * not forced to user-mode.
228   - */
229   - writel(0x77777777, &aips3->mprot0);
230   - writel(0x77777777, &aips3->mprot1);
231   -
232   - /*
233   - * Set all OPACRx to be non-bufferable, not require
234   - * supervisor privilege level for access,allow for
235   - * write access and untrusted master access.
236   - */
237   - writel(0x00000000, &aips3->opacr0);
238   - writel(0x00000000, &aips3->opacr1);
239   - writel(0x00000000, &aips3->opacr2);
240   - writel(0x00000000, &aips3->opacr3);
241   - writel(0x00000000, &aips3->opacr4);
242   -#endif
243   -}
244   -
245 186 static void clear_ldo_ramp(void)
246 187 {
247 188 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
... ... @@ -375,22 +316,6 @@
375 316 }
376 317 #endif
377 318  
378   -#define SRC_SCR_WARM_RESET_ENABLE 0
379   -
380   -static void init_src(void)
381   -{
382   - struct src *src_regs = (struct src *)SRC_BASE_ADDR;
383   - u32 val;
384   -
385   - /*
386   - * force warm reset sources to generate cold reset
387   - * for a more reliable restart
388   - */
389   - val = readl(&src_regs->scr);
390   - val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
391   - writel(val, &src_regs->scr);
392   -}
393   -
394 319 int arch_cpu_init(void)
395 320 {
396 321 init_aips();
... ... @@ -458,18 +383,6 @@
458 383 }
459 384 #endif
460 385  
461   -void boot_mode_apply(unsigned cfg_val)
462   -{
463   - unsigned reg;
464   - struct src *psrc = (struct src *)SRC_BASE_ADDR;
465   - writel(cfg_val, &psrc->gpr9);
466   - reg = readl(&psrc->gpr10);
467   - if (cfg_val)
468   - reg |= 1 << 28;
469   - else
470   - reg &= ~(1 << 28);
471   - writel(reg, &psrc->gpr10);
472   -}
473 386 /*
474 387 * cfg_val will be used for
475 388 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
arch/arm/imx-common/Makefile
Diff comments   View file @ 50a082a
... ... @@ -19,7 +19,7 @@
19 19 obj-$(CONFIG_SPL_BUILD) += spl.o
20 20 endif
21 21 ifeq ($(SOC),$(filter $(SOC),mx6))
22   -obj-y += cache.o
  22 +obj-y += cache.o init.o
23 23 obj-$(CONFIG_CMD_SATA) += sata.o
24 24 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
25 25 endif
arch/arm/imx-common/init.c
Diff comments   View file @ 50a082a
  1 +/*
  2 + * Copyright 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/io.h>
  8 +#include <asm/arch/imx-regs.h>
  9 +#include <asm/arch/clock.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/imx-common/boot_mode.h>
  12 +#include <asm/arch/crm_regs.h>
  13 +
  14 +void init_aips(void)
  15 +{
  16 + struct aipstz_regs *aips1, *aips2;
  17 +#ifdef CONFIG_MX6SX
  18 + struct aipstz_regs *aips3;
  19 +#endif
  20 +
  21 + aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  22 + aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  23 +#ifdef CONFIG_MX6SX
  24 + aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
  25 +#endif
  26 +
  27 + /*
  28 + * Set all MPROTx to be non-bufferable, trusted for R/W,
  29 + * not forced to user-mode.
  30 + */
  31 + writel(0x77777777, &aips1->mprot0);
  32 + writel(0x77777777, &aips1->mprot1);
  33 + writel(0x77777777, &aips2->mprot0);
  34 + writel(0x77777777, &aips2->mprot1);
  35 +
  36 + /*
  37 + * Set all OPACRx to be non-bufferable, not require
  38 + * supervisor privilege level for access,allow for
  39 + * write access and untrusted master access.
  40 + */
  41 + writel(0x00000000, &aips1->opacr0);
  42 + writel(0x00000000, &aips1->opacr1);
  43 + writel(0x00000000, &aips1->opacr2);
  44 + writel(0x00000000, &aips1->opacr3);
  45 + writel(0x00000000, &aips1->opacr4);
  46 + writel(0x00000000, &aips2->opacr0);
  47 + writel(0x00000000, &aips2->opacr1);
  48 + writel(0x00000000, &aips2->opacr2);
  49 + writel(0x00000000, &aips2->opacr3);
  50 + writel(0x00000000, &aips2->opacr4);
  51 +
  52 +#ifdef CONFIG_MX6SX
  53 + /*
  54 + * Set all MPROTx to be non-bufferable, trusted for R/W,
  55 + * not forced to user-mode.
  56 + */
  57 + writel(0x77777777, &aips3->mprot0);
  58 + writel(0x77777777, &aips3->mprot1);
  59 +
  60 + /*
  61 + * Set all OPACRx to be non-bufferable, not require
  62 + * supervisor privilege level for access,allow for
  63 + * write access and untrusted master access.
  64 + */
  65 + writel(0x00000000, &aips3->opacr0);
  66 + writel(0x00000000, &aips3->opacr1);
  67 + writel(0x00000000, &aips3->opacr2);
  68 + writel(0x00000000, &aips3->opacr3);
  69 + writel(0x00000000, &aips3->opacr4);
  70 +#endif
  71 +}
  72 +
  73 +#define SRC_SCR_WARM_RESET_ENABLE 0
  74 +
  75 +void init_src(void)
  76 +{
  77 + struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  78 + u32 val;
  79 +
  80 + /*
  81 + * force warm reset sources to generate cold reset
  82 + * for a more reliable restart
  83 + */
  84 + val = readl(&src_regs->scr);
  85 + val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
  86 + writel(val, &src_regs->scr);
  87 +}
  88 +
  89 +void boot_mode_apply(unsigned cfg_val)
  90 +{
  91 + unsigned reg;
  92 + struct src *psrc = (struct src *)SRC_BASE_ADDR;
  93 + writel(cfg_val, &psrc->gpr9);
  94 + reg = readl(&psrc->gpr10);
  95 + if (cfg_val)
  96 + reg |= 1 << 28;
  97 + else
  98 + reg &= ~(1 << 28);
  99 + writel(reg, &psrc->gpr10);
  100 +}
arch/arm/include/asm/arch-mx6/imx-regs.h
Diff comments   View file @ 50a082a
... ... @@ -137,8 +137,10 @@
137 137 /* Defines for Blocks connected via AIPS (SkyBlue) */
138 138 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
139 139 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
  140 +#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
140 141 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
141 142 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
  143 +#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
142 144  
143 145 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
144 146 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
... ... @@ -219,6 +221,8 @@
219 221  
220 222 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
221 223 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
  224 +#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
  225 +#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
222 226 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
223 227 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
224 228  
arch/arm/include/asm/imx-common/sys_proto.h
Diff comments   View file @ 50a082a
... ... @@ -35,6 +35,9 @@
35 35 void sdelay(unsigned long);
36 36 void set_chipselect_size(int const);
37 37  
  38 +void init_aips(void);
  39 +void init_src(void);
  40 +
38 41 /*
39 42 * Initializes on-chip ethernet controllers.
40 43 * to override, implement board_eth_init()