Eric Lee / smarc-uboot

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Commit 50dcf89d90b3597d86f5d26f131eabc98bbd5209

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent a8cb9d0b17
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc83xx: Add gdsys hrcon board 

The gdsys hrcon board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.

On board peripherals include:
- 1x GbE (optional)
- Lattice ECP3 FPGA connected via eLBC and PCIe

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 18 changed files with 2282 additions and 195 deletions Side-by-side Diff

arch/powerpc/cpu/mpc83xx/Kconfig
Diff comments   View file @ 50dcf89
... ... @@ -68,6 +68,9 @@
68 68 config TARGET_TQM834X
69 69 bool "Support TQM834x"
70 70  
  71 +config TARGET_HRCON
  72 + bool "Support hrcon"
  73 +
71 74 endchoice
72 75  
73 76 source "board/esd/vme8349/Kconfig"
... ... @@ -88,6 +91,7 @@
88 91 source "board/sbc8349/Kconfig"
89 92 source "board/tqc/tqm834x/Kconfig"
90 93 source "board/ve8313/Kconfig"
  94 +source "board/gdsys/mpc8308/Kconfig"
91 95  
92 96 endmenu
board/gdsys/405ep/iocon.c
Diff comments   View file @ 50dcf89
... ... @@ -17,6 +17,7 @@
17 17  
18 18 #include "../common/osd.h"
19 19 #include "../common/mclink.h"
  20 +#include "../common/phy.h"
20 21  
21 22 #include <i2c.h>
22 23 #include <pca953x.h>
... ... @@ -98,8 +99,6 @@
98 99 unsigned int mclink_fpgacount;
99 100 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
100 101  
101   -static int setup_88e1518(const char *bus, unsigned char addr);
102   -
103 102 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
104 103 {
105 104 int res;
... ... @@ -647,191 +646,4 @@
647 646  
648 647 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
649 648 sizeof(bb_miiphy_buses[0]);
650   -
651   -enum {
652   - MIICMD_SET,
653   - MIICMD_MODIFY,
654   - MIICMD_VERIFY_VALUE,
655   - MIICMD_WAIT_FOR_VALUE,
656   -};
657   -
658   -struct mii_setupcmd {
659   - u8 token;
660   - u8 reg;
661   - u16 data;
662   - u16 mask;
663   - u32 timeout;
664   -};
665   -
666   -/*
667   - * verify we are talking to a 88e1518
668   - */
669   -struct mii_setupcmd verify_88e1518[] = {
670   - { MIICMD_SET, 22, 0x0000 },
671   - { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
672   - { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
673   -};
674   -
675   -/*
676   - * workaround for erratum mentioned in 88E1518 release notes
677   - */
678   -struct mii_setupcmd fixup_88e1518[] = {
679   - { MIICMD_SET, 22, 0x00ff },
680   - { MIICMD_SET, 17, 0x214b },
681   - { MIICMD_SET, 16, 0x2144 },
682   - { MIICMD_SET, 17, 0x0c28 },
683   - { MIICMD_SET, 16, 0x2146 },
684   - { MIICMD_SET, 17, 0xb233 },
685   - { MIICMD_SET, 16, 0x214d },
686   - { MIICMD_SET, 17, 0xcc0c },
687   - { MIICMD_SET, 16, 0x2159 },
688   - { MIICMD_SET, 22, 0x00fb },
689   - { MIICMD_SET, 7, 0xc00d },
690   - { MIICMD_SET, 22, 0x0000 },
691   -};
692   -
693   -/*
694   - * default initialization:
695   - * - set RGMII receive timing to "receive clock transition when data stable"
696   - * - set RGMII transmit timing to "transmit clock internally delayed"
697   - * - set RGMII output impedance target to 78,8 Ohm
698   - * - run output impedance calibration
699   - * - set autonegotiation advertise to 1000FD only
700   - */
701   -struct mii_setupcmd default_88e1518[] = {
702   - { MIICMD_SET, 22, 0x0002 },
703   - { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
704   - { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
705   - { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
706   - { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
707   - { MIICMD_SET, 22, 0x0000 },
708   - { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
709   - { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
710   -};
711   -
712   -/*
713   - * turn off CLK125 for PHY daughterboard
714   - */
715   -struct mii_setupcmd ch1fix_88e1518[] = {
716   - { MIICMD_SET, 22, 0x0002 },
717   - { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
718   - { MIICMD_SET, 22, 0x0000 },
719   -};
720   -
721   -/*
722   - * perform copper software reset
723   - */
724   -struct mii_setupcmd swreset_88e1518[] = {
725   - { MIICMD_SET, 22, 0x0000 },
726   - { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
727   - { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
728   -};
729   -
730   -static int process_setupcmd(const char *bus, unsigned char addr,
731   - struct mii_setupcmd *setupcmd)
732   -{
733   - int res;
734   - u8 reg = setupcmd->reg;
735   - u16 data = setupcmd->data;
736   - u16 mask = setupcmd->mask;
737   - u32 timeout = setupcmd->timeout;
738   - u16 orig_data;
739   - unsigned long start;
740   -
741   - debug("mii %s:%u reg %2u ", bus, addr, reg);
742   -
743   - switch (setupcmd->token) {
744   - case MIICMD_MODIFY:
745   - res = miiphy_read(bus, addr, reg, &orig_data);
746   - if (res)
747   - break;
748   - debug("is %04x. (value %04x mask %04x) ", orig_data, data,
749   - mask);
750   - data = (orig_data & ~mask) | (data & mask);
751   - case MIICMD_SET:
752   - debug("=> %04x\n", data);
753   - res = miiphy_write(bus, addr, reg, data);
754   - break;
755   - case MIICMD_VERIFY_VALUE:
756   - res = miiphy_read(bus, addr, reg, &orig_data);
757   - if (res)
758   - break;
759   - if ((orig_data & mask) != (data & mask))
760   - res = -1;
761   - debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
762   - orig_data, res ? "FAIL" : "PASS");
763   - break;
764   - case MIICMD_WAIT_FOR_VALUE:
765   - res = -1;
766   - start = get_timer(0);
767   - while ((res != 0) && (get_timer(start) < timeout)) {
768   - res = miiphy_read(bus, addr, reg, &orig_data);
769   - if (res)
770   - continue;
771   - if ((orig_data & mask) != (data & mask))
772   - res = -1;
773   - }
774   - debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
775   - mask, orig_data, res ? "FAIL" : "PASS",
776   - get_timer(start));
777   - break;
778   - default:
779   - res = -1;
780   - break;
781   - }
782   -
783   - return res;
784   -}
785   -
786   -static int process_setup(const char *bus, unsigned char addr,
787   - struct mii_setupcmd *setupcmd, unsigned int count)
788   -{
789   - int res = 0;
790   - unsigned int k;
791   -
792   - for (k = 0; k < count; ++k) {
793   - res = process_setupcmd(bus, addr, &setupcmd[k]);
794   - if (res) {
795   - printf("mii cmd %u on bus %s addr %u failed, aborting setup",
796   - setupcmd[k].token, bus, addr);
797   - break;
798   - }
799   - }
800   -
801   - return res;
802   -}
803   -
804   -static int setup_88e1518(const char *bus, unsigned char addr)
805   -{
806   - int res;
807   -
808   - res = process_setup(bus, addr,
809   - verify_88e1518, ARRAY_SIZE(verify_88e1518));
810   - if (res)
811   - return res;
812   -
813   - res = process_setup(bus, addr,
814   - fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
815   - if (res)
816   - return res;
817   -
818   - res = process_setup(bus, addr,
819   - default_88e1518, ARRAY_SIZE(default_88e1518));
820   - if (res)
821   - return res;
822   -
823   - if (addr) {
824   - res = process_setup(bus, addr,
825   - ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
826   - if (res)
827   - return res;
828   - }
829   -
830   - res = process_setup(bus, addr,
831   - swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
832   - if (res)
833   - return res;
834   -
835   - return 0;
836   -}
board/gdsys/common/Makefile
Diff comments   View file @ 50dcf89
... ... @@ -6,9 +6,11 @@
6 6 #
7 7  
8 8 obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
  9 +obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
9 10 obj-$(CONFIG_IO) += miiphybb.o
10 11 obj-$(CONFIG_IO64) += miiphybb.o
11   -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
  12 +obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o
12 13 obj-$(CONFIG_DLVISION_10G) += osd.o
13 14 obj-$(CONFIG_CONTROLCENTERD) += dp501.o
  15 +obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o
board/gdsys/common/cmd_ioloop.c
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <command.h>
  10 +
  11 +#include <gdsys_fpga.h>
  12 +
  13 +enum {
  14 + STATE_TX_PACKET_BUILDING = 1<<0,
  15 + STATE_TX_TRANSMITTING = 1<<1,
  16 + STATE_TX_BUFFER_FULL = 1<<2,
  17 + STATE_TX_ERR = 1<<3,
  18 + STATE_RECEIVE_TIMEOUT = 1<<4,
  19 + STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
  20 + STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
  21 + STATE_RX_DIST_ERR = 1<<7,
  22 + STATE_RX_LENGTH_ERR = 1<<8,
  23 + STATE_RX_FRAME_CTR_ERR = 1<<9,
  24 + STATE_RX_FCS_ERR = 1<<10,
  25 + STATE_RX_PACKET_DROPPED = 1<<11,
  26 + STATE_RX_DATA_LAST = 1<<12,
  27 + STATE_RX_DATA_FIRST = 1<<13,
  28 + STATE_RX_DATA_AVAILABLE = 1<<15,
  29 +};
  30 +
  31 +enum {
  32 + CTRL_PROC_RECEIVE_ENABLE = 1<<12,
  33 + CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
  34 +};
  35 +
  36 +enum {
  37 + IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
  38 + IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
  39 + IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
  40 + IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
  41 +};
  42 +
  43 +struct io_generic_packet {
  44 + u16 target_address;
  45 + u16 source_address;
  46 + u8 packet_type;
  47 + u8 bc;
  48 + u16 packet_length;
  49 +} __attribute__((__packed__));
  50 +
  51 +unsigned long long rx_ctr;
  52 +unsigned long long tx_ctr;
  53 +unsigned long long err_ctr;
  54 +
  55 +static void io_check_status(unsigned int fpga, u16 status, bool silent)
  56 +{
  57 + u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
  58 + STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
  59 + STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
  60 +
  61 + if (!(status & mask)) {
  62 + FPGA_SET_REG(fpga, ep.rx_tx_status, status);
  63 + return;
  64 + }
  65 +
  66 + err_ctr++;
  67 + FPGA_SET_REG(fpga, ep.rx_tx_status, status);
  68 +
  69 + if (silent)
  70 + return;
  71 +
  72 + if (status & STATE_RX_PACKET_DROPPED)
  73 + printf("RX_PACKET_DROPPED, status %04x\n", status);
  74 +
  75 + if (status & STATE_RX_DIST_ERR)
  76 + printf("RX_DIST_ERR\n");
  77 + if (status & STATE_RX_LENGTH_ERR)
  78 + printf("RX_LENGTH_ERR\n");
  79 + if (status & STATE_RX_FRAME_CTR_ERR)
  80 + printf("RX_FRAME_CTR_ERR\n");
  81 + if (status & STATE_RX_FCS_ERR)
  82 + printf("RX_FCS_ERR\n");
  83 +
  84 + if (status & STATE_TX_ERR)
  85 + printf("TX_ERR\n");
  86 +}
  87 +
  88 +static void io_send(unsigned int fpga, unsigned int size)
  89 +{
  90 + unsigned int k;
  91 + struct io_generic_packet packet = {
  92 + .source_address = 1,
  93 + .packet_type = 1,
  94 + .packet_length = size,
  95 + };
  96 + u16 *p = (u16 *)&packet;
  97 +
  98 + for (k = 0; k < sizeof(packet) / 2; ++k)
  99 + FPGA_SET_REG(fpga, ep.transmit_data, *p++);
  100 +
  101 + for (k = 0; k < (size + 1) / 2; ++k)
  102 + FPGA_SET_REG(fpga, ep.transmit_data, k);
  103 +
  104 + FPGA_SET_REG(fpga, ep.rx_tx_control,
  105 + CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
  106 +
  107 + tx_ctr++;
  108 +}
  109 +
  110 +static void io_receive(unsigned int fpga)
  111 +{
  112 + unsigned int k = 0;
  113 + u16 rx_tx_status;
  114 +
  115 + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
  116 +
  117 + while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
  118 + u16 rx;
  119 +
  120 + if (rx_tx_status & STATE_RX_DATA_LAST)
  121 + rx_ctr++;
  122 +
  123 + FPGA_GET_REG(fpga, ep.receive_data, &rx);
  124 +
  125 + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
  126 +
  127 + ++k;
  128 + }
  129 +}
  130 +
  131 +static void io_reflect(unsigned int fpga)
  132 +{
  133 + u16 buffer[128];
  134 +
  135 + unsigned int k = 0;
  136 + unsigned int n;
  137 + u16 rx_tx_status;
  138 +
  139 + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
  140 +
  141 + while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
  142 + FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
  143 + if (rx_tx_status & STATE_RX_DATA_LAST)
  144 + break;
  145 +
  146 + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
  147 + }
  148 +
  149 + if (!k)
  150 + return;
  151 +
  152 + for (n = 0; n < k; ++n)
  153 + FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
  154 +
  155 + FPGA_SET_REG(fpga, ep.rx_tx_control,
  156 + CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
  157 +
  158 + tx_ctr++;
  159 +}
  160 +
  161 +/*
  162 + * FPGA io-endpoint reflector
  163 + *
  164 + * Syntax:
  165 + * ioreflect {fpga} {reportrate}
  166 + */
  167 +int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  168 +{
  169 + unsigned int fpga;
  170 + unsigned int rate = 0;
  171 + unsigned long long last_seen = 0;
  172 +
  173 + if (argc < 2)
  174 + return CMD_RET_USAGE;
  175 +
  176 + fpga = simple_strtoul(argv[1], NULL, 10);
  177 +
  178 + /*
  179 + * If another parameter, it is the report rate in packets.
  180 + */
  181 + if (argc > 2)
  182 + rate = simple_strtoul(argv[2], NULL, 10);
  183 +
  184 + /* enable receive path */
  185 + FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
  186 +
  187 + /* set device address to dummy 1*/
  188 + FPGA_SET_REG(fpga, ep.device_address, 1);
  189 +
  190 + rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
  191 +
  192 + while (1) {
  193 + u16 top_int;
  194 + u16 rx_tx_status;
  195 +
  196 + FPGA_GET_REG(fpga, top_interrupt, &top_int);
  197 + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
  198 +
  199 + io_check_status(fpga, rx_tx_status, true);
  200 + if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
  201 + (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
  202 + io_reflect(fpga);
  203 +
  204 + if (rate) {
  205 + if (!(tx_ctr % rate) && (tx_ctr != last_seen))
  206 + printf("refl %llu, err %llu\n", tx_ctr,
  207 + err_ctr);
  208 + last_seen = tx_ctr;
  209 + }
  210 +
  211 + if (ctrlc())
  212 + break;
  213 + }
  214 +
  215 + return 0;
  216 +}
  217 +
  218 +/*
  219 + * FPGA io-endpoint looptest
  220 + *
  221 + * Syntax:
  222 + * ioloop {fpga} {size} {rate}
  223 + */
  224 +#define DISP_LINE_LEN 16
  225 +int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  226 +{
  227 + unsigned int fpga;
  228 + unsigned int size;
  229 + unsigned int rate = 0;
  230 +
  231 + if (argc < 3)
  232 + return CMD_RET_USAGE;
  233 +
  234 + /*
  235 + * FPGA is specified since argc > 2
  236 + */
  237 + fpga = simple_strtoul(argv[1], NULL, 10);
  238 +
  239 + /*
  240 + * packet size is specified since argc > 2
  241 + */
  242 + size = simple_strtoul(argv[2], NULL, 10);
  243 +
  244 + /*
  245 + * If another parameter, it is the test rate in packets per second.
  246 + */
  247 + if (argc > 3)
  248 + rate = simple_strtoul(argv[3], NULL, 10);
  249 +
  250 + /* enable receive path */
  251 + FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
  252 +
  253 + /* set device address to dummy 1*/
  254 + FPGA_SET_REG(fpga, ep.device_address, 1);
  255 +
  256 + rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
  257 +
  258 + while (1) {
  259 + u16 top_int;
  260 + u16 rx_tx_status;
  261 +
  262 + FPGA_GET_REG(fpga, top_interrupt, &top_int);
  263 + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
  264 +
  265 + io_check_status(fpga, rx_tx_status, false);
  266 + if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
  267 + io_send(fpga, size);
  268 + if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
  269 + io_receive(fpga);
  270 +
  271 + if (rate) {
  272 + if (ctrlc())
  273 + break;
  274 + udelay(1000000 / rate);
  275 + if (!(tx_ctr % rate))
  276 + printf("d %lld, tx %llu, rx %llu, err %llu\n",
  277 + tx_ctr - rx_ctr, tx_ctr, rx_ctr,
  278 + err_ctr);
  279 + }
  280 + }
  281 +
  282 + return 0;
  283 +}
  284 +
  285 +U_BOOT_CMD(
  286 + ioloop, 4, 0, do_ioloop,
  287 + "fpga io-endpoint looptest",
  288 + "fpga packetsize [packets/sec]"
  289 +);
  290 +
  291 +U_BOOT_CMD(
  292 + ioreflect, 3, 0, do_ioreflect,
  293 + "fpga io-endpoint reflector",
  294 + "fpga reportrate"
  295 +);
board/gdsys/common/ihs_mdio.c
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +
  10 +#include <gdsys_fpga.h>
  11 +#include <miiphy.h>
  12 +
  13 +#include "ihs_mdio.h"
  14 +
  15 +static int ihs_mdio_idle(struct mii_dev *bus)
  16 +{
  17 + struct ihs_mdio_info *info = bus->priv;
  18 + u16 val;
  19 + unsigned int ctr = 0;
  20 +
  21 + do {
  22 + FPGA_GET_REG(info->fpga, mdio.control, &val);
  23 + udelay(100);
  24 + if (ctr++ > 10)
  25 + return -1;
  26 + } while (!(val & (1 << 12)));
  27 +
  28 + return 0;
  29 +}
  30 +
  31 +static int ihs_mdio_reset(struct mii_dev *bus)
  32 +{
  33 + ihs_mdio_idle(bus);
  34 +
  35 + return 0;
  36 +}
  37 +
  38 +static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
  39 + int regnum)
  40 +{
  41 + struct ihs_mdio_info *info = bus->priv;
  42 + u16 val;
  43 +
  44 + ihs_mdio_idle(bus);
  45 +
  46 + FPGA_SET_REG(info->fpga, mdio.control,
  47 + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
  48 +
  49 + /* wait for rx data available */
  50 + udelay(100);
  51 +
  52 + FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
  53 +
  54 + return val;
  55 +}
  56 +
  57 +static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
  58 + int regnum, u16 value)
  59 +{
  60 + struct ihs_mdio_info *info = bus->priv;
  61 +
  62 + ihs_mdio_idle(bus);
  63 +
  64 + FPGA_SET_REG(info->fpga, mdio.address_data, value);
  65 + FPGA_SET_REG(info->fpga, mdio.control,
  66 + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
  67 +
  68 + return 0;
  69 +}
  70 +
  71 +int ihs_mdio_init(struct ihs_mdio_info *info)
  72 +{
  73 + struct mii_dev *bus = mdio_alloc();
  74 +
  75 + if (!bus) {
  76 + printf("Failed to allocate FSL MDIO bus\n");
  77 + return -1;
  78 + }
  79 +
  80 + bus->read = ihs_mdio_read;
  81 + bus->write = ihs_mdio_write;
  82 + bus->reset = ihs_mdio_reset;
  83 + sprintf(bus->name, info->name);
  84 +
  85 + bus->priv = info;
  86 +
  87 + return mdio_register(bus);
  88 +}
board/gdsys/common/ihs_mdio.h
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _IHS_MDIO_H_
  9 +#define _IHS_MDIO_H_
  10 +
  11 +struct ihs_mdio_info {
  12 + u32 fpga;
  13 + char *name;
  14 +};
  15 +
  16 +int ihs_mdio_init(struct ihs_mdio_info *info);
  17 +
  18 +#endif
board/gdsys/common/phy.c
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +
  10 +#include <miiphy.h>
  11 +
  12 +enum {
  13 + MIICMD_SET,
  14 + MIICMD_MODIFY,
  15 + MIICMD_VERIFY_VALUE,
  16 + MIICMD_WAIT_FOR_VALUE,
  17 +};
  18 +
  19 +struct mii_setupcmd {
  20 + u8 token;
  21 + u8 reg;
  22 + u16 data;
  23 + u16 mask;
  24 + u32 timeout;
  25 +};
  26 +
  27 +/*
  28 + * verify we are talking to a 88e1518
  29 + */
  30 +struct mii_setupcmd verify_88e1518[] = {
  31 + { MIICMD_SET, 22, 0x0000 },
  32 + { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
  33 + { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
  34 +};
  35 +
  36 +/*
  37 + * workaround for erratum mentioned in 88E1518 release notes
  38 + */
  39 +struct mii_setupcmd fixup_88e1518[] = {
  40 + { MIICMD_SET, 22, 0x00ff },
  41 + { MIICMD_SET, 17, 0x214b },
  42 + { MIICMD_SET, 16, 0x2144 },
  43 + { MIICMD_SET, 17, 0x0c28 },
  44 + { MIICMD_SET, 16, 0x2146 },
  45 + { MIICMD_SET, 17, 0xb233 },
  46 + { MIICMD_SET, 16, 0x214d },
  47 + { MIICMD_SET, 17, 0xcc0c },
  48 + { MIICMD_SET, 16, 0x2159 },
  49 + { MIICMD_SET, 22, 0x00fb },
  50 + { MIICMD_SET, 7, 0xc00d },
  51 + { MIICMD_SET, 22, 0x0000 },
  52 +};
  53 +
  54 +/*
  55 + * default initialization:
  56 + * - set RGMII receive timing to "receive clock transition when data stable"
  57 + * - set RGMII transmit timing to "transmit clock internally delayed"
  58 + * - set RGMII output impedance target to 78,8 Ohm
  59 + * - run output impedance calibration
  60 + * - set autonegotiation advertise to 1000FD only
  61 + */
  62 +struct mii_setupcmd default_88e1518[] = {
  63 + { MIICMD_SET, 22, 0x0002 },
  64 + { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
  65 + { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
  66 + { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
  67 + { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
  68 + { MIICMD_SET, 22, 0x0000 },
  69 + { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
  70 + { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
  71 +};
  72 +
  73 +/*
  74 + * turn off CLK125 for PHY daughterboard
  75 + */
  76 +struct mii_setupcmd ch1fix_88e1518[] = {
  77 + { MIICMD_SET, 22, 0x0002 },
  78 + { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
  79 + { MIICMD_SET, 22, 0x0000 },
  80 +};
  81 +
  82 +/*
  83 + * perform copper software reset
  84 + */
  85 +struct mii_setupcmd swreset_88e1518[] = {
  86 + { MIICMD_SET, 22, 0x0000 },
  87 + { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
  88 + { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
  89 +};
  90 +
  91 +/*
  92 + * special one for 88E1514:
  93 + * Force SGMII to Copper mode
  94 + */
  95 +struct mii_setupcmd mii_to_copper_88e1514[] = {
  96 + { MIICMD_SET, 22, 0x0012 },
  97 + { MIICMD_MODIFY, 20, 0x0001, 0x0007 },
  98 + { MIICMD_MODIFY, 20, 0x8000, 0x8000 },
  99 + { MIICMD_SET, 22, 0x0000 },
  100 +};
  101 +
  102 +/*
  103 + * turn off SGMII auto-negotiation
  104 + */
  105 +struct mii_setupcmd sgmii_autoneg_off_88e1518[] = {
  106 + { MIICMD_SET, 22, 0x0001 },
  107 + { MIICMD_MODIFY, 0, 0x0000, 0x1000 },
  108 + { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
  109 + { MIICMD_SET, 22, 0x0000 },
  110 +};
  111 +
  112 +/*
  113 + * invert LED2 polarity
  114 + */
  115 +struct mii_setupcmd invert_led2_88e1514[] = {
  116 + { MIICMD_SET, 22, 0x0003 },
  117 + { MIICMD_MODIFY, 17, 0x0030, 0x0010 },
  118 + { MIICMD_SET, 22, 0x0000 },
  119 +};
  120 +
  121 +static int process_setupcmd(const char *bus, unsigned char addr,
  122 + struct mii_setupcmd *setupcmd)
  123 +{
  124 + int res;
  125 + u8 reg = setupcmd->reg;
  126 + u16 data = setupcmd->data;
  127 + u16 mask = setupcmd->mask;
  128 + u32 timeout = setupcmd->timeout;
  129 + u16 orig_data;
  130 + unsigned long start;
  131 +
  132 + debug("mii %s:%u reg %2u ", bus, addr, reg);
  133 +
  134 + switch (setupcmd->token) {
  135 + case MIICMD_MODIFY:
  136 + res = miiphy_read(bus, addr, reg, &orig_data);
  137 + if (res)
  138 + break;
  139 + debug("is %04x. (value %04x mask %04x) ", orig_data, data,
  140 + mask);
  141 + data = (orig_data & ~mask) | (data & mask);
  142 + /* fallthrough */
  143 + case MIICMD_SET:
  144 + debug("=> %04x\n", data);
  145 + res = miiphy_write(bus, addr, reg, data);
  146 + break;
  147 + case MIICMD_VERIFY_VALUE:
  148 + res = miiphy_read(bus, addr, reg, &orig_data);
  149 + if (res)
  150 + break;
  151 + if ((orig_data & mask) != (data & mask))
  152 + res = -1;
  153 + debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
  154 + orig_data, res ? "FAIL" : "PASS");
  155 + break;
  156 + case MIICMD_WAIT_FOR_VALUE:
  157 + res = -1;
  158 + start = get_timer(0);
  159 + while ((res != 0) && (get_timer(start) < timeout)) {
  160 + res = miiphy_read(bus, addr, reg, &orig_data);
  161 + if (res)
  162 + continue;
  163 + if ((orig_data & mask) != (data & mask))
  164 + res = -1;
  165 + }
  166 + debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
  167 + mask, orig_data, res ? "FAIL" : "PASS",
  168 + get_timer(start));
  169 + break;
  170 + default:
  171 + res = -1;
  172 + break;
  173 + }
  174 +
  175 + return res;
  176 +}
  177 +
  178 +static int process_setup(const char *bus, unsigned char addr,
  179 + struct mii_setupcmd *setupcmd, unsigned int count)
  180 +{
  181 + int res = 0;
  182 + unsigned int k;
  183 +
  184 + for (k = 0; k < count; ++k) {
  185 + res = process_setupcmd(bus, addr, &setupcmd[k]);
  186 + if (res) {
  187 + printf("mii cmd %u on bus %s addr %u failed, aborting setup\n",
  188 + setupcmd[k].token, bus, addr);
  189 + break;
  190 + }
  191 + }
  192 +
  193 + return res;
  194 +}
  195 +
  196 +int setup_88e1518(const char *bus, unsigned char addr)
  197 +{
  198 + int res;
  199 +
  200 + res = process_setup(bus, addr,
  201 + verify_88e1518, ARRAY_SIZE(verify_88e1518));
  202 + if (res)
  203 + return res;
  204 +
  205 + res = process_setup(bus, addr,
  206 + fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
  207 + if (res)
  208 + return res;
  209 +
  210 + res = process_setup(bus, addr,
  211 + default_88e1518, ARRAY_SIZE(default_88e1518));
  212 + if (res)
  213 + return res;
  214 +
  215 + if (addr) {
  216 + res = process_setup(bus, addr,
  217 + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
  218 + if (res)
  219 + return res;
  220 + }
  221 +
  222 + res = process_setup(bus, addr,
  223 + swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
  224 + if (res)
  225 + return res;
  226 +
  227 + return 0;
  228 +}
  229 +
  230 +int setup_88e1514(const char *bus, unsigned char addr)
  231 +{
  232 + int res;
  233 +
  234 + res = process_setup(bus, addr,
  235 + verify_88e1518, ARRAY_SIZE(verify_88e1518));
  236 + if (res)
  237 + return res;
  238 +
  239 + res = process_setup(bus, addr,
  240 + fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
  241 + if (res)
  242 + return res;
  243 +
  244 + res = process_setup(bus, addr,
  245 + mii_to_copper_88e1514,
  246 + ARRAY_SIZE(mii_to_copper_88e1514));
  247 + if (res)
  248 + return res;
  249 +
  250 + res = process_setup(bus, addr,
  251 + sgmii_autoneg_off_88e1518,
  252 + ARRAY_SIZE(sgmii_autoneg_off_88e1518));
  253 + if (res)
  254 + return res;
  255 +
  256 + res = process_setup(bus, addr,
  257 + invert_led2_88e1514,
  258 + ARRAY_SIZE(invert_led2_88e1514));
  259 + if (res)
  260 + return res;
  261 +
  262 + res = process_setup(bus, addr,
  263 + default_88e1518, ARRAY_SIZE(default_88e1518));
  264 + if (res)
  265 + return res;
  266 +
  267 + if (addr) {
  268 + res = process_setup(bus, addr,
  269 + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
  270 + if (res)
  271 + return res;
  272 + }
  273 +
  274 + res = process_setup(bus, addr,
  275 + swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
  276 + if (res)
  277 + return res;
  278 +
  279 + return 0;
  280 +}
board/gdsys/common/phy.h
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _PHY_H_
  9 +#define _PHY_H_
  10 +
  11 +int setup_88e1514(const char *bus, unsigned char addr);
  12 +int setup_88e1518(const char *bus, unsigned char addr);
  13 +
  14 +#endif
board/gdsys/mpc8308/Kconfig
Diff comments   View file @ 50dcf89
  1 +if TARGET_HRCON
  2 +
  3 +config SYS_BOARD
  4 + default "mpc8308"
  5 +
  6 +config SYS_VENDOR
  7 + default "gdsys"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "hrcon"
  11 +
  12 +endif
board/gdsys/mpc8308/MAINTAINERS
Diff comments   View file @ 50dcf89
  1 +MPC8308 BOARD
  2 +M: Dirk Eibach <eibach@gdsys.de>
  3 +S: Maintained
  4 +F: board/gdsys/mpc8308/
  5 +F: include/configs/hrcon.h
  6 +F: configs/hrcon_defconfig
board/gdsys/mpc8308/Makefile
Diff comments   View file @ 50dcf89
  1 +#
  2 +# (C) Copyright 2014
  3 +# Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := mpc8308.o sdram.o
  9 +obj-$(CONFIG_HRCON) += hrcon.o
board/gdsys/mpc8308/hrcon.c
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <hwconfig.h>
  10 +#include <i2c.h>
  11 +#include <spi.h>
  12 +#include <libfdt.h>
  13 +#include <fdt_support.h>
  14 +#include <pci.h>
  15 +#include <mpc83xx.h>
  16 +#include <fsl_esdhc.h>
  17 +#include <asm/io.h>
  18 +#include <asm/fsl_serdes.h>
  19 +#include <asm/fsl_mpc83xx_serdes.h>
  20 +
  21 +#include "mpc8308.h"
  22 +
  23 +#include <gdsys_fpga.h>
  24 +
  25 +#include "../common/osd.h"
  26 +#include "../common/mclink.h"
  27 +#include "../common/phy.h"
  28 +
  29 +#include <pca953x.h>
  30 +#include <pca9698.h>
  31 +
  32 +#include <miiphy.h>
  33 +
  34 +DECLARE_GLOBAL_DATA_PTR;
  35 +
  36 +#define MAX_MUX_CHANNELS 2
  37 +
  38 +enum {
  39 + UNITTYPE_MAIN_SERVER = 0,
  40 + UNITTYPE_MAIN_USER = 1,
  41 + UNITTYPE_VIDEO_SERVER = 2,
  42 + UNITTYPE_VIDEO_USER = 3,
  43 +};
  44 +
  45 +enum {
  46 + UNITTYPEPCB_DVI = 0,
  47 + UNITTYPEPCB_DP_165 = 1,
  48 + UNITTYPEPCB_DP_300 = 2,
  49 + UNITTYPEPCB_HDMI = 3,
  50 +};
  51 +
  52 +enum {
  53 + HWVER_100 = 0,
  54 + HWVER_110 = 1,
  55 +};
  56 +
  57 +enum {
  58 + FPGA_HWVER_200 = 0,
  59 + FPGA_HWVER_210 = 1,
  60 +};
  61 +
  62 +enum {
  63 + COMPRESSION_NONE = 0,
  64 + COMPRESSION_TYPE1_DELTA = 1,
  65 + COMPRESSION_TYPE1_TYPE2_DELTA = 3,
  66 +};
  67 +
  68 +enum {
  69 + AUDIO_NONE = 0,
  70 + AUDIO_TX = 1,
  71 + AUDIO_RX = 2,
  72 + AUDIO_RXTX = 3,
  73 +};
  74 +
  75 +enum {
  76 + SYSCLK_147456 = 0,
  77 +};
  78 +
  79 +enum {
  80 + RAM_DDR2_32 = 0,
  81 + RAM_DDR3_32 = 1,
  82 +};
  83 +
  84 +enum {
  85 + CARRIER_SPEED_1G = 0,
  86 + CARRIER_SPEED_2_5G = 1,
  87 +};
  88 +
  89 +enum {
  90 + MCFPGA_DONE = 1 << 0,
  91 + MCFPGA_INIT_N = 1 << 1,
  92 + MCFPGA_PROGRAM_N = 1 << 2,
  93 + MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  94 + MCFPGA_RESET_N = 1 << 4,
  95 +};
  96 +
  97 +enum {
  98 + GPIO_MDC = 1 << 14,
  99 + GPIO_MDIO = 1 << 15,
  100 +};
  101 +
  102 +unsigned int mclink_fpgacount;
  103 +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  104 +
  105 +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  106 +{
  107 + int res;
  108 +
  109 + switch (fpga) {
  110 + case 0:
  111 + out_le16(reg, data);
  112 + break;
  113 + default:
  114 + res = mclink_send(fpga - 1, regoff, data);
  115 + if (res < 0) {
  116 + printf("mclink_send reg %02lx data %04x returned %d\n",
  117 + regoff, data, res);
  118 + return res;
  119 + }
  120 + break;
  121 + }
  122 +
  123 + return 0;
  124 +}
  125 +
  126 +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  127 +{
  128 + int res;
  129 +
  130 + switch (fpga) {
  131 + case 0:
  132 + *data = in_le16(reg);
  133 + break;
  134 + default:
  135 + if (fpga > mclink_fpgacount)
  136 + return -EINVAL;
  137 + res = mclink_receive(fpga - 1, regoff, data);
  138 + if (res < 0) {
  139 + printf("mclink_receive reg %02lx returned %d\n",
  140 + regoff, res);
  141 + return res;
  142 + }
  143 + }
  144 +
  145 + return 0;
  146 +}
  147 +
  148 +int checkboard(void)
  149 +{
  150 + char *s = getenv("serial#");
  151 + bool hw_type_cat = pca9698_get_value(0x20, 20);
  152 +
  153 + puts("Board: ");
  154 +
  155 + printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
  156 +
  157 + if (s != NULL) {
  158 + puts(", serial# ");
  159 + puts(s);
  160 + }
  161 +
  162 + puts("\n");
  163 +
  164 + return 0;
  165 +}
  166 +
  167 +static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
  168 +{
  169 + u16 versions;
  170 + u16 fpga_version;
  171 + u16 fpga_features;
  172 + unsigned unit_type;
  173 + unsigned unit_type_pcb_video;
  174 + unsigned hardware_version;
  175 + unsigned feature_compression;
  176 + unsigned feature_osd;
  177 + unsigned feature_audio;
  178 + unsigned feature_sysclock;
  179 + unsigned feature_ramconfig;
  180 + unsigned feature_carrier_speed;
  181 + unsigned feature_carriers;
  182 + unsigned feature_video_channels;
  183 +
  184 + FPGA_GET_REG(fpga, versions, &versions);
  185 + FPGA_GET_REG(fpga, fpga_version, &fpga_version);
  186 + FPGA_GET_REG(fpga, fpga_features, &fpga_features);
  187 +
  188 + unit_type = (versions & 0xf000) >> 12;
  189 + unit_type_pcb_video = (versions & 0x01c0) >> 6;
  190 + feature_compression = (fpga_features & 0xe000) >> 13;
  191 + feature_osd = fpga_features & (1<<11);
  192 + feature_audio = (fpga_features & 0x0600) >> 9;
  193 + feature_sysclock = (fpga_features & 0x0180) >> 7;
  194 + feature_ramconfig = (fpga_features & 0x0060) >> 5;
  195 + feature_carrier_speed = fpga_features & (1<<4);
  196 + feature_carriers = (fpga_features & 0x000c) >> 2;
  197 + feature_video_channels = fpga_features & 0x0003;
  198 +
  199 + switch (unit_type) {
  200 + case UNITTYPE_MAIN_USER:
  201 + printf("Mainchannel");
  202 + break;
  203 +
  204 + case UNITTYPE_VIDEO_USER:
  205 + printf("Videochannel");
  206 + break;
  207 +
  208 + default:
  209 + printf("UnitType %d(not supported)", unit_type);
  210 + break;
  211 + }
  212 +
  213 + if (unit_type == UNITTYPE_MAIN_USER) {
  214 + hardware_version =
  215 + (!!pca9698_get_value(0x20, 24) << 0)
  216 + | (!!pca9698_get_value(0x20, 25) << 1)
  217 + | (!!pca9698_get_value(0x20, 26) << 2)
  218 + | (!!pca9698_get_value(0x20, 27) << 3)
  219 + | (!!pca9698_get_value(0x20, 28) << 4);
  220 + switch (hardware_version) {
  221 + case HWVER_100:
  222 + printf(" HW-Ver 1.00,");
  223 + break;
  224 +
  225 + case HWVER_110:
  226 + printf(" HW-Ver 1.10,");
  227 + break;
  228 +
  229 + default:
  230 + printf(" HW-Ver %d(not supported),",
  231 + hardware_version);
  232 + break;
  233 + }
  234 + if (rgmii2_present)
  235 + printf(" RGMII2,");
  236 + }
  237 +
  238 + if (unit_type == UNITTYPE_VIDEO_USER) {
  239 + hardware_version = versions & 0x000f;
  240 + switch (hardware_version) {
  241 + case FPGA_HWVER_200:
  242 + printf(" HW-Ver 2.00,");
  243 + break;
  244 +
  245 + case FPGA_HWVER_210:
  246 + printf(" HW-Ver 2.10,");
  247 + break;
  248 +
  249 + default:
  250 + printf(" HW-Ver %d(not supported),",
  251 + hardware_version);
  252 + break;
  253 + }
  254 + }
  255 +
  256 + switch (unit_type_pcb_video) {
  257 + case UNITTYPEPCB_DVI:
  258 + printf(" DVI,");
  259 + break;
  260 +
  261 + case UNITTYPEPCB_DP_165:
  262 + printf(" DP 165MPix/s,");
  263 + break;
  264 +
  265 + case UNITTYPEPCB_DP_300:
  266 + printf(" DP 300MPix/s,");
  267 + break;
  268 +
  269 + case UNITTYPEPCB_HDMI:
  270 + printf(" HDMI,");
  271 + break;
  272 + }
  273 +
  274 + printf(" FPGA V %d.%02d\n features:",
  275 + fpga_version / 100, fpga_version % 100);
  276 +
  277 +
  278 + switch (feature_compression) {
  279 + case COMPRESSION_NONE:
  280 + printf(" no compression");
  281 + break;
  282 +
  283 + case COMPRESSION_TYPE1_DELTA:
  284 + printf(" type1-deltacompression");
  285 + break;
  286 +
  287 + case COMPRESSION_TYPE1_TYPE2_DELTA:
  288 + printf(" type1-deltacompression, type2-inlinecompression");
  289 + break;
  290 +
  291 + default:
  292 + printf(" compression %d(not supported)", feature_compression);
  293 + break;
  294 + }
  295 +
  296 + printf(", %sosd", feature_osd ? "" : "no ");
  297 +
  298 + switch (feature_audio) {
  299 + case AUDIO_NONE:
  300 + printf(", no audio");
  301 + break;
  302 +
  303 + case AUDIO_TX:
  304 + printf(", audio tx");
  305 + break;
  306 +
  307 + case AUDIO_RX:
  308 + printf(", audio rx");
  309 + break;
  310 +
  311 + case AUDIO_RXTX:
  312 + printf(", audio rx+tx");
  313 + break;
  314 +
  315 + default:
  316 + printf(", audio %d(not supported)", feature_audio);
  317 + break;
  318 + }
  319 +
  320 + puts(",\n ");
  321 +
  322 + switch (feature_sysclock) {
  323 + case SYSCLK_147456:
  324 + printf("clock 147.456 MHz");
  325 + break;
  326 +
  327 + default:
  328 + printf("clock %d(not supported)", feature_sysclock);
  329 + break;
  330 + }
  331 +
  332 + switch (feature_ramconfig) {
  333 + case RAM_DDR2_32:
  334 + printf(", RAM 32 bit DDR2");
  335 + break;
  336 +
  337 + case RAM_DDR3_32:
  338 + printf(", RAM 32 bit DDR3");
  339 + break;
  340 +
  341 + default:
  342 + printf(", RAM %d(not supported)", feature_ramconfig);
  343 + break;
  344 + }
  345 +
  346 + printf(", %d carrier(s) %s", feature_carriers,
  347 + feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
  348 +
  349 + printf(", %d video channel(s)\n", feature_video_channels);
  350 +}
  351 +
  352 +int last_stage_init(void)
  353 +{
  354 + int slaves;
  355 + unsigned int k;
  356 + unsigned int mux_ch;
  357 + unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
  358 + u16 fpga_features;
  359 + bool hw_type_cat = pca9698_get_value(0x20, 20);
  360 + bool ch0_rgmii2_present = false;
  361 +
  362 + FPGA_GET_REG(0, fpga_features, &fpga_features);
  363 +
  364 + /* Turn on Parade DP501 */
  365 + pca9698_direction_output(0x20, 10, 1);
  366 +
  367 + ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
  368 +
  369 + /* wait for FPGA done */
  370 + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
  371 + unsigned int ctr = 0;
  372 +
  373 + if (i2c_probe(mclink_controllers[k]))
  374 + continue;
  375 +
  376 + while (!(pca953x_get_val(mclink_controllers[k])
  377 + & MCFPGA_DONE)) {
  378 + udelay(100000);
  379 + if (ctr++ > 5) {
  380 + printf("no done for mclink_controller %d\n", k);
  381 + break;
  382 + }
  383 + }
  384 + }
  385 +
  386 + if (hw_type_cat) {
  387 + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
  388 + bb_miiphy_write);
  389 + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  390 + if ((mux_ch == 1) && !ch0_rgmii2_present)
  391 + continue;
  392 +
  393 + setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  394 + }
  395 + }
  396 +
  397 + /* give slave-PLLs and Parade DP501 some time to be up and running */
  398 + udelay(500000);
  399 +
  400 + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  401 + slaves = mclink_probe();
  402 + mclink_fpgacount = 0;
  403 +
  404 + print_fpga_info(0, ch0_rgmii2_present);
  405 + osd_probe(0);
  406 +
  407 + if (slaves <= 0)
  408 + return 0;
  409 +
  410 + mclink_fpgacount = slaves;
  411 +
  412 + for (k = 1; k <= slaves; ++k) {
  413 + FPGA_GET_REG(k, fpga_features, &fpga_features);
  414 +
  415 + print_fpga_info(k, false);
  416 + osd_probe(k);
  417 + if (hw_type_cat) {
  418 + miiphy_register(bb_miiphy_buses[k].name,
  419 + bb_miiphy_read, bb_miiphy_write);
  420 + setup_88e1514(bb_miiphy_buses[k].name, 0);
  421 + }
  422 + }
  423 +
  424 + return 0;
  425 +}
  426 +
  427 +/*
  428 + * provide access to fpga gpios (for I2C bitbang)
  429 + * (these may look all too simple but make iocon.h much more readable)
  430 + */
  431 +void fpga_gpio_set(unsigned int bus, int pin)
  432 +{
  433 + FPGA_SET_REG(bus, gpio.set, pin);
  434 +}
  435 +
  436 +void fpga_gpio_clear(unsigned int bus, int pin)
  437 +{
  438 + FPGA_SET_REG(bus, gpio.clear, pin);
  439 +}
  440 +
  441 +int fpga_gpio_get(unsigned int bus, int pin)
  442 +{
  443 + u16 val;
  444 +
  445 + FPGA_GET_REG(bus, gpio.read, &val);
  446 +
  447 + return val & pin;
  448 +}
  449 +
  450 +void mpc8308_init(void)
  451 +{
  452 + pca9698_direction_output(0x20, 4, 1);
  453 +}
  454 +
  455 +void mpc8308_set_fpga_reset(unsigned state)
  456 +{
  457 + pca9698_set_value(0x20, 4, state ? 0 : 1);
  458 +}
  459 +
  460 +void mpc8308_setup_hw(void)
  461 +{
  462 + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  463 +
  464 + /*
  465 + * set "startup-finished"-gpios
  466 + */
  467 + setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
  468 + setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
  469 +}
  470 +
  471 +int mpc8308_get_fpga_done(unsigned fpga)
  472 +{
  473 + return pca9698_get_value(0x20, 19);
  474 +}
  475 +
  476 +#ifdef CONFIG_FSL_ESDHC
  477 +int board_mmc_init(bd_t *bd)
  478 +{
  479 + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  480 + sysconf83xx_t *sysconf = &immr->sysconf;
  481 +
  482 + /* Enable cache snooping in eSDHC system configuration register */
  483 + out_be32(&sysconf->sdhccr, 0x02000000);
  484 +
  485 + return fsl_esdhc_mmc_init(bd);
  486 +}
  487 +#endif
  488 +
  489 +static struct pci_region pcie_regions_0[] = {
  490 + {
  491 + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  492 + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  493 + .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  494 + .flags = PCI_REGION_MEM,
  495 + },
  496 + {
  497 + .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  498 + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  499 + .size = CONFIG_SYS_PCIE1_IO_SIZE,
  500 + .flags = PCI_REGION_IO,
  501 + },
  502 +};
  503 +
  504 +void pci_init_board(void)
  505 +{
  506 + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  507 + sysconf83xx_t *sysconf = &immr->sysconf;
  508 + law83xx_t *pcie_law = sysconf->pcielaw;
  509 + struct pci_region *pcie_reg[] = { pcie_regions_0 };
  510 +
  511 + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  512 + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  513 +
  514 + /* Deassert the resets in the control register */
  515 + out_be32(&sysconf->pecr1, 0xE0008000);
  516 + udelay(2000);
  517 +
  518 + /* Configure PCI Express Local Access Windows */
  519 + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  520 + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  521 +
  522 + mpc83xx_pcie_init(1, pcie_reg);
  523 +}
  524 +
  525 +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  526 +{
  527 + info->portwidth = FLASH_CFI_16BIT;
  528 + info->chipwidth = FLASH_CFI_BY16;
  529 + info->interface = FLASH_CFI_X16;
  530 + return 1;
  531 +}
  532 +
  533 +#if defined(CONFIG_OF_BOARD_SETUP)
  534 +void ft_board_setup(void *blob, bd_t *bd)
  535 +{
  536 + ft_cpu_setup(blob, bd);
  537 + fdt_fixup_dr_usb(blob, bd);
  538 + fdt_fixup_esdhc(blob, bd);
  539 +}
  540 +#endif
  541 +
  542 +/*
  543 + * FPGA MII bitbang implementation
  544 + */
  545 +
  546 +struct fpga_mii {
  547 + unsigned fpga;
  548 + int mdio;
  549 +} fpga_mii[] = {
  550 + { 0, 1},
  551 + { 1, 1},
  552 + { 2, 1},
  553 + { 3, 1},
  554 +};
  555 +
  556 +static int mii_dummy_init(struct bb_miiphy_bus *bus)
  557 +{
  558 + return 0;
  559 +}
  560 +
  561 +static int mii_mdio_active(struct bb_miiphy_bus *bus)
  562 +{
  563 + struct fpga_mii *fpga_mii = bus->priv;
  564 +
  565 + if (fpga_mii->mdio)
  566 + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  567 + else
  568 + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  569 +
  570 + return 0;
  571 +}
  572 +
  573 +static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  574 +{
  575 + struct fpga_mii *fpga_mii = bus->priv;
  576 +
  577 + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  578 +
  579 + return 0;
  580 +}
  581 +
  582 +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  583 +{
  584 + struct fpga_mii *fpga_mii = bus->priv;
  585 +
  586 + if (v)
  587 + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  588 + else
  589 + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  590 +
  591 + fpga_mii->mdio = v;
  592 +
  593 + return 0;
  594 +}
  595 +
  596 +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  597 +{
  598 + u16 gpio;
  599 + struct fpga_mii *fpga_mii = bus->priv;
  600 +
  601 + FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  602 +
  603 + *v = ((gpio & GPIO_MDIO) != 0);
  604 +
  605 + return 0;
  606 +}
  607 +
  608 +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  609 +{
  610 + struct fpga_mii *fpga_mii = bus->priv;
  611 +
  612 + if (v)
  613 + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  614 + else
  615 + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  616 +
  617 + return 0;
  618 +}
  619 +
  620 +static int mii_delay(struct bb_miiphy_bus *bus)
  621 +{
  622 + udelay(1);
  623 +
  624 + return 0;
  625 +}
  626 +
  627 +struct bb_miiphy_bus bb_miiphy_buses[] = {
  628 + {
  629 + .name = "board0",
  630 + .init = mii_dummy_init,
  631 + .mdio_active = mii_mdio_active,
  632 + .mdio_tristate = mii_mdio_tristate,
  633 + .set_mdio = mii_set_mdio,
  634 + .get_mdio = mii_get_mdio,
  635 + .set_mdc = mii_set_mdc,
  636 + .delay = mii_delay,
  637 + .priv = &fpga_mii[0],
  638 + },
  639 + {
  640 + .name = "board1",
  641 + .init = mii_dummy_init,
  642 + .mdio_active = mii_mdio_active,
  643 + .mdio_tristate = mii_mdio_tristate,
  644 + .set_mdio = mii_set_mdio,
  645 + .get_mdio = mii_get_mdio,
  646 + .set_mdc = mii_set_mdc,
  647 + .delay = mii_delay,
  648 + .priv = &fpga_mii[1],
  649 + },
  650 + {
  651 + .name = "board2",
  652 + .init = mii_dummy_init,
  653 + .mdio_active = mii_mdio_active,
  654 + .mdio_tristate = mii_mdio_tristate,
  655 + .set_mdio = mii_set_mdio,
  656 + .get_mdio = mii_get_mdio,
  657 + .set_mdc = mii_set_mdc,
  658 + .delay = mii_delay,
  659 + .priv = &fpga_mii[2],
  660 + },
  661 + {
  662 + .name = "board3",
  663 + .init = mii_dummy_init,
  664 + .mdio_active = mii_mdio_active,
  665 + .mdio_tristate = mii_mdio_tristate,
  666 + .set_mdio = mii_set_mdio,
  667 + .get_mdio = mii_get_mdio,
  668 + .set_mdc = mii_set_mdc,
  669 + .delay = mii_delay,
  670 + .priv = &fpga_mii[3],
  671 + },
  672 +};
  673 +
  674 +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
  675 + sizeof(bb_miiphy_buses[0]);
board/gdsys/mpc8308/mpc8308.c
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <command.h>
  10 +#include <asm/processor.h>
  11 +#include <asm/io.h>
  12 +#include <asm/ppc4xx-gpio.h>
  13 +#include <asm/global_data.h>
  14 +
  15 +#include "mpc8308.h"
  16 +#include <gdsys_fpga.h>
  17 +
  18 +#define REFLECTION_TESTPATTERN 0xdede
  19 +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  20 +
  21 +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  22 +#define REFLECTION_TESTREG reflection_low
  23 +#else
  24 +#define REFLECTION_TESTREG reflection_high
  25 +#endif
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +int get_fpga_state(unsigned dev)
  30 +{
  31 + return gd->arch.fpga_state[dev];
  32 +}
  33 +
  34 +void print_fpga_state(unsigned dev)
  35 +{
  36 + if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  37 + puts(" Waiting for FPGA-DONE timed out.\n");
  38 + if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  39 + puts(" FPGA reflection test failed.\n");
  40 +}
  41 +
  42 +int board_early_init_f(void)
  43 +{
  44 + unsigned k;
  45 +
  46 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  47 + gd->arch.fpga_state[k] = 0;
  48 +
  49 + return 0;
  50 +}
  51 +
  52 +int board_early_init_r(void)
  53 +{
  54 + unsigned k;
  55 + unsigned ctr;
  56 +
  57 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  58 + gd->arch.fpga_state[k] = 0;
  59 +
  60 + /*
  61 + * reset FPGA
  62 + */
  63 + mpc8308_init();
  64 +
  65 + mpc8308_set_fpga_reset(1);
  66 +
  67 + mpc8308_setup_hw();
  68 +
  69 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  70 + ctr = 0;
  71 + while (!mpc8308_get_fpga_done(k)) {
  72 + udelay(100000);
  73 + if (ctr++ > 5) {
  74 + gd->arch.fpga_state[k] |=
  75 + FPGA_STATE_DONE_FAILED;
  76 + break;
  77 + }
  78 + }
  79 + }
  80 +
  81 + udelay(10);
  82 +
  83 + mpc8308_set_fpga_reset(0);
  84 +
  85 + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  86 + /*
  87 + * wait for fpga out of reset
  88 + */
  89 + ctr = 0;
  90 + while (1) {
  91 + u16 val;
  92 +
  93 + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  94 +
  95 + FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  96 + if (val == REFLECTION_TESTPATTERN_INV)
  97 + break;
  98 +
  99 + udelay(100000);
  100 + if (ctr++ > 5) {
  101 + gd->arch.fpga_state[k] |=
  102 + FPGA_STATE_REFLECTION_FAILED;
  103 + break;
  104 + }
  105 + }
  106 + }
  107 +
  108 + return 0;
  109 +}
board/gdsys/mpc8308/mpc8308.h
Diff comments   View file @ 50dcf89
  1 +#ifndef __MPC8308_H_
  2 +#define __MPC8308_H_
  3 +
  4 +/* functions to be provided by board implementation */
  5 +void mpc8308_init(void);
  6 +void mpc8308_set_fpga_reset(unsigned state);
  7 +void mpc8308_setup_hw(void);
  8 +int mpc8308_get_fpga_done(unsigned fpga);
  9 +
  10 +#endif /* __MPC8308_H_ */
board/gdsys/mpc8308/sdram.c
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * Copyright (C) 2007 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  4 + *
  5 + * Authors: Nick.Spence@freescale.com
  6 + * Wilson.Lo@freescale.com
  7 + * scottwood@freescale.com
  8 + *
  9 + * This files is mostly identical to the original from
  10 + * board\freescale\mpc8315erdb\sdram.c
  11 + *
  12 + * SPDX-License-Identifier: GPL-2.0+
  13 + */
  14 +
  15 +#include <common.h>
  16 +#include <mpc83xx.h>
  17 +#include <spd_sdram.h>
  18 +
  19 +#include <asm/bitops.h>
  20 +#include <asm/io.h>
  21 +
  22 +#include <asm/processor.h>
  23 +
  24 +DECLARE_GLOBAL_DATA_PTR;
  25 +
  26 +/* Fixed sdram init -- doesn't use serial presence detect.
  27 + *
  28 + * This is useful for faster booting in configs where the RAM is unlikely
  29 + * to be changed, or for things like NAND booting where space is tight.
  30 + */
  31 +static long fixed_sdram(void)
  32 +{
  33 + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  34 + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  35 + u32 msize_log2 = __ilog2(msize);
  36 +
  37 + out_be32(&im->sysconf.ddrlaw[0].bar,
  38 + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
  39 + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
  40 + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  41 +
  42 + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
  43 + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  44 +
  45 + /* Currently we use only one CS, so disable the other bank. */
  46 + out_be32(&im->ddr.cs_config[1], 0);
  47 +
  48 + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
  49 + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  50 + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  51 + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  52 + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  53 +
  54 + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  55 + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  56 + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  57 + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  58 +
  59 + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  60 + sync();
  61 +
  62 + /* enable DDR controller */
  63 + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  64 + sync();
  65 +
  66 + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
  67 +}
  68 +
  69 +phys_size_t initdram(int board_type)
  70 +{
  71 + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  72 + u32 msize;
  73 +
  74 + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  75 + return -1;
  76 +
  77 + /* DDR SDRAM */
  78 + msize = fixed_sdram();
  79 +
  80 + /* return total bus SDRAM size(bytes) -- DDR */
  81 + return msize;
  82 +}
configs/hrcon_defconfig
Diff comments   View file @ 50dcf89
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC83xx=y
  3 +CONFIG_TARGET_HRCON=y
include/configs/hrcon.h
Diff comments   View file @ 50dcf89
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_H
  10 +#define __CONFIG_H
  11 +
  12 +/*
  13 + * High Level Configuration Options
  14 + */
  15 +#define CONFIG_E300 1 /* E300 family */
  16 +#define CONFIG_MPC83xx 1 /* MPC83xx family */
  17 +#define CONFIG_MPC830x 1 /* MPC830x family */
  18 +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
  19 +#define CONFIG_HRCON 1 /* HRCON board specific */
  20 +
  21 +#define CONFIG_SYS_TEXT_BASE 0xFE000000
  22 +
  23 +#define CONFIG_IDENT_STRING " hrcon 0.01"
  24 +
  25 +#define CONFIG_SYS_GENERIC_BOARD
  26 +
  27 +#define CONFIG_BOARD_EARLY_INIT_F
  28 +#define CONFIG_BOARD_EARLY_INIT_R
  29 +#define CONFIG_LAST_STAGE_INIT
  30 +
  31 +/* new uImage format support */
  32 +#define CONFIG_FIT 1
  33 +#define CONFIG_FIT_VERBOSE 1
  34 +
  35 +#define CONFIG_MMC
  36 +#define CONFIG_FSL_ESDHC
  37 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  38 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  39 +
  40 +#define CONFIG_CMD_MMC
  41 +#define CONFIG_GENERIC_MMC
  42 +#define CONFIG_DOS_PARTITION
  43 +#define CONFIG_CMD_EXT2
  44 +
  45 +#define CONFIG_CMD_FPGAD
  46 +#define CONFIG_CMD_IOLOOP
  47 +
  48 +/*
  49 + * System Clock Setup
  50 + */
  51 +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  52 +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  53 +
  54 +/*
  55 + * Hardware Reset Configuration Word
  56 + * if CLKIN is 66.66MHz, then
  57 + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  58 + * We choose the A type silicon as default, so the core is 400Mhz.
  59 + */
  60 +#define CONFIG_SYS_HRCW_LOW (\
  61 + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  62 + HRCWL_DDR_TO_SCB_CLK_2X1 |\
  63 + HRCWL_SVCOD_DIV_2 |\
  64 + HRCWL_CSB_TO_CLKIN_4X1 |\
  65 + HRCWL_CORE_TO_CSB_3X1)
  66 +/*
  67 + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  68 + * in 8308's HRCWH according to the manual, but original Freescale's
  69 + * code has them and I've expirienced some problems using the board
  70 + * with BDI3000 attached when I've tried to set these bits to zero
  71 + * (UART doesn't work after the 'reset run' command).
  72 + */
  73 +#define CONFIG_SYS_HRCW_HIGH (\
  74 + HRCWH_PCI_HOST |\
  75 + HRCWH_PCI1_ARBITER_ENABLE |\
  76 + HRCWH_CORE_ENABLE |\
  77 + HRCWH_FROM_0XFFF00100 |\
  78 + HRCWH_BOOTSEQ_DISABLE |\
  79 + HRCWH_SW_WATCHDOG_DISABLE |\
  80 + HRCWH_ROM_LOC_LOCAL_16BIT |\
  81 + HRCWH_RL_EXT_LEGACY |\
  82 + HRCWH_TSEC1M_IN_RGMII |\
  83 + HRCWH_TSEC2M_IN_RGMII |\
  84 + HRCWH_BIG_ENDIAN)
  85 +
  86 +/*
  87 + * System IO Config
  88 + */
  89 +#define CONFIG_SYS_SICRH (\
  90 + SICRH_ESDHC_A_SD |\
  91 + SICRH_ESDHC_B_SD |\
  92 + SICRH_ESDHC_C_SD |\
  93 + SICRH_GPIO_A_GPIO |\
  94 + SICRH_GPIO_B_GPIO |\
  95 + SICRH_IEEE1588_A_GPIO |\
  96 + SICRH_USB |\
  97 + SICRH_GTM_GPIO |\
  98 + SICRH_IEEE1588_B_GPIO |\
  99 + SICRH_ETSEC2_GPIO |\
  100 + SICRH_GPIOSEL_1 |\
  101 + SICRH_TMROBI_V3P3 |\
  102 + SICRH_TSOBI1_V2P5 |\
  103 + SICRH_TSOBI2_V2P5) /* 0x0037f103 */
  104 +#define CONFIG_SYS_SICRL (\
  105 + SICRL_SPI_PF0 |\
  106 + SICRL_UART_PF0 |\
  107 + SICRL_IRQ_PF0 |\
  108 + SICRL_I2C2_PF0 |\
  109 + SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
  110 +
  111 +/*
  112 + * IMMR new address
  113 + */
  114 +#define CONFIG_SYS_IMMR 0xE0000000
  115 +
  116 +/*
  117 + * SERDES
  118 + */
  119 +#define CONFIG_FSL_SERDES
  120 +#define CONFIG_FSL_SERDES1 0xe3000
  121 +
  122 +/*
  123 + * Arbiter Setup
  124 + */
  125 +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  126 +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
  127 +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
  128 +
  129 +/*
  130 + * DDR Setup
  131 + */
  132 +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
  133 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  134 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  135 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  136 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  137 + | DDRCDR_PZ_LOZ \
  138 + | DDRCDR_NZ_LOZ \
  139 + | DDRCDR_ODT \
  140 + | DDRCDR_Q_DRN)
  141 + /* 0x7b880001 */
  142 +/*
  143 + * Manually set up DDR parameters
  144 + * consist of one chip NT5TU64M16HG from NANYA
  145 + */
  146 +
  147 +#define CONFIG_SYS_DDR_SIZE 128 /* MB */
  148 +
  149 +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  150 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  151 + | CSCONFIG_ODT_RD_NEVER \
  152 + | CSCONFIG_ODT_WR_ONLY_CURRENT \
  153 + | CSCONFIG_BANK_BIT_3 \
  154 + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  155 + /* 0x80010102 */
  156 +#define CONFIG_SYS_DDR_TIMING_3 0
  157 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  158 + | (0 << TIMING_CFG0_WRT_SHIFT) \
  159 + | (0 << TIMING_CFG0_RRT_SHIFT) \
  160 + | (0 << TIMING_CFG0_WWT_SHIFT) \
  161 + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  162 + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  163 + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  164 + | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  165 + /* 0x00260802 */
  166 +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  167 + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  168 + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  169 + | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  170 + | (9 << TIMING_CFG1_REFREC_SHIFT) \
  171 + | (2 << TIMING_CFG1_WRREC_SHIFT) \
  172 + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  173 + | (2 << TIMING_CFG1_WRTORD_SHIFT))
  174 + /* 0x26279222 */
  175 +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  176 + | (4 << TIMING_CFG2_CPO_SHIFT) \
  177 + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  178 + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  179 + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  180 + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  181 + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  182 + /* 0x021848c5 */
  183 +#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  184 + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  185 + /* 0x08240100 */
  186 +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  187 + | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  188 + | SDRAM_CFG_DBW_16)
  189 + /* 0x43100000 */
  190 +
  191 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  192 +#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  193 + | (0x0242 << SDRAM_MODE_SD_SHIFT))
  194 + /* ODT 150ohm CL=4, AL=0 on SDRAM */
  195 +#define CONFIG_SYS_DDR_MODE2 0x00000000
  196 +
  197 +/*
  198 + * Memory test
  199 + */
  200 +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
  201 +#define CONFIG_SYS_MEMTEST_END 0x07f00000
  202 +
  203 +/*
  204 + * The reserved memory
  205 + */
  206 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  207 +
  208 +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  209 +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  210 +
  211 +/*
  212 + * Initial RAM Base Address Setup
  213 + */
  214 +#define CONFIG_SYS_INIT_RAM_LOCK 1
  215 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  216 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  217 +#define CONFIG_SYS_GBL_DATA_OFFSET \
  218 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  219 +
  220 +/*
  221 + * Local Bus Configuration & Clock Setup
  222 + */
  223 +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  224 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  225 +#define CONFIG_SYS_LBC_LBCR 0x00040000
  226 +
  227 +/*
  228 + * FLASH on the Local Bus
  229 + */
  230 +#if 1
  231 +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  232 +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  233 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  234 +#define CONFIG_FLASH_CFI_LEGACY
  235 +#define CONFIG_SYS_FLASH_LEGACY_512Kx16
  236 +#else
  237 +#define CONFIG_SYS_NO_FLASH
  238 +#endif
  239 +
  240 +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  241 +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
  242 +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  243 +
  244 +/* Window base at flash base */
  245 +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  246 +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
  247 +
  248 +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  249 + | BR_PS_16 /* 16 bit port */ \
  250 + | BR_MS_GPCM /* MSEL = GPCM */ \
  251 + | BR_V) /* valid */
  252 +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  253 + | OR_UPM_XAM \
  254 + | OR_GPCM_CSNT \
  255 + | OR_GPCM_ACS_DIV2 \
  256 + | OR_GPCM_XACS \
  257 + | OR_GPCM_SCY_15 \
  258 + | OR_GPCM_TRLX_SET \
  259 + | OR_GPCM_EHTR_SET)
  260 +
  261 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  262 +#define CONFIG_SYS_MAX_FLASH_SECT 135
  263 +
  264 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  265 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  266 +
  267 +/*
  268 + * FPGA
  269 + */
  270 +#define CONFIG_SYS_FPGA0_BASE 0xE0600000
  271 +#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
  272 +
  273 +/* Window base at FPGA base */
  274 +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
  275 +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
  276 +
  277 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
  278 + | BR_PS_16 /* 16 bit port */ \
  279 + | BR_MS_GPCM /* MSEL = GPCM */ \
  280 + | BR_V) /* valid */
  281 +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
  282 + | OR_UPM_XAM \
  283 + | OR_GPCM_CSNT \
  284 + | OR_GPCM_ACS_DIV2 \
  285 + | OR_GPCM_XACS \
  286 + | OR_GPCM_SCY_15 \
  287 + | OR_GPCM_TRLX_SET \
  288 + | OR_GPCM_EHTR_SET)
  289 +
  290 +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
  291 +#define CONFIG_SYS_FPGA_DONE(k) 0x0010
  292 +
  293 +#define CONFIG_SYS_FPGA_COUNT 1
  294 +
  295 +#define CONFIG_SYS_MCLINK_MAX 3
  296 +
  297 +#define CONFIG_SYS_FPGA_PTR \
  298 + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
  299 +
  300 +/*
  301 + * Serial Port
  302 + */
  303 +#define CONFIG_CONS_INDEX 2
  304 +#define CONFIG_SYS_NS16550
  305 +#define CONFIG_SYS_NS16550_SERIAL
  306 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  307 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  308 +
  309 +#define CONFIG_SYS_BAUDRATE_TABLE \
  310 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  311 +
  312 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  313 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  314 +
  315 +/* Use the HUSH parser */
  316 +#define CONFIG_SYS_HUSH_PARSER
  317 +
  318 +/* Pass open firmware flat tree */
  319 +#define CONFIG_OF_LIBFDT 1
  320 +#define CONFIG_OF_BOARD_SETUP 1
  321 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1
  322 +
  323 +/* I2C */
  324 +#define CONFIG_SYS_I2C
  325 +#define CONFIG_SYS_I2C_FSL
  326 +#define CONFIG_SYS_FSL_I2C_SPEED 400000
  327 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  328 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  329 +
  330 +#define CONFIG_PCA953X /* NXP PCA9554 */
  331 +#define CONFIG_PCA9698 /* NXP PCA9698 */
  332 +
  333 +#define CONFIG_SYS_I2C_IHS
  334 +#define CONFIG_SYS_I2C_IHS_CH0
  335 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
  336 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
  337 +#define CONFIG_SYS_I2C_IHS_CH1
  338 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
  339 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
  340 +#define CONFIG_SYS_I2C_IHS_CH2
  341 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
  342 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
  343 +#define CONFIG_SYS_I2C_IHS_CH3
  344 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
  345 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
  346 +
  347 +/*
  348 + * Software (bit-bang) I2C driver configuration
  349 + */
  350 +#define CONFIG_SYS_I2C_SOFT
  351 +#define CONFIG_SYS_I2C_SOFT_SPEED 50000
  352 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
  353 +#define I2C_SOFT_DECLARATIONS2
  354 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
  355 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
  356 +#define I2C_SOFT_DECLARATIONS3
  357 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
  358 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
  359 +#define I2C_SOFT_DECLARATIONS4
  360 +#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
  361 +#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
  362 +
  363 +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
  364 +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
  365 +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
  366 +
  367 +#ifndef __ASSEMBLY__
  368 +void fpga_gpio_set(unsigned int bus, int pin);
  369 +void fpga_gpio_clear(unsigned int bus, int pin);
  370 +int fpga_gpio_get(unsigned int bus, int pin);
  371 +#endif
  372 +
  373 +#define I2C_ACTIVE { }
  374 +#define I2C_TRISTATE { }
  375 +#define I2C_READ \
  376 + (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
  377 +#define I2C_SDA(bit) \
  378 + do { \
  379 + if (bit) \
  380 + fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
  381 + else \
  382 + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
  383 + } while (0)
  384 +#define I2C_SCL(bit) \
  385 + do { \
  386 + if (bit) \
  387 + fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
  388 + else \
  389 + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
  390 + } while (0)
  391 +#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
  392 +
  393 +/*
  394 + * Software (bit-bang) MII driver configuration
  395 + */
  396 +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  397 +#define CONFIG_BITBANGMII_MULTI
  398 +
  399 +/*
  400 + * OSD Setup
  401 + */
  402 +#define CONFIG_SYS_OSD_SCREENS 1
  403 +#define CONFIG_SYS_DP501_DIFFERENTIAL
  404 +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
  405 +
  406 +/*
  407 + * General PCI
  408 + * Addresses are mapped 1-1.
  409 + */
  410 +#define CONFIG_SYS_PCIE1_BASE 0xA0000000
  411 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  412 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  413 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  414 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  415 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  416 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  417 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  418 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  419 +
  420 +/* enable PCIE clock */
  421 +#define CONFIG_SYS_SCCR_PCIEXP1CM 1
  422 +
  423 +#define CONFIG_PCI
  424 +#define CONFIG_PCI_INDIRECT_BRIDGE
  425 +#define CONFIG_PCIE
  426 +
  427 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  428 +
  429 +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  430 +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  431 +
  432 +/*
  433 + * TSEC
  434 + */
  435 +#define CONFIG_TSEC_ENET /* TSEC ethernet support */
  436 +#define CONFIG_SYS_TSEC1_OFFSET 0x24000
  437 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  438 +
  439 +/*
  440 + * TSEC ethernet configuration
  441 + */
  442 +#define CONFIG_MII 1 /* MII PHY management */
  443 +#define CONFIG_TSEC1
  444 +#define CONFIG_TSEC1_NAME "eTSEC0"
  445 +#define TSEC1_PHY_ADDR 1
  446 +#define TSEC1_PHYIDX 0
  447 +#define TSEC1_FLAGS TSEC_GIGABIT
  448 +
  449 +/* Options are: eTSEC[0-1] */
  450 +#define CONFIG_ETHPRIME "eTSEC0"
  451 +
  452 +/*
  453 + * Environment
  454 + */
  455 +#if 1
  456 +#define CONFIG_ENV_IS_IN_FLASH 1
  457 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  458 + CONFIG_SYS_MONITOR_LEN)
  459 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  460 +#define CONFIG_ENV_SIZE 0x2000
  461 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  462 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  463 +#else
  464 +#define CONFIG_ENV_IS_NOWHERE
  465 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  466 +#endif
  467 +
  468 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  469 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  470 +
  471 +/*
  472 + * Command line configuration.
  473 + */
  474 +#include <config_cmd_default.h>
  475 +
  476 +#define CONFIG_CMD_I2C
  477 +#define CONFIG_CMD_MII
  478 +#define CONFIG_CMD_NET
  479 +#define CONFIG_CMD_PCI
  480 +#define CONFIG_CMD_PING
  481 +
  482 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  483 +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  484 +
  485 +/*
  486 + * Miscellaneous configurable options
  487 + */
  488 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  489 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  490 +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  491 +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  492 +
  493 +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
  494 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
  495 +#define CONFIG_AUTOBOOT_STOP_STR " "
  496 +
  497 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  498 +
  499 +#define CONFIG_SYS_CONSOLE_INFO_QUIET
  500 +
  501 +/* Print Buffer Size */
  502 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  503 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  504 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  505 +
  506 +/*
  507 + * For booting Linux, the board info and command line data
  508 + * have to be in the first 256 MB of memory, since this is
  509 + * the maximum mapped by the Linux kernel during initialization.
  510 + */
  511 +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  512 +
  513 +/*
  514 + * Core HID Setup
  515 + */
  516 +#define CONFIG_SYS_HID0_INIT 0x000000000
  517 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  518 + HID0_ENABLE_INSTRUCTION_CACHE | \
  519 + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  520 +#define CONFIG_SYS_HID2 HID2_HBE
  521 +
  522 +/*
  523 + * MMU Setup
  524 + */
  525 +
  526 +/* DDR: cache cacheable */
  527 +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
  528 + BATL_MEMCOHERENCE)
  529 +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
  530 + BATU_VS | BATU_VP)
  531 +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  532 +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  533 +
  534 +/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
  535 +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
  536 + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  537 +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
  538 + BATU_VP)
  539 +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  540 +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  541 +
  542 +/* FLASH: icache cacheable, but dcache-inhibit and guarded */
  543 +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
  544 + BATL_MEMCOHERENCE)
  545 +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
  546 + BATU_VS | BATU_VP)
  547 +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
  548 + BATL_CACHEINHIBIT | \
  549 + BATL_GUARDEDSTORAGE)
  550 +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  551 +
  552 +/* Stack in dcache: cacheable, no memory coherence */
  553 +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
  554 +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
  555 + BATU_VS | BATU_VP)
  556 +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  557 +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  558 +
  559 +/*
  560 + * Environment Configuration
  561 + */
  562 +
  563 +#define CONFIG_ENV_OVERWRITE
  564 +
  565 +#if defined(CONFIG_TSEC_ENET)
  566 +#define CONFIG_HAS_ETH0
  567 +#endif
  568 +
  569 +#define CONFIG_BAUDRATE 115200
  570 +
  571 +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  572 +
  573 +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
  574 +
  575 +#define CONFIG_HOSTNAME hrcon
  576 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  577 +#define CONFIG_BOOTFILE "uImage"
  578 +
  579 +#define CONFIG_PREBOOT /* enable preboot variable */
  580 +
  581 +#define CONFIG_EXTRA_ENV_SETTINGS \
  582 + "netdev=eth0\0" \
  583 + "consoledev=ttyS1\0" \
  584 + "u-boot=u-boot.bin\0" \
  585 + "kernel_addr=1000000\0" \
  586 + "fdt_addr=C00000\0" \
  587 + "fdtfile=hrcon.dtb\0" \
  588 + "load=tftp ${loadaddr} ${u-boot}\0" \
  589 + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  590 + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  591 + " +${filesize};cp.b ${fileaddr} " \
  592 + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  593 + "upd=run load update\0" \
  594 +
  595 +#define CONFIG_NFSBOOTCOMMAND \
  596 + "setenv bootargs root=/dev/nfs rw " \
  597 + "nfsroot=$serverip:$rootpath " \
  598 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  599 + "console=$consoledev,$baudrate $othbootargs;" \
  600 + "tftp ${kernel_addr} $bootfile;" \
  601 + "tftp ${fdt_addr} $fdtfile;" \
  602 + "bootm ${kernel_addr} - ${fdt_addr}"
  603 +
  604 +#define CONFIG_MMCBOOTCOMMAND \
  605 + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
  606 + "console=$consoledev,$baudrate $othbootargs;" \
  607 + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
  608 + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
  609 + "bootm ${kernel_addr} - ${fdt_addr}"
  610 +
  611 +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
  612 +
  613 +
  614 +#endif /* __CONFIG_H */
include/gdsys_fpga.h
Diff comments   View file @ 50dcf89
... ... @@ -61,6 +61,22 @@
61 61 u16 y_pos;
62 62 };
63 63  
  64 +struct ihs_mdio {
  65 + u16 control;
  66 + u16 address_data;
  67 + u16 rx_data;
  68 +};
  69 +
  70 +struct ihs_io_ep {
  71 + u16 transmit_data;
  72 + u16 rx_tx_control;
  73 + u16 receive_data;
  74 + u16 rx_tx_status;
  75 + u16 reserved;
  76 + u16 device_address;
  77 + u16 target_address;
  78 +};
  79 +
64 80 #ifdef CONFIG_NEO
65 81 struct ihs_fpga {
66 82 u16 reflection_low; /* 0x0000 */
67 83  
68 84  
... ... @@ -119,12 +135,16 @@
119 135 u16 versions; /* 0x0002 */
120 136 u16 fpga_version; /* 0x0004 */
121 137 u16 fpga_features; /* 0x0006 */
122   - u16 reserved_0[6]; /* 0x0008 */
  138 + u16 reserved_0[1]; /* 0x0008 */
  139 + u16 top_interrupt; /* 0x000a */
  140 + u16 reserved_1[4]; /* 0x000c */
123 141 struct ihs_gpio gpio; /* 0x0014 */
124 142 u16 mpc3w_control; /* 0x001a */
125   - u16 reserved_1[18]; /* 0x001c */
  143 + u16 reserved_2[2]; /* 0x001c */
  144 + struct ihs_io_ep ep; /* 0x0020 */
  145 + u16 reserved_3[9]; /* 0x002e */
126 146 struct ihs_i2c i2c; /* 0x0040 */
127   - u16 reserved_2[10]; /* 0x004c */
  147 + u16 reserved_4[10]; /* 0x004c */
128 148 u16 mc_int; /* 0x0060 */
129 149 u16 mc_int_en; /* 0x0062 */
130 150 u16 mc_status; /* 0x0064 */
131 151  
... ... @@ -135,10 +155,44 @@
135 155 u16 mc_res; /* 0x006e */
136 156 u16 mc_rx_cmd_status; /* 0x0070 */
137 157 u16 mc_rx_data; /* 0x0072 */
138   - u16 reserved_3[69]; /* 0x0074 */
  158 + u16 reserved_5[69]; /* 0x0074 */
139 159 u16 reflection_high; /* 0x00fe */
140 160 struct ihs_osd osd; /* 0x0100 */
141   - u16 reserved_4[889]; /* 0x010e */
  161 + u16 reserved_6[889]; /* 0x010e */
  162 + u16 videomem[31736]; /* 0x0800 */
  163 +};
  164 +#endif
  165 +
  166 +#ifdef CONFIG_HRCON
  167 +struct ihs_fpga {
  168 + u16 reflection_low; /* 0x0000 */
  169 + u16 versions; /* 0x0002 */
  170 + u16 fpga_version; /* 0x0004 */
  171 + u16 fpga_features; /* 0x0006 */
  172 + u16 reserved_0[1]; /* 0x0008 */
  173 + u16 top_interrupt; /* 0x000a */
  174 + u16 reserved_1[4]; /* 0x000c */
  175 + struct ihs_gpio gpio; /* 0x0014 */
  176 + u16 mpc3w_control; /* 0x001a */
  177 + u16 reserved_2[2]; /* 0x001c */
  178 + struct ihs_io_ep ep; /* 0x0020 */
  179 + u16 reserved_3[9]; /* 0x002e */
  180 + struct ihs_i2c i2c; /* 0x0040 */
  181 + u16 reserved_4[10]; /* 0x004c */
  182 + u16 mc_int; /* 0x0060 */
  183 + u16 mc_int_en; /* 0x0062 */
  184 + u16 mc_status; /* 0x0064 */
  185 + u16 mc_control; /* 0x0066 */
  186 + u16 mc_tx_data; /* 0x0068 */
  187 + u16 mc_tx_address; /* 0x006a */
  188 + u16 mc_tx_cmd; /* 0x006c */
  189 + u16 mc_res; /* 0x006e */
  190 + u16 mc_rx_cmd_status; /* 0x0070 */
  191 + u16 mc_rx_data; /* 0x0072 */
  192 + u16 reserved_5[69]; /* 0x0074 */
  193 + u16 reflection_high; /* 0x00fe */
  194 + struct ihs_osd osd; /* 0x0100 */
  195 + u16 reserved_6[889]; /* 0x010e */
142 196 u16 videomem[31736]; /* 0x0800 */
143 197 };
144 198 #endif