ARM: rmobile: salvator-x: Add SD support

Add support for the SD card slots on the Salvator-X board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

ARM: rmobile: salvator-x: Add SD support
Add support for the SD card slots on the Salvator-X board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut · Nobuhiro Iwamatsu
1 parent 8474681c3e
Showing 3 changed files with 102 additions and 5 deletions Side-by-side Diff
board/renesas/salvator-x/salvator-x.c
configs/salvator-x_defconfig
include/configs/salvator-x.h
@@ -2,7 +2,7 @@
  * board/renesas/salvator-x/salvator-x.c
  *     This file is Salvator-X board support.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * SPDX-License-Identifier: GPL-2.0+
@@ -22,6 +22,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/rmobile.h>
 #include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
 #include <i2c.h>
 #include <mmc.h>
  
  
  
  
@@ -48,14 +49,32 @@
 #define TMU0_MSTP125		BIT(25)	/* secure */
 #define TMU1_MSTP124		BIT(24)	/* non-secure */
 #define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
+#define SD0_MSTP314		BIT(14)
+#define SD1_MSTP313		BIT(13)
+#define SD2_MSTP312		BIT(12)	/* either MMC0 */
+#define SD3_MSTP311		BIT(11)	/* either MMC1 */
  
+#define SD0CKCR			0xE6150074
+#define SD1CKCR			0xE6150078
+#define SD2CKCR			0xE6150268
+#define SD3CKCR			0xE615026C
+
 int board_early_init_f(void)
 {
 	/* TMU0,1 */		/* which use ? */
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
 	/* SCIF2 */
 	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+	/* eMMC */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
+	/* SDHI0, 3 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
  
+	writel(0, SD0CKCR);
+	writel(0, SD1CKCR);
+	writel(0, SD2CKCR);
+	writel(0, SD3CKCR);
+
 	return 0;
 }
  
@@ -82,6 +101,74 @@
  
 	return 0;
 }
+
+#ifdef CONFIG_SH_SDHI
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+	/* SDHI0 */
+	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD0_CLK, NULL);
+	gpio_request(GPIO_GFN_SD0_CMD, NULL);
+	gpio_request(GPIO_GFN_SD0_CD, NULL);
+	gpio_request(GPIO_GFN_SD0_WP, NULL);
+
+	gpio_request(GPIO_GP_5_2, NULL);
+	gpio_request(GPIO_GP_5_1, NULL);
+	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
+	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	if (ret)
+		return ret;
+
+	/* SDHI1/SDHI2 eMMC */
+	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_CLK, NULL);
+	gpio_request(GPIO_GFN_SD2_CMD, NULL);
+	gpio_request(GPIO_GP_5_3, NULL);
+	gpio_request(GPIO_GP_5_9, NULL);
+	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
+	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	if (ret)
+		return ret;
+
+	/* SDHI3 */
+	gpio_request(GPIO_GFN_SD3_DAT0, NULL);	/* GP_4_9 */
+	gpio_request(GPIO_GFN_SD3_DAT1, NULL);	/* GP_4_10 */
+	gpio_request(GPIO_GFN_SD3_DAT2, NULL);	/* GP_4_11 */
+	gpio_request(GPIO_GFN_SD3_DAT3, NULL);	/* GP_4_12 */
+	gpio_request(GPIO_GFN_SD3_CLK, NULL);	/* GP_4_7 */
+	gpio_request(GPIO_GFN_SD3_CMD, NULL);	/* GP_4_8 */
+	/* IPSR10 */
+	gpio_request(GPIO_FN_SD3_CD, NULL);
+	gpio_request(GPIO_FN_SD3_WP, NULL);
+
+	gpio_request(GPIO_GP_3_15, NULL);
+	gpio_request(GPIO_GP_3_14, NULL);
+	gpio_direction_output(GPIO_GP_3_15, 1);	/* power on */
+	gpio_direction_output(GPIO_GP_3_14, 1);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	return ret;
+}
+#endif
  
 int dram_init(void)
 {
@@ -8,10 +8,12 @@
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_FDT=y
 CONFIG_R8A7795=y
-# CONFIG_CMD_IMI is not set
+CONFIG_SH_SDHI=y
 # CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
 CONFIG_DOS_PARTITION=y
-# CONFIG_MMC is not set
+CONFIG_MMC=y
+CONFIG_GENERIC_MMC=y
 CONFIG_OF_LIBFDT=y
@@ -24,7 +24,6 @@
  
 /* [A] Hyper Flash */
 /* use to RPC(SPI Multi I/O Bus Controller) */
-#define CONFIG_ENV_IS_NOWHERE
  
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
@@ -44,6 +43,15 @@
 #define CONFIG_GICV2
 #define GICD_BASE	0xF1010000
 #define GICC_BASE	0xF1020000
+
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ		200000000
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
  
 /* Module stop status bits */
 /* MFIS, SCIF1 */
...	...	@@ -2,7 +2,7 @@
2	2	* board/renesas/salvator-x/salvator-x.c
3	3	* This file is Salvator-X board support.
4	4	*
5		- * Copyright (C) 2015 Renesas Electronics Corporation
	5	+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
6	6	* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7	7	*
8	8	* SPDX-License-Identifier: GPL-2.0+
...	...	@@ -22,6 +22,7 @@
22	22	#include <asm/arch/gpio.h>
23	23	#include <asm/arch/rmobile.h>
24	24	#include <asm/arch/rcar-mstp.h>
	25	+#include <asm/arch/sh_sdhi.h>
25	26	#include <i2c.h>
26	27	#include <mmc.h>
27	28
28	29
29	30
30	31
...	...	@@ -48,14 +49,32 @@
48	49	#define TMU0_MSTP125 BIT(25) /* secure */
49	50	#define TMU1_MSTP124 BIT(24) /* non-secure */
50	51	#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
	52	+#define SD0_MSTP314 BIT(14)
	53	+#define SD1_MSTP313 BIT(13)
	54	+#define SD2_MSTP312 BIT(12) /* either MMC0 */
	55	+#define SD3_MSTP311 BIT(11) /* either MMC1 */
51	56
	57	+#define SD0CKCR 0xE6150074
	58	+#define SD1CKCR 0xE6150078
	59	+#define SD2CKCR 0xE6150268
	60	+#define SD3CKCR 0xE615026C
	61	+
52	62	int board_early_init_f(void)
53	63	{
54	64	/* TMU0,1 / / which use ? */
55	65	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 \| TMU1_MSTP124);
56	66	/* SCIF2 */
57	67	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
	68	+ /* eMMC */
	69	+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 \| SD2_MSTP312);
	70	+ /* SDHI0, 3 */
	71	+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 \| SD3_MSTP311);
58	72
	73	+ writel(0, SD0CKCR);
	74	+ writel(0, SD1CKCR);
	75	+ writel(0, SD2CKCR);
	76	+ writel(0, SD3CKCR);
	77	+
59	78	return 0;
60	79	}
61	80
...	...	@@ -82,6 +101,74 @@
82	101
83	102	return 0;
84	103	}
	104	+
	105	+#ifdef CONFIG_SH_SDHI
	106	+int board_mmc_init(bd_t *bis)
	107	+{
	108	+ int ret = -ENODEV;
	109	+
	110	+ /* SDHI0 */
	111	+ gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	112	+ gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	113	+ gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	114	+ gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	115	+ gpio_request(GPIO_GFN_SD0_CLK, NULL);
	116	+ gpio_request(GPIO_GFN_SD0_CMD, NULL);
	117	+ gpio_request(GPIO_GFN_SD0_CD, NULL);
	118	+ gpio_request(GPIO_GFN_SD0_WP, NULL);
	119	+
	120	+ gpio_request(GPIO_GP_5_2, NULL);
	121	+ gpio_request(GPIO_GP_5_1, NULL);
	122	+ gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
	123	+ gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
	124	+
	125	+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
	126	+ SH_SDHI_QUIRK_64BIT_BUF);
	127	+ if (ret)
	128	+ return ret;
	129	+
	130	+ /* SDHI1/SDHI2 eMMC */
	131	+ gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	132	+ gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	133	+ gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	134	+ gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	135	+ gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	136	+ gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	137	+ gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	138	+ gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	139	+ gpio_request(GPIO_GFN_SD2_CLK, NULL);
	140	+ gpio_request(GPIO_GFN_SD2_CMD, NULL);
	141	+ gpio_request(GPIO_GP_5_3, NULL);
	142	+ gpio_request(GPIO_GP_5_9, NULL);
	143	+ gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
	144	+ gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
	145	+
	146	+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
	147	+ SH_SDHI_QUIRK_64BIT_BUF);
	148	+ if (ret)
	149	+ return ret;
	150	+
	151	+ /* SDHI3 */
	152	+ gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
	153	+ gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
	154	+ gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
	155	+ gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
	156	+ gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
	157	+ gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
	158	+ /* IPSR10 */
	159	+ gpio_request(GPIO_FN_SD3_CD, NULL);
	160	+ gpio_request(GPIO_FN_SD3_WP, NULL);
	161	+
	162	+ gpio_request(GPIO_GP_3_15, NULL);
	163	+ gpio_request(GPIO_GP_3_14, NULL);
	164	+ gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
	165	+ gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
	166	+
	167	+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
	168	+ SH_SDHI_QUIRK_64BIT_BUF);
	169	+ return ret;
	170	+}
	171	+#endif
85	172
86	173	int dram_init(void)
87	174	{
...	...	@@ -8,10 +8,12 @@
8	8	CONFIG_CMD_BOOTZ=y
9	9	CONFIG_CMD_FDT=y
10	10	CONFIG_R8A7795=y
11		-# CONFIG_CMD_IMI is not set
	11	+CONFIG_SH_SDHI=y
12	12	# CONFIG_CMD_IMLS is not set
13		-# CONFIG_CMD_XIMG is not set
	13	+CONFIG_CMD_EDITENV=y
	14	+CONFIG_CMD_SAVEENV=y
14	15	CONFIG_DOS_PARTITION=y
15		-# CONFIG_MMC is not set
	16	+CONFIG_MMC=y
	17	+CONFIG_GENERIC_MMC=y
16	18	CONFIG_OF_LIBFDT=y
...	...	@@ -24,7 +24,6 @@
24	24
25	25	/* [A] Hyper Flash */
26	26	/* use to RPC(SPI Multi I/O Bus Controller) */
27		-#define CONFIG_ENV_IS_NOWHERE
28	27
29	28	/* Board Clock */
30	29	/* XTAL_CLK : 33.33MHz */
...	...	@@ -44,6 +43,15 @@
44	43	#define CONFIG_GICV2
45	44	#define GICD_BASE 0xF1010000
46	45	#define GICC_BASE 0xF1020000
	46	+
	47	+/* SDHI */
	48	+#define CONFIG_SH_SDHI_FREQ 200000000
	49	+
	50	+/* Environment in eMMC, at the end of 2nd "boot sector" */
	51	+#define CONFIG_ENV_IS_IN_MMC
	52	+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
	53	+#define CONFIG_SYS_MMC_ENV_DEV 1
	54	+#define CONFIG_SYS_MMC_ENV_PART 2
47	55
48	56	/* Module stop status bits */
49	57	/* MFIS, SCIF1 */