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Commit 5122dfae5d3cd68e0b6e5e08597df91ba79770aa

Authored by Shengzhou Liu
Committed by York Sun
1 parent c665c473b6
Exists in v2017.01-smarct4x and in 41 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/85xx: add T4080 SoC support 

The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>

Showing 11 changed files with 57 additions and 10 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/Makefile
Diff comments   View file @ 5122dfa
... ... @@ -44,6 +44,7 @@
44 44 obj-$(CONFIG_PPC_P5040) += p5040_ids.o
45 45 obj-$(CONFIG_PPC_T4240) += t4240_ids.o
46 46 obj-$(CONFIG_PPC_T4160) += t4240_ids.o
  47 +obj-$(CONFIG_PPC_T4080) += t4240_ids.o
47 48 obj-$(CONFIG_PPC_B4420) += b4860_ids.o
48 49 obj-$(CONFIG_PPC_B4860) += b4860_ids.o
49 50 obj-$(CONFIG_PPC_T1040) += t1040_ids.o
... ... @@ -88,6 +89,7 @@
88 89 obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
89 90 obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
90 91 obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
  92 +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
91 93 obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
92 94 obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
93 95 obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
arch/powerpc/cpu/mpc85xx/cpu.c
Diff comments   View file @ 5122dfa
... ... @@ -77,6 +77,30 @@
77 77 major = SVR_MAJ(svr);
78 78 minor = SVR_MIN(svr);
79 79  
  80 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  81 + if (SVR_SOC_VER(svr) == SVR_T4080) {
  82 + ccsr_rcpm_t *rcpm =
  83 + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  84 +
  85 + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
  86 + FSL_CORENET_DEVDISR2_DTSEC1_9);
  87 + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
  88 + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
  89 +
  90 + /* It needs SW to disable core4~7 as HW design sake on T4080 */
  91 + for (i = 4; i < 8; i++)
  92 + cpu_disable(i);
  93 +
  94 + /* request core4~7 into PH20 state, prior to entering PCL10
  95 + * state, all cores in cluster should be placed in PH20 state.
  96 + */
  97 + setbits_be32(&rcpm->pcph20setr, 0xf0);
  98 +
  99 + /* put the 2nd cluster into PCL10 state */
  100 + setbits_be32(&rcpm->clpcl10setr, 1 << 1);
  101 + }
  102 +#endif
  103 +
80 104 if (cpu_numcores() > 1) {
81 105 #ifndef CONFIG_MP
82 106 puts("Unicore software on multiprocessor system!!\n"
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 5122dfa
... ... @@ -462,9 +462,16 @@
462 462 int enable_cluster_l2(void)
463 463 {
464 464 int i = 0;
465   - u32 cluster;
  465 + u32 cluster, svr = get_svr();
466 466 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
467 467 struct ccsr_cluster_l2 __iomem *l2cache;
  468 +
  469 + /* only the L2 of first cluster should be enabled as expected on T4080,
  470 + * but there is no EOC in the first cluster as HW sake, so return here
  471 + * to skip enabling L2 cache of the 2nd cluster.
  472 + */
  473 + if (SVR_SOC_VER(svr) == SVR_T4080)
  474 + return 0;
468 475  
469 476 cluster = in_be32(&gur->tp_cluster[i].lower);
470 477 if (cluster & TP_CLUSTER_EOC)
arch/powerpc/cpu/mpc85xx/speed.c
Diff comments   View file @ 5122dfa
... ... @@ -123,7 +123,8 @@
123 123 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
124 124 * it uses 6.
125 125 */
126   -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
  126 +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  127 + defined(CONFIG_PPC_T4080)
127 128 if (SVR_MAJ(get_svr()) >= 2)
128 129 mem_pll_rat *= 2;
129 130 #endif
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
Diff comments   View file @ 5122dfa
... ... @@ -172,7 +172,7 @@
172 172 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
173 173 {}
174 174 };
175   -#elif defined(CONFIG_PPC_T4160)
  175 +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
176 176 static const struct serdes_config serdes1_cfg_tbl[] = {
177 177 /* SerDes 1 */
178 178 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
arch/powerpc/cpu/mpc8xxx/cpu.c
Diff comments   View file @ 5122dfa
... ... @@ -62,6 +62,7 @@
62 62 CPU_TYPE_ENTRY(T4240, T4240, 0),
63 63 CPU_TYPE_ENTRY(T4120, T4120, 0),
64 64 CPU_TYPE_ENTRY(T4160, T4160, 0),
  65 + CPU_TYPE_ENTRY(T4080, T4080, 4),
65 66 CPU_TYPE_ENTRY(B4860, B4860, 0),
66 67 CPU_TYPE_ENTRY(G4860, G4860, 0),
67 68 CPU_TYPE_ENTRY(G4060, G4060, 0),
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ 5122dfa
... ... @@ -595,7 +595,8 @@
595 595 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
596 596 #define CONFIG_ESDHC_HC_BLK_ADDR
597 597  
598   -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
  598 +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  599 + defined(CONFIG_PPC_T4080)
599 600 #define CONFIG_E6500
600 601 #define CONFIG_SYS_PPC64 /* 64-bit core */
601 602 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
602 603  
603 604  
... ... @@ -611,13 +612,18 @@
611 612 #define CONFIG_SYS_NUM_FM2_10GEC 2
612 613 #define CONFIG_NUM_DDR_CONTROLLERS 3
613 614 #else
614   -#define CONFIG_MAX_CPUS 8
615   -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
616   -#define CONFIG_SYS_NUM_FM1_DTSEC 7
  615 +#define CONFIG_SYS_NUM_FM1_DTSEC 6
617 616 #define CONFIG_SYS_NUM_FM1_10GEC 1
618   -#define CONFIG_SYS_NUM_FM2_DTSEC 7
  617 +#define CONFIG_SYS_NUM_FM2_DTSEC 8
619 618 #define CONFIG_SYS_NUM_FM2_10GEC 1
620 619 #define CONFIG_NUM_DDR_CONTROLLERS 2
  620 +#if defined(CONFIG_PPC_T4160)
  621 +#define CONFIG_MAX_CPUS 8
  622 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  623 +#elif defined(CONFIG_PPC_T4080)
  624 +#define CONFIG_MAX_CPUS 4
  625 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
  626 +#endif
621 627 #endif
622 628 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
623 629 #define CONFIG_SYS_FSL_NUM_LAWS 32
arch/powerpc/include/asm/fsl_errata.h
Diff comments   View file @ 5122dfa
... ... @@ -16,6 +16,7 @@
16 16 u32 svr = get_svr();
17 17 if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
18 18 ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
  19 + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
19 20 ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
20 21 ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
21 22 ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
... ... @@ -49,6 +50,7 @@
49 50 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
50 51 case SVR_T4240:
51 52 case SVR_T4160:
  53 + case SVR_T4080:
52 54 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
53 55 case SVR_T1040:
54 56 return IS_SVR_REV(svr, 1, 0);
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ 5122dfa
... ... @@ -1748,7 +1748,8 @@
1748 1748 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
1749 1749 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
1750 1750 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1751   -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
  1751 +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  1752 + defined(CONFIG_PPC_T4080)
1752 1753 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1753 1754 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1754 1755 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
... ... @@ -1848,7 +1849,8 @@
1848 1849 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1849 1850 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1850 1851 #endif
1851   -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
  1852 +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  1853 + defined(CONFIG_PPC_T4080)
1852 1854 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1853 1855 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1854 1856 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
arch/powerpc/include/asm/processor.h
Diff comments   View file @ 5122dfa
... ... @@ -1111,6 +1111,7 @@
1111 1111 #define SVR_T4240 0x824000
1112 1112 #define SVR_T4120 0x824001
1113 1113 #define SVR_T4160 0x824100
  1114 +#define SVR_T4080 0x824102
1114 1115 #define SVR_C291 0x850000
1115 1116 #define SVR_C292 0x850020
1116 1117 #define SVR_C293 0x850030
drivers/net/fm/Makefile
Diff comments   View file @ 5122dfa
... ... @@ -32,6 +32,7 @@
32 32 obj-$(CONFIG_PPC_T2081) += t2080.o
33 33 obj-$(CONFIG_PPC_T4240) += t4240.o
34 34 obj-$(CONFIG_PPC_T4160) += t4240.o
  35 +obj-$(CONFIG_PPC_T4080) += t4240.o
35 36 obj-$(CONFIG_PPC_B4420) += b4860.o
36 37 obj-$(CONFIG_PPC_B4860) += b4860.o