Commit 517c5dfed5107fe1d77dd1e003c3c076bcf279e6
Committed by
Albert ARIBAUD
Albert ARIBAUD
1 parent
66463e60df
Exists in
master
and in
54 other branches
update/fix AcTux1 board
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Showing 5 changed files with 124 additions and 93 deletions Side-by-side Diff
board/actux1/actux1.c
| ... | ... | @@ -37,71 +37,79 @@ |
| 37 | 37 | #include <asm/arch/ixp425.h> |
| 38 | 38 | #include <asm/io.h> |
| 39 | 39 | #include <miiphy.h> |
| 40 | +#ifdef CONFIG_PCI | |
| 41 | +#include <pci.h> | |
| 42 | +#include <asm/arch/ixp425pci.h> | |
| 43 | +#endif | |
| 40 | 44 | |
| 41 | 45 | #include "actux1_hw.h" |
| 42 | 46 | |
| 43 | 47 | DECLARE_GLOBAL_DATA_PTR; |
| 44 | 48 | |
| 45 | -int board_init (void) | |
| 49 | +int board_early_init_f(void) | |
| 46 | 50 | { |
| 51 | + /* CS5: Debug port */ | |
| 52 | + writel(0x9d520003, IXP425_EXP_CS5); | |
| 53 | + /* CS6: HwRel */ | |
| 54 | + writel(0x81860001, IXP425_EXP_CS6); | |
| 55 | + /* CS7: LEDs */ | |
| 56 | + writel(0x80900003, IXP425_EXP_CS7); | |
| 57 | + return 0; | |
| 58 | +} | |
| 59 | + | |
| 60 | +int board_init(void) | |
| 61 | +{ | |
| 47 | 62 | gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; |
| 48 | 63 | |
| 49 | 64 | /* adress of boot parameters */ |
| 50 | 65 | gd->bd->bi_boot_params = 0x00000100; |
| 51 | 66 | |
| 52 | - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); | |
| 53 | - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); | |
| 67 | + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); | |
| 68 | + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); | |
| 54 | 69 | |
| 55 | - /* Setup GPIO's for PCI INTA */ | |
| 56 | - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA); | |
| 57 | - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA); | |
| 70 | + /* Setup GPIOs for PCI INTA */ | |
| 71 | + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); | |
| 72 | + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); | |
| 58 | 73 | |
| 59 | - /* Setup GPIO's for 33MHz clock output */ | |
| 60 | - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); | |
| 61 | - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); | |
| 62 | - *IXP425_GPIO_GPCLKR = 0x011001FF; | |
| 74 | + /* Setup GPIOs for 33MHz clock output */ | |
| 75 | + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); | |
| 76 | + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); | |
| 77 | + writel(0x011001FF, IXP425_GPIO_GPCLKR); | |
| 63 | 78 | |
| 64 | - /* CS5: Debug port */ | |
| 65 | - *IXP425_EXP_CS5 = 0x9d520003; | |
| 66 | - /* CS6: HwRel */ | |
| 67 | - *IXP425_EXP_CS6 = 0x81860001; | |
| 68 | - /* CS7: LEDs */ | |
| 69 | - *IXP425_EXP_CS7 = 0x80900003; | |
| 79 | + udelay(533); | |
| 80 | + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); | |
| 70 | 81 | |
| 71 | - udelay (533); | |
| 72 | - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); | |
| 82 | + ACTUX1_LED1(2); | |
| 83 | + ACTUX1_LED2(2); | |
| 84 | + ACTUX1_LED3(0); | |
| 85 | + ACTUX1_LED4(0); | |
| 86 | + ACTUX1_LED5(0); | |
| 87 | + ACTUX1_LED6(0); | |
| 88 | + ACTUX1_LED7(0); | |
| 73 | 89 | |
| 74 | - ACTUX1_LED1 (2); | |
| 75 | - ACTUX1_LED2 (2); | |
| 76 | - ACTUX1_LED3 (0); | |
| 77 | - ACTUX1_LED4 (0); | |
| 78 | - ACTUX1_LED5 (0); | |
| 79 | - ACTUX1_LED6 (0); | |
| 80 | - ACTUX1_LED7 (0); | |
| 90 | + ACTUX1_HS(ACTUX1_HS_DCD); | |
| 81 | 91 | |
| 82 | - ACTUX1_HS (ACTUX1_HS_DCD); | |
| 83 | - | |
| 84 | 92 | return 0; |
| 85 | 93 | } |
| 86 | 94 | |
| 87 | 95 | /* |
| 88 | 96 | * Check Board Identity |
| 89 | 97 | */ |
| 90 | -int checkboard (void) | |
| 98 | +int checkboard(void) | |
| 91 | 99 | { |
| 92 | 100 | char buf[64]; |
| 93 | 101 | int i = getenv_f("serial#", buf, sizeof(buf)); |
| 94 | 102 | |
| 95 | - puts ("Board: AcTux-1 rev."); | |
| 96 | - putc (ACTUX1_BOARDREL + 'A' - 1); | |
| 103 | + puts("Board: AcTux-1 rev."); | |
| 104 | + putc(ACTUX1_BOARDREL + 'A' - 1); | |
| 97 | 105 | |
| 98 | 106 | if (i > 0) { |
| 99 | 107 | puts(", serial# "); |
| 100 | 108 | puts(buf); |
| 101 | 109 | } |
| 102 | - putc ('\n'); | |
| 110 | + putc('\n'); | |
| 103 | 111 | |
| 104 | - return (0); | |
| 112 | + return 0; | |
| 105 | 113 | } |
| 106 | 114 | |
| 107 | 115 | /************************************************************************* |
| 108 | 116 | |
| 109 | 117 | |
| 110 | 118 | |
| 111 | 119 | |
| 112 | 120 | |
| 113 | 121 | |
| 114 | 122 | |
| 115 | 123 | |
| ... | ... | @@ -110,39 +118,36 @@ |
| 110 | 118 | * 1 = Rev. A |
| 111 | 119 | * 2 = Rev. B |
| 112 | 120 | *************************************************************************/ |
| 113 | -u32 get_board_rev (void) | |
| 121 | +u32 get_board_rev(void) | |
| 114 | 122 | { |
| 115 | 123 | return ACTUX1_BOARDREL; |
| 116 | 124 | } |
| 117 | 125 | |
| 118 | -int dram_init (void) | |
| 126 | +int dram_init(void) | |
| 119 | 127 | { |
| 120 | - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
| 121 | - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
| 122 | - | |
| 123 | - return (0); | |
| 128 | + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); | |
| 129 | + return 0; | |
| 124 | 130 | } |
| 125 | 131 | |
| 126 | -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) | |
| 127 | -extern struct pci_controller hose; | |
| 128 | -extern void pci_ixp_init (struct pci_controller *hose); | |
| 129 | 132 | |
| 130 | -void pci_init_board (void) | |
| 133 | +#ifdef CONFIG_PCI | |
| 134 | +struct pci_controller hose; | |
| 135 | + | |
| 136 | +void pci_init_board(void) | |
| 131 | 137 | { |
| 132 | - extern void pci_ixp_init (struct pci_controller *hose); | |
| 133 | - pci_ixp_init (&hose); | |
| 138 | + pci_ixp_init(&hose); | |
| 134 | 139 | } |
| 135 | 140 | #endif |
| 136 | 141 | |
| 137 | -void reset_phy (void) | |
| 142 | +void reset_phy(void) | |
| 138 | 143 | { |
| 139 | 144 | u16 id1, id2; |
| 140 | 145 | |
| 141 | 146 | /* initialize the PHY */ |
| 142 | - miiphy_reset ("NPE0", CONFIG_PHY_ADDR); | |
| 147 | + miiphy_reset("NPE0", CONFIG_PHY_ADDR); | |
| 143 | 148 | |
| 144 | - miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); | |
| 145 | - miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); | |
| 149 | + miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); | |
| 150 | + miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); | |
| 146 | 151 | |
| 147 | 152 | id2 &= 0xFFF0; /* mask out revision bits */ |
| 148 | 153 | |
| 149 | 154 | |
| ... | ... | @@ -153,10 +158,10 @@ |
| 153 | 158 | * LED2 (unused) = LINK, |
| 154 | 159 | * LED3(red) = Coll |
| 155 | 160 | */ |
| 156 | - miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); | |
| 161 | + miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); | |
| 157 | 162 | } else if (id1 == 0x143 && id2 == 0xbc30) { |
| 158 | 163 | /* BCM5241: default values are OK */ |
| 159 | 164 | } else |
| 160 | - printf ("unknown ethernet PHY ID: %x %x\n", id1, id2); | |
| 165 | + printf("unknown ethernet PHY ID: %x %x\n", id1, id2); | |
| 161 | 166 | } |
board/actux1/config.mk
board/actux1/u-boot.lds
| ... | ... | @@ -30,15 +30,15 @@ |
| 30 | 30 | |
| 31 | 31 | . = ALIGN (4); |
| 32 | 32 | .text : { |
| 33 | - arch/arm/cpu/ixp/start.o(.text) | |
| 34 | - lib/string.o(.text) | |
| 35 | - lib/vsprintf.o(.text) | |
| 36 | - arch/arm/lib/board.o(.text) | |
| 37 | - common/dlmalloc.o(.text) | |
| 38 | - arch/arm/cpu/ixp/cpu.o(.text) | |
| 33 | + arch/arm/cpu/ixp/start.o(.text*) | |
| 34 | + net/libnet.o(.text*) | |
| 35 | + board/actux1/libactux1.o(.text*) | |
| 36 | + arch/arm/cpu/ixp/libixp.o(.text*) | |
| 37 | + drivers/serial/libserial.o(.text*) | |
| 38 | + | |
| 39 | 39 | . = env_offset; |
| 40 | 40 | common/env_embedded.o(.ppcenv) |
| 41 | - * (.text) | |
| 41 | + *(.text*) | |
| 42 | 42 | } |
| 43 | 43 | |
| 44 | 44 | . = ALIGN (4); |
| ... | ... | @@ -47,7 +47,7 @@ |
| 47 | 47 | } |
| 48 | 48 | . = ALIGN (4); |
| 49 | 49 | .data : { |
| 50 | - *(.data) | |
| 50 | + *(.data*) | |
| 51 | 51 | } |
| 52 | 52 | . = ALIGN (4); |
| 53 | 53 | .got : { |
| 54 | 54 | |
| 55 | 55 | |
| ... | ... | @@ -61,11 +61,28 @@ |
| 61 | 61 | __u_boot_cmd_end =.; |
| 62 | 62 | |
| 63 | 63 | . = ALIGN (4); |
| 64 | - __bss_start =.; | |
| 65 | - .bss (NOLOAD): { | |
| 66 | - *(.bss) | |
| 67 | - . = ALIGN(4); | |
| 64 | + .rel.dyn : { | |
| 65 | + __rel_dyn_start = .; | |
| 66 | + *(.rel*) | |
| 67 | + __rel_dyn_end = .; | |
| 68 | 68 | } |
| 69 | + | |
| 70 | + .dynsym : { | |
| 71 | + __dynsym_start = .; | |
| 72 | + *(.dynsym) | |
| 73 | + } | |
| 74 | + | |
| 75 | + .bss __rel_dyn_start (OVERLAY) : { | |
| 76 | + __bss_start = .; | |
| 77 | + *(.bss*) | |
| 78 | + . = ALIGN(4); | |
| 79 | + _end = .; | |
| 80 | + } | |
| 69 | 81 | __bss_end__ =.; |
| 82 | + /DISCARD/ : { *(.dynstr*) } | |
| 83 | + /DISCARD/ : { *(.dynamic*) } | |
| 84 | + /DISCARD/ : { *(.plt*) } | |
| 85 | + /DISCARD/ : { *(.interp*) } | |
| 86 | + /DISCARD/ : { *(.gnu*) } | |
| 70 | 87 | } |
boards.cfg
| ... | ... | @@ -164,7 +164,10 @@ |
| 164 | 164 | harmony arm armv7 harmony nvidia tegra2 |
| 165 | 165 | seaboard arm armv7 seaboard nvidia tegra2 |
| 166 | 166 | u8500_href arm armv7 u8500 st-ericsson u8500 |
| 167 | -actux1 arm ixp | |
| 167 | +actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 | |
| 168 | +actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 | |
| 169 | +actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB | |
| 170 | +actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB | |
| 168 | 171 | actux2 arm ixp |
| 169 | 172 | actux3 arm ixp |
| 170 | 173 | actux4 arm ixp |
include/configs/actux1.h
| ... | ... | @@ -26,13 +26,6 @@ |
| 26 | 26 | #ifndef __CONFIG_H |
| 27 | 27 | #define __CONFIG_H |
| 28 | 28 | |
| 29 | -/* 1: modified board with 32MB DRAM */ | |
| 30 | -#define CONFIG_ACTUX1_32MB 0 | |
| 31 | -/* 1: 2*2MB FLASH (standard) */ | |
| 32 | -#define CONFIG_ACTUX1_FLASH2X2 1 | |
| 33 | -/* 1: 1*8MB FLASH (upgraded boards) */ | |
| 34 | -#define CONFIG_ACTUX1_FLASH1X8 0 | |
| 35 | - | |
| 36 | 29 | #define CONFIG_IXP425 1 |
| 37 | 30 | #define CONFIG_ACTUX1 1 |
| 38 | 31 | |
| 39 | 32 | |
| ... | ... | @@ -44,12 +37,12 @@ |
| 44 | 37 | #define CONFIG_BAUDRATE 115200 |
| 45 | 38 | #define CONFIG_BOOTDELAY 3 |
| 46 | 39 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 40 | +#define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 41 | +#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" | |
| 47 | 42 | |
| 48 | 43 | /*************************************************************** |
| 49 | 44 | * U-boot generic defines start here. |
| 50 | 45 | ***************************************************************/ |
| 51 | -#undef CONFIG_USE_IRQ | |
| 52 | - | |
| 53 | 46 | /* |
| 54 | 47 | * Size of malloc() pool |
| 55 | 48 | */ |
| ... | ... | @@ -62,8 +55,13 @@ |
| 62 | 55 | #include <config_cmd_default.h> |
| 63 | 56 | |
| 64 | 57 | #define CONFIG_CMD_ELF |
| 65 | -#undef CONFIG_CMD_PCI | |
| 66 | -#undef CONFIG_PCI | |
| 58 | +#ifdef CONFIG_PCI | |
| 59 | +#define CONFIG_CMD_PCI | |
| 60 | +#define CONFIG_PCI_PNP | |
| 61 | +#define CONFIG_IXP_PCI | |
| 62 | +#define CONFIG_PCI_SCAN_SHOW | |
| 63 | +#define CONFIG_CMD_PCI_ENUM | |
| 64 | +#endif | |
| 67 | 65 | |
| 68 | 66 | #define CONFIG_BOOTCOMMAND "run boot_flash" |
| 69 | 67 | /* enable passing of ATAGs */ |
| ... | ... | @@ -93,8 +91,9 @@ |
| 93 | 91 | #define CONFIG_SYS_MEMTEST_START 0x00400000 |
| 94 | 92 | #define CONFIG_SYS_MEMTEST_END 0x00800000 |
| 95 | 93 | |
| 96 | -/* spec says 66.666 MHz, but it appears to be 33 */ | |
| 97 | -#define CONFIG_SYS_HZ 3333333 | |
| 94 | +/* timer clock - 2* OSC_IN system clock */ | |
| 95 | +#define CONFIG_IXP425_TIMER_CLK 66666666 | |
| 96 | +#define CONFIG_SYS_HZ 1000 | |
| 98 | 97 | |
| 99 | 98 | /* default load address */ |
| 100 | 99 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 |
| ... | ... | @@ -109,10 +108,6 @@ |
| 109 | 108 | * The stack sizes are set up in start.S using the settings below |
| 110 | 109 | */ |
| 111 | 110 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
| 112 | -#ifdef CONFIG_USE_IRQ | |
| 113 | -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
| 114 | -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
| 115 | -#endif | |
| 116 | 111 | |
| 117 | 112 | /* Expansion bus settings */ |
| 118 | 113 | #define CONFIG_SYS_EXP_CS0 0xbd113842 |
| 119 | 114 | |
| ... | ... | @@ -120,9 +115,9 @@ |
| 120 | 115 | /* SDRAM settings */ |
| 121 | 116 | #define CONFIG_NR_DRAM_BANKS 1 |
| 122 | 117 | #define PHYS_SDRAM_1 0x00000000 |
| 123 | -#define CONFIG_SYS_DRAM_BASE 0x00000000 | |
| 118 | +#define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
| 124 | 119 | |
| 125 | -#if CONFIG_ACTUX1_32MB | |
| 120 | +#ifdef CONFIG_RAM_32MB | |
| 126 | 121 | # define CONFIG_SYS_SDR_CONFIG 0x18 |
| 127 | 122 | # define PHYS_SDRAM_1_SIZE 0x02000000 |
| 128 | 123 | # define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
| 129 | 124 | |
| ... | ... | @@ -136,8 +131,11 @@ |
| 136 | 131 | # define CONFIG_SYS_DRAM_SIZE 0x01000000 |
| 137 | 132 | #endif |
| 138 | 133 | |
| 134 | + | |
| 135 | + | |
| 139 | 136 | /* FLASH organization */ |
| 140 | -#if CONFIG_ACTUX1_FLASH2X2 | |
| 137 | +#define CONFIG_SYS_TEXT_BASE 0x50000000 | |
| 138 | +#ifdef CONFIG_FLASH2X2 | |
| 141 | 139 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 |
| 142 | 140 | /* max number of sectors on one chip */ |
| 143 | 141 | # define CONFIG_SYS_MAX_FLASH_SECT 40 |
| ... | ... | @@ -145,7 +143,7 @@ |
| 145 | 143 | # define PHYS_FLASH_2 0x50200000 |
| 146 | 144 | # define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
| 147 | 145 | #endif |
| 148 | -#if CONFIG_ACTUX1_FLASH1X8 | |
| 146 | +#ifdef CONFIG_FLASH1X8 | |
| 149 | 147 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 150 | 148 | /* max number of sectors on one chip */ |
| 151 | 149 | # define CONFIG_SYS_MAX_FLASH_SECT 140 |
| ... | ... | @@ -156,6 +154,7 @@ |
| 156 | 154 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 157 | 155 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
| 158 | 156 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
| 157 | +#define CONFIG_BOARD_SIZE_LIMIT 262144 | |
| 159 | 158 | |
| 160 | 159 | /* Use common CFI driver */ |
| 161 | 160 | #define CONFIG_SYS_FLASH_CFI |
| 162 | 161 | |
| ... | ... | @@ -172,12 +171,16 @@ |
| 172 | 171 | #define CONFIG_NET_MULTI 1 |
| 173 | 172 | /* NPE0 PHY address */ |
| 174 | 173 | #define CONFIG_PHY_ADDR 0 |
| 174 | +/* NPE1 PHY address (HW Release E only) */ | |
| 175 | +#define CONFIG_PHY1_ADDR 1 | |
| 175 | 176 | /* MII PHY management */ |
| 176 | 177 | #define CONFIG_MII 1 |
| 177 | 178 | /* Number of ethernet rx buffers & descriptors */ |
| 178 | 179 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
| 179 | 180 | #define CONFIG_RESET_PHY_R 1 |
| 180 | 181 | |
| 182 | +#define CONFIG_HAS_ETH1 1 | |
| 183 | + | |
| 181 | 184 | #define CONFIG_CMD_DHCP |
| 182 | 185 | #define CONFIG_CMD_NET |
| 183 | 186 | #define CONFIG_CMD_MII |
| 184 | 187 | |
| 185 | 188 | |
| ... | ... | @@ -202,17 +205,19 @@ |
| 202 | 205 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) |
| 203 | 206 | #define CONFIG_SYS_USE_PPCENV 1 |
| 204 | 207 | |
| 205 | -#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 208 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 206 | 209 | "npe_ucode=50040000\0" \ |
| 207 | 210 | "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ |
| 208 | 211 | "kerneladdr=50050000\0" \ |
| 212 | + "kernelfile=actux1/uImage\0" \ | |
| 213 | + "rootfile=actux1/rootfs\0" \ | |
| 209 | 214 | "rootaddr=50170000\0" \ |
| 210 | 215 | "loadaddr=10000\0" \ |
| 211 | 216 | "updateboot_ser=mw.b 10000 ff 40000;" \ |
| 212 | 217 | " loady ${loadaddr};" \ |
| 213 | 218 | " run eraseboot writeboot\0" \ |
| 214 | 219 | "updateboot_net=mw.b 10000 ff 40000;" \ |
| 215 | - " tftp ${loadaddr} u-boot.bin;" \ | |
| 220 | + " tftp ${loadaddr} actux1/u-boot.bin;" \ | |
| 216 | 221 | " run eraseboot writeboot\0" \ |
| 217 | 222 | "eraseboot=protect off 50000000 50003fff;" \ |
| 218 | 223 | " protect off 50006000 5003ffff;" \ |
| ... | ... | @@ -220,8 +225,9 @@ |
| 220 | 225 | " erase 50006000 5003ffff\0" \ |
| 221 | 226 | "writeboot=cp.b 10000 50000000 4000;" \ |
| 222 | 227 | " cp.b 16000 50006000 3a000\0" \ |
| 223 | - "eraseenv=protect off 50004000 50005fff;" \ | |
| 224 | - " erase 50004000 50005fff\0" \ | |
| 228 | + "updateucode=loady;" \ | |
| 229 | + " era ${npe_ucode} +${filesize};" \ | |
| 230 | + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ | |
| 225 | 231 | "updateroot=tftp ${loadaddr} ${rootfile};" \ |
| 226 | 232 | " era ${rootaddr} +${filesize};" \ |
| 227 | 233 | " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ |
| 228 | 234 | |
| ... | ... | @@ -232,13 +238,17 @@ |
| 232 | 238 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ |
| 233 | 239 | "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ |
| 234 | 240 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ |
| 235 | - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate},${baudrate}\0" \" \ | |
| 241 | + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate},${baudrate}\0" \" \ | |
| 236 | 242 | "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ |
| 237 | 243 | "boot_flash=run flashargs addtty addeth;" \ |
| 238 | 244 | " bootm ${kerneladdr}\0" \ |
| 239 | 245 | "boot_net=run netargs addtty addeth;" \ |
| 240 | 246 | " tftpboot ${loadaddr} ${kernelfile};" \ |
| 241 | 247 | " bootm\0" |
| 248 | + | |
| 249 | +/* additions for new relocation code, must be added to all boards */ | |
| 250 | +#define CONFIG_SYS_INIT_SP_ADDR \ | |
| 251 | + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
| 242 | 252 | |
| 243 | 253 | #endif /* __CONFIG_H */ |