Commit 51b06dc40bce0768c77a23fcfc4a5ed5537aa2bd

Authored by Simon Glass
1 parent a1efd49ee2

dm: sound: exynos: Correct codec bus addresses

For snow the codec is at address 0x11 on the i2c bus, in 7-bit format.
The device tree and code are in 8-bit format (i.e. shifted left one bit).
Fix both. Fix pit in a similar way.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 4 changed files with 11 additions and 12 deletions Side-by-side Diff

arch/arm/dts/exynos5250-snow.dts
... ... @@ -214,8 +214,8 @@
214 214 };
215 215 };
216 216  
217   - soundcodec@22 {
218   - reg = <0x22>;
  217 + soundcodec@11 {
  218 + reg = <0x11>;
219 219 compatible = "maxim,max98095-codec";
220 220 };
221 221 };
arch/arm/dts/exynos5420-peach-pit.dts
... ... @@ -69,10 +69,10 @@
69 69  
70 70 i2c@12CD0000 { /* i2c7 */
71 71 clock-frequency = <100000>;
72   - soundcodec@20 {
73   - reg = <0x20>;
74   - compatible = "maxim,max98090-codec";
75   - };
  72 + soundcodec@10 {
  73 + reg = <0x10>;
  74 + compatible = "maxim,max98090-codec";
  75 + };
76 76  
77 77 edp-lvds-bridge@48 {
78 78 compatible = "parade,ps8625";
arch/arm/dts/exynos5800-peach-pi.dts
... ... @@ -81,10 +81,10 @@
81 81  
82 82 i2c@12CD0000 { /* i2c7 */
83 83 clock-frequency = <100000>;
84   - soundcodec@20 {
85   - reg = <0x20>;
86   - compatible = "maxim,max98090-codec";
87   - };
  84 + soundcodec@10 {
  85 + reg = <0x10>;
  86 + compatible = "maxim,max98090-codec";
  87 + };
88 88 };
89 89  
90 90 sound@3830000 {
drivers/sound/max98095.c
... ... @@ -569,8 +569,7 @@
569 569  
570 570 i2c_set_bus_num(pcodec_info.i2c_bus);
571 571  
572   - /* shift the device address by 1 for 7 bit addressing */
573   - max98095_info.i2c_addr = pcodec_info.i2c_dev_addr >> 1;
  572 + max98095_info.i2c_addr = pcodec_info.i2c_dev_addr;
574 573 ret = max98095_device_init(&max98095_info);
575 574 if (ret < 0) {
576 575 debug("%s: max98095 codec chip init failed\n", __func__);