Eric Lee / smarc-uboot

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Commit 5205a82eb31e12c275b6827dc782be2309ed3b2c

Authored by Lokesh Vutla
1 parent c165945d19
Exists in v2016.05-smarct4x and in 3 other branches v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc

ARM: OMAP4+: Fix DPLL programming sequence 

All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 1 changed file with 5 additions and 3 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap-common/clocks-common.c
Diff comments   View file @ 5205a82
... ... @@ -236,6 +236,8 @@
236 236 /* Dpll locked with ideal values for nominal opps. */
237 237 debug("\n %s Dpll already locked with ideal"
238 238 "nominal opp values", dpll);
  239 +
  240 + bypass_dpll(base);
239 241 goto setup_post_dividers;
240 242 }
241 243 }
242 244  
... ... @@ -251,12 +253,12 @@
251 253  
252 254 writel(temp, &dpll_regs->cm_clksel_dpll);
253 255  
  256 +setup_post_dividers:
  257 + setup_post_dividers(base, params);
  258 +
254 259 /* Lock */
255 260 if (lock)
256 261 do_lock_dpll(base);
257   -
258   -setup_post_dividers:
259   - setup_post_dividers(base, params);
260 262  
261 263 /* Wait till the DPLL locks */
262 264 if (lock)