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Commit 5274ae1eb950001cf37a6f8bc30d8f499c1d37d3

Authored by Ye Li
1 parent 18d62cf12e
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22851-2 mmc: fsl_esdhc: Update compatible string for imx8m 

To enable HS400 and UHS for imx8m platforms, update the driver data
to share with imx8x platforms and add relevant compatible string.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e0cc56f76027d014414b5aed6c26af444388093a)

Showing 1 changed file with 4 additions and 2 deletions Inline Diff

drivers/mmc/fsl_esdhc.c
Diff comments   View file @ 5274ae1
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc 3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Andy Fleming 4 * Andy Fleming
5 * 5 *
6 * Based vaguely on the pxa mmc code: 6 * Based vaguely on the pxa mmc code:
7 * (C) Copyright 2003 7 * (C) Copyright 2003
8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * Copyright 2019 NXP 9 * Copyright 2019 NXP
10 * 10 *
11 */ 11 */
12 12
13 #include <config.h> 13 #include <config.h>
14 #include <common.h> 14 #include <common.h>
15 #include <command.h> 15 #include <command.h>
16 #include <clk.h> 16 #include <clk.h>
17 #include <errno.h> 17 #include <errno.h>
18 #include <hwconfig.h> 18 #include <hwconfig.h>
19 #include <mmc.h> 19 #include <mmc.h>
20 #include <part.h> 20 #include <part.h>
21 #include <power/regulator.h> 21 #include <power/regulator.h>
22 #include <malloc.h> 22 #include <malloc.h>
23 #include <fsl_esdhc.h> 23 #include <fsl_esdhc.h>
24 #include <fdt_support.h> 24 #include <fdt_support.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <dm.h> 26 #include <dm.h>
27 #include <asm-generic/gpio.h> 27 #include <asm-generic/gpio.h>
28 #include <dm/pinctrl.h> 28 #include <dm/pinctrl.h>
29 #include <asm/arch/sys_proto.h> 29 #include <asm/arch/sys_proto.h>
30 30
31 DECLARE_GLOBAL_DATA_PTR; 31 DECLARE_GLOBAL_DATA_PTR;
32 32
33 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ 33 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
34 IRQSTATEN_CINT | \ 34 IRQSTATEN_CINT | \
35 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ 35 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
36 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ 36 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
37 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ 37 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
38 IRQSTATEN_DINT) 38 IRQSTATEN_DINT)
39 #define MAX_TUNING_LOOP 40 39 #define MAX_TUNING_LOOP 40
40 40
41 struct fsl_esdhc { 41 struct fsl_esdhc {
42 uint dsaddr; /* SDMA system address register */ 42 uint dsaddr; /* SDMA system address register */
43 uint blkattr; /* Block attributes register */ 43 uint blkattr; /* Block attributes register */
44 uint cmdarg; /* Command argument register */ 44 uint cmdarg; /* Command argument register */
45 uint xfertyp; /* Transfer type register */ 45 uint xfertyp; /* Transfer type register */
46 uint cmdrsp0; /* Command response 0 register */ 46 uint cmdrsp0; /* Command response 0 register */
47 uint cmdrsp1; /* Command response 1 register */ 47 uint cmdrsp1; /* Command response 1 register */
48 uint cmdrsp2; /* Command response 2 register */ 48 uint cmdrsp2; /* Command response 2 register */
49 uint cmdrsp3; /* Command response 3 register */ 49 uint cmdrsp3; /* Command response 3 register */
50 uint datport; /* Buffer data port register */ 50 uint datport; /* Buffer data port register */
51 uint prsstat; /* Present state register */ 51 uint prsstat; /* Present state register */
52 uint proctl; /* Protocol control register */ 52 uint proctl; /* Protocol control register */
53 uint sysctl; /* System Control Register */ 53 uint sysctl; /* System Control Register */
54 uint irqstat; /* Interrupt status register */ 54 uint irqstat; /* Interrupt status register */
55 uint irqstaten; /* Interrupt status enable register */ 55 uint irqstaten; /* Interrupt status enable register */
56 uint irqsigen; /* Interrupt signal enable register */ 56 uint irqsigen; /* Interrupt signal enable register */
57 uint autoc12err; /* Auto CMD error status register */ 57 uint autoc12err; /* Auto CMD error status register */
58 uint hostcapblt; /* Host controller capabilities register */ 58 uint hostcapblt; /* Host controller capabilities register */
59 uint wml; /* Watermark level register */ 59 uint wml; /* Watermark level register */
60 uint mixctrl; /* For USDHC */ 60 uint mixctrl; /* For USDHC */
61 char reserved1[4]; /* reserved */ 61 char reserved1[4]; /* reserved */
62 uint fevt; /* Force event register */ 62 uint fevt; /* Force event register */
63 uint admaes; /* ADMA error status register */ 63 uint admaes; /* ADMA error status register */
64 uint adsaddr; /* ADMA system address register */ 64 uint adsaddr; /* ADMA system address register */
65 char reserved2[4]; 65 char reserved2[4];
66 uint dllctrl; 66 uint dllctrl;
67 uint dllstat; 67 uint dllstat;
68 uint clktunectrlstatus; 68 uint clktunectrlstatus;
69 char reserved3[4]; 69 char reserved3[4];
70 uint strobe_dllctrl; 70 uint strobe_dllctrl;
71 uint strobe_dllstat; 71 uint strobe_dllstat;
72 char reserved4[72]; 72 char reserved4[72];
73 uint vendorspec; 73 uint vendorspec;
74 uint mmcboot; 74 uint mmcboot;
75 uint vendorspec2; 75 uint vendorspec2;
76 uint tuning_ctrl; /* on i.MX6/7/8 */ 76 uint tuning_ctrl; /* on i.MX6/7/8 */
77 char reserved5[44]; 77 char reserved5[44];
78 uint hostver; /* Host controller version register */ 78 uint hostver; /* Host controller version register */
79 char reserved6[4]; /* reserved */ 79 char reserved6[4]; /* reserved */
80 uint dmaerraddr; /* DMA error address register */ 80 uint dmaerraddr; /* DMA error address register */
81 char reserved7[4]; /* reserved */ 81 char reserved7[4]; /* reserved */
82 uint dmaerrattr; /* DMA error attribute register */ 82 uint dmaerrattr; /* DMA error attribute register */
83 char reserved8[4]; /* reserved */ 83 char reserved8[4]; /* reserved */
84 uint hostcapblt2; /* Host controller capabilities register 2 */ 84 uint hostcapblt2; /* Host controller capabilities register 2 */
85 char reserved9[8]; /* reserved */ 85 char reserved9[8]; /* reserved */
86 uint tcr; /* Tuning control register */ 86 uint tcr; /* Tuning control register */
87 char reserved10[28]; /* reserved */ 87 char reserved10[28]; /* reserved */
88 uint sddirctl; /* SD direction control register */ 88 uint sddirctl; /* SD direction control register */
89 char reserved11[712];/* reserved */ 89 char reserved11[712];/* reserved */
90 uint scr; /* eSDHC control register */ 90 uint scr; /* eSDHC control register */
91 }; 91 };
92 92
93 struct fsl_esdhc_plat { 93 struct fsl_esdhc_plat {
94 struct mmc_config cfg; 94 struct mmc_config cfg;
95 struct mmc mmc; 95 struct mmc mmc;
96 }; 96 };
97 97
98 struct esdhc_soc_data { 98 struct esdhc_soc_data {
99 u32 flags; 99 u32 flags;
100 u32 caps; 100 u32 caps;
101 }; 101 };
102 102
103 /** 103 /**
104 * struct fsl_esdhc_priv 104 * struct fsl_esdhc_priv
105 * 105 *
106 * @esdhc_regs: registers of the sdhc controller 106 * @esdhc_regs: registers of the sdhc controller
107 * @sdhc_clk: Current clk of the sdhc controller 107 * @sdhc_clk: Current clk of the sdhc controller
108 * @bus_width: bus width, 1bit, 4bit or 8bit 108 * @bus_width: bus width, 1bit, 4bit or 8bit
109 * @cfg: mmc config 109 * @cfg: mmc config
110 * @mmc: mmc 110 * @mmc: mmc
111 * Following is used when Driver Model is enabled for MMC 111 * Following is used when Driver Model is enabled for MMC
112 * @dev: pointer for the device 112 * @dev: pointer for the device
113 * @non_removable: 0: removable; 1: non-removable 113 * @non_removable: 0: removable; 1: non-removable
114 * @wp_enable: 1: enable checking wp; 0: no check 114 * @wp_enable: 1: enable checking wp; 0: no check
115 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V 115 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
116 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h 116 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
117 * @caps: controller capabilities 117 * @caps: controller capabilities
118 * @tuning_step: tuning step setting in tuning_ctrl register 118 * @tuning_step: tuning step setting in tuning_ctrl register
119 * @start_tuning_tap: the start point for tuning in tuning_ctrl register 119 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
120 * @strobe_dll_delay_target: settings in strobe_dllctrl 120 * @strobe_dll_delay_target: settings in strobe_dllctrl
121 * @signal_voltage: indicating the current voltage 121 * @signal_voltage: indicating the current voltage
122 * @cd_gpio: gpio for card detection 122 * @cd_gpio: gpio for card detection
123 * @wp_gpio: gpio for write protection 123 * @wp_gpio: gpio for write protection
124 */ 124 */
125 struct fsl_esdhc_priv { 125 struct fsl_esdhc_priv {
126 struct fsl_esdhc *esdhc_regs; 126 struct fsl_esdhc *esdhc_regs;
127 unsigned int sdhc_clk; 127 unsigned int sdhc_clk;
128 struct clk per_clk; 128 struct clk per_clk;
129 unsigned int clock; 129 unsigned int clock;
130 unsigned int mode; 130 unsigned int mode;
131 unsigned int bus_width; 131 unsigned int bus_width;
132 #if !CONFIG_IS_ENABLED(BLK) 132 #if !CONFIG_IS_ENABLED(BLK)
133 struct mmc *mmc; 133 struct mmc *mmc;
134 #endif 134 #endif
135 struct udevice *dev; 135 struct udevice *dev;
136 int non_removable; 136 int non_removable;
137 int wp_enable; 137 int wp_enable;
138 int vs18_enable; 138 int vs18_enable;
139 u32 flags; 139 u32 flags;
140 u32 caps; 140 u32 caps;
141 u32 tuning_step; 141 u32 tuning_step;
142 u32 tuning_start_tap; 142 u32 tuning_start_tap;
143 u32 strobe_dll_delay_target; 143 u32 strobe_dll_delay_target;
144 u32 signal_voltage; 144 u32 signal_voltage;
145 #if IS_ENABLED(CONFIG_DM_REGULATOR) 145 #if IS_ENABLED(CONFIG_DM_REGULATOR)
146 struct udevice *vqmmc_dev; 146 struct udevice *vqmmc_dev;
147 struct udevice *vmmc_dev; 147 struct udevice *vmmc_dev;
148 #endif 148 #endif
149 #ifdef CONFIG_DM_GPIO 149 #ifdef CONFIG_DM_GPIO
150 struct gpio_desc cd_gpio; 150 struct gpio_desc cd_gpio;
151 struct gpio_desc wp_gpio; 151 struct gpio_desc wp_gpio;
152 #endif 152 #endif
153 }; 153 };
154 154
155 /* Return the XFERTYP flags for a given command and data packet */ 155 /* Return the XFERTYP flags for a given command and data packet */
156 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 156 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
157 { 157 {
158 uint xfertyp = 0; 158 uint xfertyp = 0;
159 159
160 if (data) { 160 if (data) {
161 xfertyp |= XFERTYP_DPSEL; 161 xfertyp |= XFERTYP_DPSEL;
162 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 162 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
163 xfertyp |= XFERTYP_DMAEN; 163 xfertyp |= XFERTYP_DMAEN;
164 #endif 164 #endif
165 if (data->blocks > 1) { 165 if (data->blocks > 1) {
166 xfertyp |= XFERTYP_MSBSEL; 166 xfertyp |= XFERTYP_MSBSEL;
167 xfertyp |= XFERTYP_BCEN; 167 xfertyp |= XFERTYP_BCEN;
168 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 168 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
169 xfertyp |= XFERTYP_AC12EN; 169 xfertyp |= XFERTYP_AC12EN;
170 #endif 170 #endif
171 } 171 }
172 172
173 if (data->flags & MMC_DATA_READ) 173 if (data->flags & MMC_DATA_READ)
174 xfertyp |= XFERTYP_DTDSEL; 174 xfertyp |= XFERTYP_DTDSEL;
175 } 175 }
176 176
177 if (cmd->resp_type & MMC_RSP_CRC) 177 if (cmd->resp_type & MMC_RSP_CRC)
178 xfertyp |= XFERTYP_CCCEN; 178 xfertyp |= XFERTYP_CCCEN;
179 if (cmd->resp_type & MMC_RSP_OPCODE) 179 if (cmd->resp_type & MMC_RSP_OPCODE)
180 xfertyp |= XFERTYP_CICEN; 180 xfertyp |= XFERTYP_CICEN;
181 if (cmd->resp_type & MMC_RSP_136) 181 if (cmd->resp_type & MMC_RSP_136)
182 xfertyp |= XFERTYP_RSPTYP_136; 182 xfertyp |= XFERTYP_RSPTYP_136;
183 else if (cmd->resp_type & MMC_RSP_BUSY) 183 else if (cmd->resp_type & MMC_RSP_BUSY)
184 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 184 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
185 else if (cmd->resp_type & MMC_RSP_PRESENT) 185 else if (cmd->resp_type & MMC_RSP_PRESENT)
186 xfertyp |= XFERTYP_RSPTYP_48; 186 xfertyp |= XFERTYP_RSPTYP_48;
187 187
188 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 188 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
189 xfertyp |= XFERTYP_CMDTYP_ABORT; 189 xfertyp |= XFERTYP_CMDTYP_ABORT;
190 190
191 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 191 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
192 } 192 }
193 193
194 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 194 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
195 /* 195 /*
196 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. 196 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
197 */ 197 */
198 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, 198 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
199 struct mmc_data *data) 199 struct mmc_data *data)
200 { 200 {
201 struct fsl_esdhc *regs = priv->esdhc_regs; 201 struct fsl_esdhc *regs = priv->esdhc_regs;
202 uint blocks; 202 uint blocks;
203 char *buffer; 203 char *buffer;
204 uint databuf; 204 uint databuf;
205 uint size; 205 uint size;
206 uint irqstat; 206 uint irqstat;
207 ulong start; 207 ulong start;
208 208
209 if (data->flags & MMC_DATA_READ) { 209 if (data->flags & MMC_DATA_READ) {
210 blocks = data->blocks; 210 blocks = data->blocks;
211 buffer = data->dest; 211 buffer = data->dest;
212 while (blocks) { 212 while (blocks) {
213 start = get_timer(0); 213 start = get_timer(0);
214 size = data->blocksize; 214 size = data->blocksize;
215 irqstat = esdhc_read32(&regs->irqstat); 215 irqstat = esdhc_read32(&regs->irqstat);
216 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) { 216 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
217 if (get_timer(start) > PIO_TIMEOUT) { 217 if (get_timer(start) > PIO_TIMEOUT) {
218 printf("\nData Read Failed in PIO Mode."); 218 printf("\nData Read Failed in PIO Mode.");
219 return; 219 return;
220 } 220 }
221 } 221 }
222 while (size && (!(irqstat & IRQSTAT_TC))) { 222 while (size && (!(irqstat & IRQSTAT_TC))) {
223 udelay(100); /* Wait before last byte transfer complete */ 223 udelay(100); /* Wait before last byte transfer complete */
224 irqstat = esdhc_read32(&regs->irqstat); 224 irqstat = esdhc_read32(&regs->irqstat);
225 databuf = in_le32(&regs->datport); 225 databuf = in_le32(&regs->datport);
226 *((uint *)buffer) = databuf; 226 *((uint *)buffer) = databuf;
227 buffer += 4; 227 buffer += 4;
228 size -= 4; 228 size -= 4;
229 } 229 }
230 blocks--; 230 blocks--;
231 } 231 }
232 } else { 232 } else {
233 blocks = data->blocks; 233 blocks = data->blocks;
234 buffer = (char *)data->src; 234 buffer = (char *)data->src;
235 while (blocks) { 235 while (blocks) {
236 start = get_timer(0); 236 start = get_timer(0);
237 size = data->blocksize; 237 size = data->blocksize;
238 irqstat = esdhc_read32(&regs->irqstat); 238 irqstat = esdhc_read32(&regs->irqstat);
239 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) { 239 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
240 if (get_timer(start) > PIO_TIMEOUT) { 240 if (get_timer(start) > PIO_TIMEOUT) {
241 printf("\nData Write Failed in PIO Mode."); 241 printf("\nData Write Failed in PIO Mode.");
242 return; 242 return;
243 } 243 }
244 } 244 }
245 while (size && (!(irqstat & IRQSTAT_TC))) { 245 while (size && (!(irqstat & IRQSTAT_TC))) {
246 udelay(100); /* Wait before last byte transfer complete */ 246 udelay(100); /* Wait before last byte transfer complete */
247 databuf = *((uint *)buffer); 247 databuf = *((uint *)buffer);
248 buffer += 4; 248 buffer += 4;
249 size -= 4; 249 size -= 4;
250 irqstat = esdhc_read32(&regs->irqstat); 250 irqstat = esdhc_read32(&regs->irqstat);
251 out_le32(&regs->datport, databuf); 251 out_le32(&regs->datport, databuf);
252 } 252 }
253 blocks--; 253 blocks--;
254 } 254 }
255 } 255 }
256 } 256 }
257 #endif 257 #endif
258 258
259 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, 259 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
260 struct mmc_data *data) 260 struct mmc_data *data)
261 { 261 {
262 int timeout; 262 int timeout;
263 struct fsl_esdhc *regs = priv->esdhc_regs; 263 struct fsl_esdhc *regs = priv->esdhc_regs;
264 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 264 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
265 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 265 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
266 dma_addr_t addr; 266 dma_addr_t addr;
267 #endif 267 #endif
268 uint wml_value; 268 uint wml_value;
269 269
270 wml_value = data->blocksize/4; 270 wml_value = data->blocksize/4;
271 271
272 if (data->flags & MMC_DATA_READ) { 272 if (data->flags & MMC_DATA_READ) {
273 if (wml_value > WML_RD_WML_MAX) 273 if (wml_value > WML_RD_WML_MAX)
274 wml_value = WML_RD_WML_MAX_VAL; 274 wml_value = WML_RD_WML_MAX_VAL;
275 275
276 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value); 276 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
277 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 277 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
278 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 278 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
279 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 279 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
280 addr = virt_to_phys((void *)(data->dest)); 280 addr = virt_to_phys((void *)(data->dest));
281 if (upper_32_bits(addr)) 281 if (upper_32_bits(addr))
282 printf("Error found for upper 32 bits\n"); 282 printf("Error found for upper 32 bits\n");
283 else 283 else
284 esdhc_write32(&regs->dsaddr, lower_32_bits(addr)); 284 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
285 #else 285 #else
286 esdhc_write32(&regs->dsaddr, (u32)data->dest); 286 esdhc_write32(&regs->dsaddr, (u32)data->dest);
287 #endif 287 #endif
288 #endif 288 #endif
289 } else { 289 } else {
290 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 290 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
291 flush_dcache_range((ulong)data->src, 291 flush_dcache_range((ulong)data->src,
292 (ulong)data->src+data->blocks 292 (ulong)data->src+data->blocks
293 *data->blocksize); 293 *data->blocksize);
294 #endif 294 #endif
295 if (wml_value > WML_WR_WML_MAX) 295 if (wml_value > WML_WR_WML_MAX)
296 wml_value = WML_WR_WML_MAX_VAL; 296 wml_value = WML_WR_WML_MAX_VAL;
297 if (priv->wp_enable) { 297 if (priv->wp_enable) {
298 if ((esdhc_read32(&regs->prsstat) & 298 if ((esdhc_read32(&regs->prsstat) &
299 PRSSTAT_WPSPL) == 0) { 299 PRSSTAT_WPSPL) == 0) {
300 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 300 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
301 return -ETIMEDOUT; 301 return -ETIMEDOUT;
302 } 302 }
303 } else { 303 } else {
304 #ifdef CONFIG_DM_GPIO 304 #ifdef CONFIG_DM_GPIO
305 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) { 305 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
306 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 306 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
307 return -ETIMEDOUT; 307 return -ETIMEDOUT;
308 } 308 }
309 #endif 309 #endif
310 } 310 }
311 311
312 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK, 312 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
313 wml_value << 16); 313 wml_value << 16);
314 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO 314 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
315 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 315 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
316 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 316 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
317 addr = virt_to_phys((void *)(data->src)); 317 addr = virt_to_phys((void *)(data->src));
318 if (upper_32_bits(addr)) 318 if (upper_32_bits(addr))
319 printf("Error found for upper 32 bits\n"); 319 printf("Error found for upper 32 bits\n");
320 else 320 else
321 esdhc_write32(&regs->dsaddr, lower_32_bits(addr)); 321 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
322 #else 322 #else
323 esdhc_write32(&regs->dsaddr, (u32)data->src); 323 esdhc_write32(&regs->dsaddr, (u32)data->src);
324 #endif 324 #endif
325 #endif 325 #endif
326 } 326 }
327 327
328 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize); 328 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
329 329
330 /* Calculate the timeout period for data transactions */ 330 /* Calculate the timeout period for data transactions */
331 /* 331 /*
332 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles 332 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
333 * 2)Timeout period should be minimum 0.250sec as per SD Card spec 333 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
334 * So, Number of SD Clock cycles for 0.25sec should be minimum 334 * So, Number of SD Clock cycles for 0.25sec should be minimum
335 * (SD Clock/sec * 0.25 sec) SD Clock cycles 335 * (SD Clock/sec * 0.25 sec) SD Clock cycles
336 * = (mmc->clock * 1/4) SD Clock cycles 336 * = (mmc->clock * 1/4) SD Clock cycles
337 * As 1) >= 2) 337 * As 1) >= 2)
338 * => (2^(timeout+13)) >= mmc->clock * 1/4 338 * => (2^(timeout+13)) >= mmc->clock * 1/4
339 * Taking log2 both the sides 339 * Taking log2 both the sides
340 * => timeout + 13 >= log2(mmc->clock/4) 340 * => timeout + 13 >= log2(mmc->clock/4)
341 * Rounding up to next power of 2 341 * Rounding up to next power of 2
342 * => timeout + 13 = log2(mmc->clock/4) + 1 342 * => timeout + 13 = log2(mmc->clock/4) + 1
343 * => timeout + 13 = fls(mmc->clock/4) 343 * => timeout + 13 = fls(mmc->clock/4)
344 * 344 *
345 * However, the MMC spec "It is strongly recommended for hosts to 345 * However, the MMC spec "It is strongly recommended for hosts to
346 * implement more than 500ms timeout value even if the card 346 * implement more than 500ms timeout value even if the card
347 * indicates the 250ms maximum busy length." Even the previous 347 * indicates the 250ms maximum busy length." Even the previous
348 * value of 300ms is known to be insufficient for some cards. 348 * value of 300ms is known to be insufficient for some cards.
349 * So, we use 349 * So, we use
350 * => timeout + 13 = fls(mmc->clock/2) 350 * => timeout + 13 = fls(mmc->clock/2)
351 */ 351 */
352 timeout = fls(mmc->clock/2); 352 timeout = fls(mmc->clock/2);
353 timeout -= 13; 353 timeout -= 13;
354 354
355 if (timeout > 14) 355 if (timeout > 14)
356 timeout = 14; 356 timeout = 14;
357 357
358 if (timeout < 0) 358 if (timeout < 0)
359 timeout = 0; 359 timeout = 0;
360 360
361 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 361 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
362 if ((timeout == 4) || (timeout == 8) || (timeout == 12)) 362 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
363 timeout++; 363 timeout++;
364 #endif 364 #endif
365 365
366 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 366 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
367 timeout = 0xE; 367 timeout = 0xE;
368 #endif 368 #endif
369 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 369 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
370 370
371 return 0; 371 return 0;
372 } 372 }
373 373
374 static void check_and_invalidate_dcache_range 374 static void check_and_invalidate_dcache_range
375 (struct mmc_cmd *cmd, 375 (struct mmc_cmd *cmd,
376 struct mmc_data *data) { 376 struct mmc_data *data) {
377 unsigned start = 0; 377 unsigned start = 0;
378 unsigned end = 0; 378 unsigned end = 0;
379 unsigned size = roundup(ARCH_DMA_MINALIGN, 379 unsigned size = roundup(ARCH_DMA_MINALIGN,
380 data->blocks*data->blocksize); 380 data->blocks*data->blocksize);
381 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ 381 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
382 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) 382 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
383 dma_addr_t addr; 383 dma_addr_t addr;
384 384
385 addr = virt_to_phys((void *)(data->dest)); 385 addr = virt_to_phys((void *)(data->dest));
386 if (upper_32_bits(addr)) 386 if (upper_32_bits(addr))
387 printf("Error found for upper 32 bits\n"); 387 printf("Error found for upper 32 bits\n");
388 else 388 else
389 start = lower_32_bits(addr); 389 start = lower_32_bits(addr);
390 #else 390 #else
391 start = (unsigned)data->dest; 391 start = (unsigned)data->dest;
392 #endif 392 #endif
393 end = start + size; 393 end = start + size;
394 invalidate_dcache_range(start, end); 394 invalidate_dcache_range(start, end);
395 } 395 }
396 396
397 #ifdef CONFIG_MCF5441x 397 #ifdef CONFIG_MCF5441x
398 /* 398 /*
399 * Swaps 32-bit words to little-endian byte order. 399 * Swaps 32-bit words to little-endian byte order.
400 */ 400 */
401 static inline void sd_swap_dma_buff(struct mmc_data *data) 401 static inline void sd_swap_dma_buff(struct mmc_data *data)
402 { 402 {
403 int i, size = data->blocksize >> 2; 403 int i, size = data->blocksize >> 2;
404 u32 *buffer = (u32 *)data->dest; 404 u32 *buffer = (u32 *)data->dest;
405 u32 sw; 405 u32 sw;
406 406
407 while (data->blocks--) { 407 while (data->blocks--) {
408 for (i = 0; i < size; i++) { 408 for (i = 0; i < size; i++) {
409 sw = __sw32(*buffer); 409 sw = __sw32(*buffer);
410 *buffer++ = sw; 410 *buffer++ = sw;
411 } 411 }
412 } 412 }
413 } 413 }
414 #endif 414 #endif
415 415
416 /* 416 /*
417 * Sends a command out on the bus. Takes the mmc pointer, 417 * Sends a command out on the bus. Takes the mmc pointer,
418 * a command pointer, and an optional data pointer. 418 * a command pointer, and an optional data pointer.
419 */ 419 */
420 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, 420 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
421 struct mmc_cmd *cmd, struct mmc_data *data) 421 struct mmc_cmd *cmd, struct mmc_data *data)
422 { 422 {
423 int err = 0; 423 int err = 0;
424 uint xfertyp; 424 uint xfertyp;
425 uint irqstat; 425 uint irqstat;
426 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; 426 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
427 struct fsl_esdhc *regs = priv->esdhc_regs; 427 struct fsl_esdhc *regs = priv->esdhc_regs;
428 unsigned long start; 428 unsigned long start;
429 429
430 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 430 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
431 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 431 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
432 return 0; 432 return 0;
433 #endif 433 #endif
434 434
435 esdhc_write32(&regs->irqstat, -1); 435 esdhc_write32(&regs->irqstat, -1);
436 436
437 sync(); 437 sync();
438 438
439 /* Wait for the bus to be idle */ 439 /* Wait for the bus to be idle */
440 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) || 440 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
441 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB)) 441 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
442 ; 442 ;
443 443
444 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA) 444 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
445 ; 445 ;
446 446
447 /* Wait at least 8 SD clock cycles before the next command */ 447 /* Wait at least 8 SD clock cycles before the next command */
448 /* 448 /*
449 * Note: This is way more than 8 cycles, but 1ms seems to 449 * Note: This is way more than 8 cycles, but 1ms seems to
450 * resolve timing issues with some cards 450 * resolve timing issues with some cards
451 */ 451 */
452 udelay(1000); 452 udelay(1000);
453 453
454 /* Set up for a data transfer if we have one */ 454 /* Set up for a data transfer if we have one */
455 if (data) { 455 if (data) {
456 err = esdhc_setup_data(priv, mmc, data); 456 err = esdhc_setup_data(priv, mmc, data);
457 if(err) 457 if(err)
458 return err; 458 return err;
459 459
460 if (data->flags & MMC_DATA_READ) 460 if (data->flags & MMC_DATA_READ)
461 check_and_invalidate_dcache_range(cmd, data); 461 check_and_invalidate_dcache_range(cmd, data);
462 } 462 }
463 463
464 /* Figure out the transfer arguments */ 464 /* Figure out the transfer arguments */
465 xfertyp = esdhc_xfertyp(cmd, data); 465 xfertyp = esdhc_xfertyp(cmd, data);
466 466
467 /* Mask all irqs */ 467 /* Mask all irqs */
468 esdhc_write32(&regs->irqsigen, 0); 468 esdhc_write32(&regs->irqsigen, 0);
469 469
470 /* Send the command */ 470 /* Send the command */
471 esdhc_write32(&regs->cmdarg, cmd->cmdarg); 471 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
472 #if defined(CONFIG_FSL_USDHC) 472 #if defined(CONFIG_FSL_USDHC)
473 esdhc_write32(&regs->mixctrl, 473 esdhc_write32(&regs->mixctrl,
474 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) 474 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
475 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); 475 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
476 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000); 476 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
477 #else 477 #else
478 esdhc_write32(&regs->xfertyp, xfertyp); 478 esdhc_write32(&regs->xfertyp, xfertyp);
479 #endif 479 #endif
480 480
481 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 481 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
482 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) 482 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
483 flags = IRQSTAT_BRR; 483 flags = IRQSTAT_BRR;
484 484
485 /* Wait for the command to complete */ 485 /* Wait for the command to complete */
486 start = get_timer(0); 486 start = get_timer(0);
487 while (!(esdhc_read32(&regs->irqstat) & flags)) { 487 while (!(esdhc_read32(&regs->irqstat) & flags)) {
488 if (get_timer(start) > 1000) { 488 if (get_timer(start) > 1000) {
489 err = -ETIMEDOUT; 489 err = -ETIMEDOUT;
490 goto out; 490 goto out;
491 } 491 }
492 } 492 }
493 493
494 irqstat = esdhc_read32(&regs->irqstat); 494 irqstat = esdhc_read32(&regs->irqstat);
495 495
496 if (irqstat & CMD_ERR) { 496 if (irqstat & CMD_ERR) {
497 err = -ECOMM; 497 err = -ECOMM;
498 goto out; 498 goto out;
499 } 499 }
500 500
501 if (irqstat & IRQSTAT_CTOE) { 501 if (irqstat & IRQSTAT_CTOE) {
502 err = -ETIMEDOUT; 502 err = -ETIMEDOUT;
503 goto out; 503 goto out;
504 } 504 }
505 505
506 /* Switch voltage to 1.8V if CMD11 succeeded */ 506 /* Switch voltage to 1.8V if CMD11 succeeded */
507 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { 507 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
508 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); 508 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
509 509
510 printf("Run CMD11 1.8V switch\n"); 510 printf("Run CMD11 1.8V switch\n");
511 /* Sleep for 5 ms - max time for card to switch to 1.8V */ 511 /* Sleep for 5 ms - max time for card to switch to 1.8V */
512 udelay(5000); 512 udelay(5000);
513 } 513 }
514 514
515 /* Workaround for ESDHC errata ENGcm03648 */ 515 /* Workaround for ESDHC errata ENGcm03648 */
516 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { 516 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
517 int timeout = 50000; 517 int timeout = 50000;
518 518
519 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */ 519 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
520 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) & 520 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
521 PRSSTAT_DAT0)) { 521 PRSSTAT_DAT0)) {
522 udelay(100); 522 udelay(100);
523 timeout--; 523 timeout--;
524 } 524 }
525 525
526 if (timeout <= 0) { 526 if (timeout <= 0) {
527 printf("Timeout waiting for DAT0 to go high!\n"); 527 printf("Timeout waiting for DAT0 to go high!\n");
528 err = -ETIMEDOUT; 528 err = -ETIMEDOUT;
529 goto out; 529 goto out;
530 } 530 }
531 } 531 }
532 532
533 /* Copy the response to the response buffer */ 533 /* Copy the response to the response buffer */
534 if (cmd->resp_type & MMC_RSP_136) { 534 if (cmd->resp_type & MMC_RSP_136) {
535 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 535 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
536 536
537 cmdrsp3 = esdhc_read32(&regs->cmdrsp3); 537 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
538 cmdrsp2 = esdhc_read32(&regs->cmdrsp2); 538 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
539 cmdrsp1 = esdhc_read32(&regs->cmdrsp1); 539 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
540 cmdrsp0 = esdhc_read32(&regs->cmdrsp0); 540 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
541 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 541 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
542 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 542 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
543 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 543 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
544 cmd->response[3] = (cmdrsp0 << 8); 544 cmd->response[3] = (cmdrsp0 << 8);
545 } else 545 } else
546 cmd->response[0] = esdhc_read32(&regs->cmdrsp0); 546 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
547 547
548 /* Wait until all of the blocks are transferred */ 548 /* Wait until all of the blocks are transferred */
549 if (data) { 549 if (data) {
550 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO 550 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
551 esdhc_pio_read_write(priv, data); 551 esdhc_pio_read_write(priv, data);
552 #else 552 #else
553 flags = DATA_COMPLETE; 553 flags = DATA_COMPLETE;
554 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || 554 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
555 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) { 555 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
556 flags = IRQSTAT_BRR; 556 flags = IRQSTAT_BRR;
557 } 557 }
558 558
559 do { 559 do {
560 irqstat = esdhc_read32(&regs->irqstat); 560 irqstat = esdhc_read32(&regs->irqstat);
561 561
562 if (irqstat & IRQSTAT_DTOE) { 562 if (irqstat & IRQSTAT_DTOE) {
563 err = -ETIMEDOUT; 563 err = -ETIMEDOUT;
564 goto out; 564 goto out;
565 } 565 }
566 566
567 if (irqstat & DATA_ERR) { 567 if (irqstat & DATA_ERR) {
568 err = -ECOMM; 568 err = -ECOMM;
569 goto out; 569 goto out;
570 } 570 }
571 } while ((irqstat & flags) != flags); 571 } while ((irqstat & flags) != flags);
572 572
573 /* 573 /*
574 * Need invalidate the dcache here again to avoid any 574 * Need invalidate the dcache here again to avoid any
575 * cache-fill during the DMA operations such as the 575 * cache-fill during the DMA operations such as the
576 * speculative pre-fetching etc. 576 * speculative pre-fetching etc.
577 */ 577 */
578 if (data->flags & MMC_DATA_READ) { 578 if (data->flags & MMC_DATA_READ) {
579 check_and_invalidate_dcache_range(cmd, data); 579 check_and_invalidate_dcache_range(cmd, data);
580 #ifdef CONFIG_MCF5441x 580 #ifdef CONFIG_MCF5441x
581 sd_swap_dma_buff(data); 581 sd_swap_dma_buff(data);
582 #endif 582 #endif
583 } 583 }
584 #endif 584 #endif
585 } 585 }
586 586
587 out: 587 out:
588 /* Reset CMD and DATA portions on error */ 588 /* Reset CMD and DATA portions on error */
589 if (err) { 589 if (err) {
590 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | 590 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
591 SYSCTL_RSTC); 591 SYSCTL_RSTC);
592 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) 592 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
593 ; 593 ;
594 594
595 if (data) { 595 if (data) {
596 esdhc_write32(&regs->sysctl, 596 esdhc_write32(&regs->sysctl,
597 esdhc_read32(&regs->sysctl) | 597 esdhc_read32(&regs->sysctl) |
598 SYSCTL_RSTD); 598 SYSCTL_RSTD);
599 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) 599 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
600 ; 600 ;
601 } 601 }
602 602
603 /* If this was CMD11, then notify that power cycle is needed */ 603 /* If this was CMD11, then notify that power cycle is needed */
604 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) 604 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
605 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); 605 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
606 } 606 }
607 607
608 esdhc_write32(&regs->irqstat, -1); 608 esdhc_write32(&regs->irqstat, -1);
609 609
610 return err; 610 return err;
611 } 611 }
612 612
613 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) 613 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
614 { 614 {
615 struct fsl_esdhc *regs = priv->esdhc_regs; 615 struct fsl_esdhc *regs = priv->esdhc_regs;
616 int div = 1; 616 int div = 1;
617 #ifdef ARCH_MXC 617 #ifdef ARCH_MXC
618 #ifdef CONFIG_MX53 618 #ifdef CONFIG_MX53
619 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 619 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
620 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; 620 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
621 #else 621 #else
622 int pre_div = 1; 622 int pre_div = 1;
623 #endif 623 #endif
624 #else 624 #else
625 int pre_div = 2; 625 int pre_div = 2;
626 #endif 626 #endif
627 int sdhc_clk = priv->sdhc_clk; 627 int sdhc_clk = priv->sdhc_clk;
628 uint clk; 628 uint clk;
629 629
630 /* 630 /*
631 * For ddr mode, usdhc need to enable DDR mode first, after select 631 * For ddr mode, usdhc need to enable DDR mode first, after select
632 * this DDR mode, usdhc will automatically divide the usdhc clock 632 * this DDR mode, usdhc will automatically divide the usdhc clock
633 */ 633 */
634 if (mmc->ddr_mode) { 634 if (mmc->ddr_mode) {
635 writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl); 635 writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl);
636 sdhc_clk >>= 1; 636 sdhc_clk >>= 1;
637 } 637 }
638 638
639 if (sdhc_clk / 16 > clock) { 639 if (sdhc_clk / 16 > clock) {
640 for (; pre_div < 256; pre_div *= 2) 640 for (; pre_div < 256; pre_div *= 2)
641 if ((sdhc_clk / pre_div) <= (clock * 16)) 641 if ((sdhc_clk / pre_div) <= (clock * 16))
642 break; 642 break;
643 } 643 }
644 644
645 for (div = 1; div <= 16; div++) 645 for (div = 1; div <= 16; div++)
646 if ((sdhc_clk / (div * pre_div)) <= clock) 646 if ((sdhc_clk / (div * pre_div)) <= clock)
647 break; 647 break;
648 648
649 pre_div >>= 1; 649 pre_div >>= 1;
650 div -= 1; 650 div -= 1;
651 651
652 clk = (pre_div << 8) | (div << 4); 652 clk = (pre_div << 8) | (div << 4);
653 653
654 #ifdef CONFIG_FSL_USDHC 654 #ifdef CONFIG_FSL_USDHC
655 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); 655 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
656 #else 656 #else
657 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); 657 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
658 #endif 658 #endif
659 659
660 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); 660 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
661 661
662 udelay(10000); 662 udelay(10000);
663 663
664 #ifdef CONFIG_FSL_USDHC 664 #ifdef CONFIG_FSL_USDHC
665 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); 665 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
666 #else 666 #else
667 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 667 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
668 #endif 668 #endif
669 669
670 priv->clock = clock; 670 priv->clock = clock;
671 } 671 }
672 672
673 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 673 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
674 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) 674 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
675 { 675 {
676 struct fsl_esdhc *regs = priv->esdhc_regs; 676 struct fsl_esdhc *regs = priv->esdhc_regs;
677 u32 value; 677 u32 value;
678 u32 time_out; 678 u32 time_out;
679 679
680 value = esdhc_read32(&regs->sysctl); 680 value = esdhc_read32(&regs->sysctl);
681 681
682 if (enable) 682 if (enable)
683 value |= SYSCTL_CKEN; 683 value |= SYSCTL_CKEN;
684 else 684 else
685 value &= ~SYSCTL_CKEN; 685 value &= ~SYSCTL_CKEN;
686 686
687 esdhc_write32(&regs->sysctl, value); 687 esdhc_write32(&regs->sysctl, value);
688 688
689 time_out = 20; 689 time_out = 20;
690 value = PRSSTAT_SDSTB; 690 value = PRSSTAT_SDSTB;
691 while (!(esdhc_read32(&regs->prsstat) & value)) { 691 while (!(esdhc_read32(&regs->prsstat) & value)) {
692 if (time_out == 0) { 692 if (time_out == 0) {
693 printf("fsl_esdhc: Internal clock never stabilised.\n"); 693 printf("fsl_esdhc: Internal clock never stabilised.\n");
694 break; 694 break;
695 } 695 }
696 time_out--; 696 time_out--;
697 mdelay(1); 697 mdelay(1);
698 } 698 }
699 } 699 }
700 #endif 700 #endif
701 701
702 #ifdef MMC_SUPPORTS_TUNING 702 #ifdef MMC_SUPPORTS_TUNING
703 static int esdhc_change_pinstate(struct udevice *dev) 703 static int esdhc_change_pinstate(struct udevice *dev)
704 { 704 {
705 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 705 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
706 int ret; 706 int ret;
707 707
708 switch (priv->mode) { 708 switch (priv->mode) {
709 case UHS_SDR50: 709 case UHS_SDR50:
710 case UHS_DDR50: 710 case UHS_DDR50:
711 ret = pinctrl_select_state(dev, "state_100mhz"); 711 ret = pinctrl_select_state(dev, "state_100mhz");
712 break; 712 break;
713 case UHS_SDR104: 713 case UHS_SDR104:
714 case MMC_HS_200: 714 case MMC_HS_200:
715 case MMC_HS_400: 715 case MMC_HS_400:
716 case MMC_HS_400_ES: 716 case MMC_HS_400_ES:
717 ret = pinctrl_select_state(dev, "state_200mhz"); 717 ret = pinctrl_select_state(dev, "state_200mhz");
718 break; 718 break;
719 default: 719 default:
720 ret = pinctrl_select_state(dev, "default"); 720 ret = pinctrl_select_state(dev, "default");
721 break; 721 break;
722 } 722 }
723 723
724 if (ret) 724 if (ret)
725 printf("%s %d error\n", __func__, priv->mode); 725 printf("%s %d error\n", __func__, priv->mode);
726 726
727 return ret; 727 return ret;
728 } 728 }
729 729
730 static void esdhc_reset_tuning(struct mmc *mmc) 730 static void esdhc_reset_tuning(struct mmc *mmc)
731 { 731 {
732 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 732 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
733 struct fsl_esdhc *regs = priv->esdhc_regs; 733 struct fsl_esdhc *regs = priv->esdhc_regs;
734 734
735 if (priv->flags & ESDHC_FLAG_USDHC) { 735 if (priv->flags & ESDHC_FLAG_USDHC) {
736 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 736 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
737 esdhc_clrbits32(&regs->autoc12err, 737 esdhc_clrbits32(&regs->autoc12err,
738 MIX_CTRL_SMPCLK_SEL | 738 MIX_CTRL_SMPCLK_SEL |
739 MIX_CTRL_EXE_TUNE); 739 MIX_CTRL_EXE_TUNE);
740 } 740 }
741 } 741 }
742 } 742 }
743 743
744 static void esdhc_set_strobe_dll(struct mmc *mmc) 744 static void esdhc_set_strobe_dll(struct mmc *mmc)
745 { 745 {
746 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 746 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
747 struct fsl_esdhc *regs = priv->esdhc_regs; 747 struct fsl_esdhc *regs = priv->esdhc_regs;
748 u32 val; 748 u32 val;
749 749
750 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { 750 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
751 writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl); 751 writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
752 752
753 /* 753 /*
754 * enable strobe dll ctrl and adjust the delay target 754 * enable strobe dll ctrl and adjust the delay target
755 * for the uSDHC loopback read clock 755 * for the uSDHC loopback read clock
756 */ 756 */
757 val = ESDHC_STROBE_DLL_CTRL_ENABLE | 757 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
758 (priv->strobe_dll_delay_target << 758 (priv->strobe_dll_delay_target <<
759 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 759 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
760 writel(val, &regs->strobe_dllctrl); 760 writel(val, &regs->strobe_dllctrl);
761 /* wait 1us to make sure strobe dll status register stable */ 761 /* wait 1us to make sure strobe dll status register stable */
762 mdelay(1); 762 mdelay(1);
763 val = readl(&regs->strobe_dllstat); 763 val = readl(&regs->strobe_dllstat);
764 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) 764 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
765 pr_warn("HS400 strobe DLL status REF not lock!\n"); 765 pr_warn("HS400 strobe DLL status REF not lock!\n");
766 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) 766 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
767 pr_warn("HS400 strobe DLL status SLV not lock!\n"); 767 pr_warn("HS400 strobe DLL status SLV not lock!\n");
768 } 768 }
769 } 769 }
770 770
771 static int esdhc_set_timing(struct mmc *mmc) 771 static int esdhc_set_timing(struct mmc *mmc)
772 { 772 {
773 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 773 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
774 struct fsl_esdhc *regs = priv->esdhc_regs; 774 struct fsl_esdhc *regs = priv->esdhc_regs;
775 u32 mixctrl; 775 u32 mixctrl;
776 776
777 mixctrl = readl(&regs->mixctrl); 777 mixctrl = readl(&regs->mixctrl);
778 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); 778 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
779 779
780 switch (mmc->selected_mode) { 780 switch (mmc->selected_mode) {
781 case MMC_LEGACY: 781 case MMC_LEGACY:
782 case SD_LEGACY: 782 case SD_LEGACY:
783 esdhc_reset_tuning(mmc); 783 esdhc_reset_tuning(mmc);
784 writel(mixctrl, &regs->mixctrl); 784 writel(mixctrl, &regs->mixctrl);
785 break; 785 break;
786 case MMC_HS_400: 786 case MMC_HS_400:
787 case MMC_HS_400_ES: 787 case MMC_HS_400_ES:
788 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; 788 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
789 writel(mixctrl, &regs->mixctrl); 789 writel(mixctrl, &regs->mixctrl);
790 esdhc_set_strobe_dll(mmc); 790 esdhc_set_strobe_dll(mmc);
791 break; 791 break;
792 case MMC_HS: 792 case MMC_HS:
793 case MMC_HS_52: 793 case MMC_HS_52:
794 case MMC_HS_200: 794 case MMC_HS_200:
795 case SD_HS: 795 case SD_HS:
796 case UHS_SDR12: 796 case UHS_SDR12:
797 case UHS_SDR25: 797 case UHS_SDR25:
798 case UHS_SDR50: 798 case UHS_SDR50:
799 case UHS_SDR104: 799 case UHS_SDR104:
800 writel(mixctrl, &regs->mixctrl); 800 writel(mixctrl, &regs->mixctrl);
801 break; 801 break;
802 case UHS_DDR50: 802 case UHS_DDR50:
803 case MMC_DDR_52: 803 case MMC_DDR_52:
804 mixctrl |= MIX_CTRL_DDREN; 804 mixctrl |= MIX_CTRL_DDREN;
805 writel(mixctrl, &regs->mixctrl); 805 writel(mixctrl, &regs->mixctrl);
806 break; 806 break;
807 default: 807 default:
808 printf("Not supported %d\n", mmc->selected_mode); 808 printf("Not supported %d\n", mmc->selected_mode);
809 return -EINVAL; 809 return -EINVAL;
810 } 810 }
811 811
812 priv->mode = mmc->selected_mode; 812 priv->mode = mmc->selected_mode;
813 813
814 return esdhc_change_pinstate(mmc->dev); 814 return esdhc_change_pinstate(mmc->dev);
815 } 815 }
816 816
817 static int esdhc_set_voltage(struct mmc *mmc) 817 static int esdhc_set_voltage(struct mmc *mmc)
818 { 818 {
819 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); 819 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
820 struct fsl_esdhc *regs = priv->esdhc_regs; 820 struct fsl_esdhc *regs = priv->esdhc_regs;
821 int ret; 821 int ret;
822 822
823 priv->signal_voltage = mmc->signal_voltage; 823 priv->signal_voltage = mmc->signal_voltage;
824 switch (mmc->signal_voltage) { 824 switch (mmc->signal_voltage) {
825 case MMC_SIGNAL_VOLTAGE_330: 825 case MMC_SIGNAL_VOLTAGE_330:
826 if (priv->vs18_enable) 826 if (priv->vs18_enable)
827 return -EIO; 827 return -EIO;
828 #if CONFIG_IS_ENABLED(DM_REGULATOR) 828 #if CONFIG_IS_ENABLED(DM_REGULATOR)
829 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 829 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
830 ret = regulator_set_value(priv->vqmmc_dev, 3300000); 830 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
831 if (ret) { 831 if (ret) {
832 printf("Setting to 3.3V error"); 832 printf("Setting to 3.3V error");
833 return -EIO; 833 return -EIO;
834 } 834 }
835 /* Wait for 5ms */ 835 /* Wait for 5ms */
836 mdelay(5); 836 mdelay(5);
837 } 837 }
838 #endif 838 #endif
839 839
840 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); 840 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
841 if (!(esdhc_read32(&regs->vendorspec) & 841 if (!(esdhc_read32(&regs->vendorspec) &
842 ESDHC_VENDORSPEC_VSELECT)) 842 ESDHC_VENDORSPEC_VSELECT))
843 return 0; 843 return 0;
844 844
845 return -EAGAIN; 845 return -EAGAIN;
846 case MMC_SIGNAL_VOLTAGE_180: 846 case MMC_SIGNAL_VOLTAGE_180:
847 #if CONFIG_IS_ENABLED(DM_REGULATOR) 847 #if CONFIG_IS_ENABLED(DM_REGULATOR)
848 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { 848 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
849 ret = regulator_set_value(priv->vqmmc_dev, 1800000); 849 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
850 if (ret) { 850 if (ret) {
851 printf("Setting to 1.8V error"); 851 printf("Setting to 1.8V error");
852 return -EIO; 852 return -EIO;
853 } 853 }
854 } 854 }
855 #endif 855 #endif
856 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); 856 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
857 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT) 857 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
858 return 0; 858 return 0;
859 859
860 return -EAGAIN; 860 return -EAGAIN;
861 case MMC_SIGNAL_VOLTAGE_120: 861 case MMC_SIGNAL_VOLTAGE_120:
862 return -ENOTSUPP; 862 return -ENOTSUPP;
863 default: 863 default:
864 return 0; 864 return 0;
865 } 865 }
866 } 866 }
867 867
868 static void esdhc_stop_tuning(struct mmc *mmc) 868 static void esdhc_stop_tuning(struct mmc *mmc)
869 { 869 {
870 struct mmc_cmd cmd; 870 struct mmc_cmd cmd;
871 871
872 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 872 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
873 cmd.cmdarg = 0; 873 cmd.cmdarg = 0;
874 cmd.resp_type = MMC_RSP_R1b; 874 cmd.resp_type = MMC_RSP_R1b;
875 875
876 dm_mmc_send_cmd(mmc->dev, &cmd, NULL); 876 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
877 } 877 }
878 878
879 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) 879 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
880 { 880 {
881 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 881 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
882 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 882 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
883 struct fsl_esdhc *regs = priv->esdhc_regs; 883 struct fsl_esdhc *regs = priv->esdhc_regs;
884 struct mmc *mmc = &plat->mmc; 884 struct mmc *mmc = &plat->mmc;
885 u32 irqstaten = readl(&regs->irqstaten); 885 u32 irqstaten = readl(&regs->irqstaten);
886 u32 irqsigen = readl(&regs->irqsigen); 886 u32 irqsigen = readl(&regs->irqsigen);
887 int i, ret = -ETIMEDOUT; 887 int i, ret = -ETIMEDOUT;
888 u32 val, mixctrl; 888 u32 val, mixctrl;
889 889
890 /* clock tuning is not needed for upto 52MHz */ 890 /* clock tuning is not needed for upto 52MHz */
891 if (mmc->clock <= 52000000) 891 if (mmc->clock <= 52000000)
892 return 0; 892 return 0;
893 893
894 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ 894 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
895 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 895 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
896 val = readl(&regs->autoc12err); 896 val = readl(&regs->autoc12err);
897 mixctrl = readl(&regs->mixctrl); 897 mixctrl = readl(&regs->mixctrl);
898 val &= ~MIX_CTRL_SMPCLK_SEL; 898 val &= ~MIX_CTRL_SMPCLK_SEL;
899 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); 899 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
900 900
901 val |= MIX_CTRL_EXE_TUNE; 901 val |= MIX_CTRL_EXE_TUNE;
902 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; 902 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
903 903
904 writel(val, &regs->autoc12err); 904 writel(val, &regs->autoc12err);
905 writel(mixctrl, &regs->mixctrl); 905 writel(mixctrl, &regs->mixctrl);
906 } 906 }
907 907
908 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ 908 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
909 mixctrl = readl(&regs->mixctrl); 909 mixctrl = readl(&regs->mixctrl);
910 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); 910 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
911 writel(mixctrl, &regs->mixctrl); 911 writel(mixctrl, &regs->mixctrl);
912 912
913 writel(IRQSTATEN_BRR, &regs->irqstaten); 913 writel(IRQSTATEN_BRR, &regs->irqstaten);
914 writel(IRQSTATEN_BRR, &regs->irqsigen); 914 writel(IRQSTATEN_BRR, &regs->irqsigen);
915 915
916 /* 916 /*
917 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 917 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
918 * of loops reaches 40 times. 918 * of loops reaches 40 times.
919 */ 919 */
920 for (i = 0; i < MAX_TUNING_LOOP; i++) { 920 for (i = 0; i < MAX_TUNING_LOOP; i++) {
921 u32 ctrl; 921 u32 ctrl;
922 922
923 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { 923 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
924 if (mmc->bus_width == 8) 924 if (mmc->bus_width == 8)
925 writel(0x7080, &regs->blkattr); 925 writel(0x7080, &regs->blkattr);
926 else if (mmc->bus_width == 4) 926 else if (mmc->bus_width == 4)
927 writel(0x7040, &regs->blkattr); 927 writel(0x7040, &regs->blkattr);
928 } else { 928 } else {
929 writel(0x7040, &regs->blkattr); 929 writel(0x7040, &regs->blkattr);
930 } 930 }
931 931
932 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ 932 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
933 val = readl(&regs->mixctrl); 933 val = readl(&regs->mixctrl);
934 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); 934 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
935 writel(val, &regs->mixctrl); 935 writel(val, &regs->mixctrl);
936 936
937 /* We are using STD tuning, no need to check return value */ 937 /* We are using STD tuning, no need to check return value */
938 mmc_send_tuning(mmc, opcode, NULL); 938 mmc_send_tuning(mmc, opcode, NULL);
939 939
940 ctrl = readl(&regs->autoc12err); 940 ctrl = readl(&regs->autoc12err);
941 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && 941 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
942 (ctrl & MIX_CTRL_SMPCLK_SEL)) { 942 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
943 /* 943 /*
944 * need to wait some time, make sure sd/mmc fininsh 944 * need to wait some time, make sure sd/mmc fininsh
945 * send out tuning data, otherwise, the sd/mmc can't 945 * send out tuning data, otherwise, the sd/mmc can't
946 * response to any command when the card still out 946 * response to any command when the card still out
947 * put the tuning data. 947 * put the tuning data.
948 */ 948 */
949 mdelay(1); 949 mdelay(1);
950 ret = 0; 950 ret = 0;
951 break; 951 break;
952 } 952 }
953 953
954 /* Add 1ms delay for SD and eMMC */ 954 /* Add 1ms delay for SD and eMMC */
955 mdelay(1); 955 mdelay(1);
956 } 956 }
957 957
958 writel(irqstaten, &regs->irqstaten); 958 writel(irqstaten, &regs->irqstaten);
959 writel(irqsigen, &regs->irqsigen); 959 writel(irqsigen, &regs->irqsigen);
960 960
961 esdhc_stop_tuning(mmc); 961 esdhc_stop_tuning(mmc);
962 962
963 return ret; 963 return ret;
964 } 964 }
965 #endif 965 #endif
966 966
967 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 967 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
968 { 968 {
969 struct fsl_esdhc *regs = priv->esdhc_regs; 969 struct fsl_esdhc *regs = priv->esdhc_regs;
970 int ret __maybe_unused; 970 int ret __maybe_unused;
971 uint clock; 971 uint clock;
972 972
973 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 973 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
974 /* Select to use peripheral clock */ 974 /* Select to use peripheral clock */
975 esdhc_clock_control(priv, false); 975 esdhc_clock_control(priv, false);
976 esdhc_setbits32(&regs->scr, ESDHCCTL_PCS); 976 esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
977 esdhc_clock_control(priv, true); 977 esdhc_clock_control(priv, true);
978 #endif 978 #endif
979 /* Set the clock speed */ 979 /* Set the clock speed */
980 clock = mmc->clock; 980 clock = mmc->clock;
981 if (clock < mmc->cfg->f_min) 981 if (clock < mmc->cfg->f_min)
982 clock = mmc->cfg->f_min; 982 clock = mmc->cfg->f_min;
983 983
984 if (priv->clock != clock) 984 if (priv->clock != clock)
985 set_sysctl(priv, mmc, clock); 985 set_sysctl(priv, mmc, clock);
986 986
987 #ifdef MMC_SUPPORTS_TUNING 987 #ifdef MMC_SUPPORTS_TUNING
988 if (mmc->clk_disable) { 988 if (mmc->clk_disable) {
989 #ifdef CONFIG_FSL_USDHC 989 #ifdef CONFIG_FSL_USDHC
990 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); 990 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
991 #else 991 #else
992 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); 992 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
993 #endif 993 #endif
994 } else { 994 } else {
995 #ifdef CONFIG_FSL_USDHC 995 #ifdef CONFIG_FSL_USDHC
996 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | 996 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
997 VENDORSPEC_CKEN); 997 VENDORSPEC_CKEN);
998 #else 998 #else
999 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); 999 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
1000 #endif 1000 #endif
1001 } 1001 }
1002 1002
1003 if (priv->mode != mmc->selected_mode) { 1003 if (priv->mode != mmc->selected_mode) {
1004 ret = esdhc_set_timing(mmc); 1004 ret = esdhc_set_timing(mmc);
1005 if (ret) { 1005 if (ret) {
1006 printf("esdhc_set_timing error %d\n", ret); 1006 printf("esdhc_set_timing error %d\n", ret);
1007 return ret; 1007 return ret;
1008 } 1008 }
1009 } 1009 }
1010 1010
1011 if (priv->signal_voltage != mmc->signal_voltage) { 1011 if (priv->signal_voltage != mmc->signal_voltage) {
1012 ret = esdhc_set_voltage(mmc); 1012 ret = esdhc_set_voltage(mmc);
1013 if (ret) { 1013 if (ret) {
1014 printf("esdhc_set_voltage error %d\n", ret); 1014 printf("esdhc_set_voltage error %d\n", ret);
1015 return ret; 1015 return ret;
1016 } 1016 }
1017 } 1017 }
1018 #endif 1018 #endif
1019 1019
1020 /* Set the bus width */ 1020 /* Set the bus width */
1021 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 1021 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1022 1022
1023 if (mmc->bus_width == 4) 1023 if (mmc->bus_width == 4)
1024 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4); 1024 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
1025 else if (mmc->bus_width == 8) 1025 else if (mmc->bus_width == 8)
1026 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8); 1026 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
1027 1027
1028 return 0; 1028 return 0;
1029 } 1029 }
1030 1030
1031 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) 1031 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1032 { 1032 {
1033 struct fsl_esdhc *regs = priv->esdhc_regs; 1033 struct fsl_esdhc *regs = priv->esdhc_regs;
1034 ulong start; 1034 ulong start;
1035 1035
1036 /* Reset the entire host controller */ 1036 /* Reset the entire host controller */
1037 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA); 1037 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1038 1038
1039 /* Wait until the controller is available */ 1039 /* Wait until the controller is available */
1040 start = get_timer(0); 1040 start = get_timer(0);
1041 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) { 1041 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1042 if (get_timer(start) > 1000) 1042 if (get_timer(start) > 1000)
1043 return -ETIMEDOUT; 1043 return -ETIMEDOUT;
1044 } 1044 }
1045 1045
1046 #if defined(CONFIG_FSL_USDHC) 1046 #if defined(CONFIG_FSL_USDHC)
1047 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ 1047 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1048 esdhc_write32(&regs->mmcboot, 0x0); 1048 esdhc_write32(&regs->mmcboot, 0x0);
1049 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ 1049 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1050 esdhc_write32(&regs->mixctrl, 0x0); 1050 esdhc_write32(&regs->mixctrl, 0x0);
1051 esdhc_write32(&regs->clktunectrlstatus, 0x0); 1051 esdhc_write32(&regs->clktunectrlstatus, 0x0);
1052 1052
1053 /* Put VEND_SPEC to default value */ 1053 /* Put VEND_SPEC to default value */
1054 if (priv->vs18_enable) 1054 if (priv->vs18_enable)
1055 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT | 1055 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
1056 ESDHC_VENDORSPEC_VSELECT)); 1056 ESDHC_VENDORSPEC_VSELECT));
1057 else 1057 else
1058 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT); 1058 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
1059 1059
1060 /* Disable DLL_CTRL delay line */ 1060 /* Disable DLL_CTRL delay line */
1061 esdhc_write32(&regs->dllctrl, 0x0); 1061 esdhc_write32(&regs->dllctrl, 0x0);
1062 #endif 1062 #endif
1063 1063
1064 #ifndef ARCH_MXC 1064 #ifndef ARCH_MXC
1065 /* Enable cache snooping */ 1065 /* Enable cache snooping */
1066 esdhc_write32(&regs->scr, 0x00000040); 1066 esdhc_write32(&regs->scr, 0x00000040);
1067 #endif 1067 #endif
1068 1068
1069 #ifndef CONFIG_FSL_USDHC 1069 #ifndef CONFIG_FSL_USDHC
1070 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 1070 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1071 #else 1071 #else
1072 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); 1072 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1073 #endif 1073 #endif
1074 1074
1075 /* Set the initial clock speed */ 1075 /* Set the initial clock speed */
1076 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); 1076 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1077 1077
1078 /* Disable the BRR and BWR bits in IRQSTAT */ 1078 /* Disable the BRR and BWR bits in IRQSTAT */
1079 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 1079 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1080 1080
1081 #ifdef CONFIG_MCF5441x 1081 #ifdef CONFIG_MCF5441x
1082 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); 1082 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1083 #else 1083 #else
1084 /* Put the PROCTL reg back to the default */ 1084 /* Put the PROCTL reg back to the default */
1085 esdhc_write32(&regs->proctl, PROCTL_INIT); 1085 esdhc_write32(&regs->proctl, PROCTL_INIT);
1086 #endif 1086 #endif
1087 1087
1088 /* Set timout to the maximum value */ 1088 /* Set timout to the maximum value */
1089 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 1089 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1090 1090
1091 return 0; 1091 return 0;
1092 } 1092 }
1093 1093
1094 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) 1094 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1095 { 1095 {
1096 struct fsl_esdhc *regs = priv->esdhc_regs; 1096 struct fsl_esdhc *regs = priv->esdhc_regs;
1097 int timeout = 1000; 1097 int timeout = 1000;
1098 1098
1099 #ifdef CONFIG_ESDHC_DETECT_QUIRK 1099 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1100 if (CONFIG_ESDHC_DETECT_QUIRK) 1100 if (CONFIG_ESDHC_DETECT_QUIRK)
1101 return 1; 1101 return 1;
1102 #endif 1102 #endif
1103 1103
1104 #if CONFIG_IS_ENABLED(DM_MMC) 1104 #if CONFIG_IS_ENABLED(DM_MMC)
1105 if (priv->non_removable) 1105 if (priv->non_removable)
1106 return 1; 1106 return 1;
1107 #ifdef CONFIG_DM_GPIO 1107 #ifdef CONFIG_DM_GPIO
1108 if (dm_gpio_is_valid(&priv->cd_gpio)) 1108 if (dm_gpio_is_valid(&priv->cd_gpio))
1109 return dm_gpio_get_value(&priv->cd_gpio); 1109 return dm_gpio_get_value(&priv->cd_gpio);
1110 #endif 1110 #endif
1111 #endif 1111 #endif
1112 1112
1113 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) 1113 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1114 udelay(1000); 1114 udelay(1000);
1115 1115
1116 return timeout > 0; 1116 return timeout > 0;
1117 } 1117 }
1118 1118
1119 static int esdhc_reset(struct fsl_esdhc *regs) 1119 static int esdhc_reset(struct fsl_esdhc *regs)
1120 { 1120 {
1121 ulong start; 1121 ulong start;
1122 1122
1123 /* reset the controller */ 1123 /* reset the controller */
1124 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA); 1124 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1125 1125
1126 /* hardware clears the bit when it is done */ 1126 /* hardware clears the bit when it is done */
1127 start = get_timer(0); 1127 start = get_timer(0);
1128 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) { 1128 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1129 if (get_timer(start) > 100) { 1129 if (get_timer(start) > 100) {
1130 printf("MMC/SD: Reset never completed.\n"); 1130 printf("MMC/SD: Reset never completed.\n");
1131 return -ETIMEDOUT; 1131 return -ETIMEDOUT;
1132 } 1132 }
1133 } 1133 }
1134 1134
1135 return 0; 1135 return 0;
1136 } 1136 }
1137 1137
1138 #if !CONFIG_IS_ENABLED(DM_MMC) 1138 #if !CONFIG_IS_ENABLED(DM_MMC)
1139 static int esdhc_getcd(struct mmc *mmc) 1139 static int esdhc_getcd(struct mmc *mmc)
1140 { 1140 {
1141 struct fsl_esdhc_priv *priv = mmc->priv; 1141 struct fsl_esdhc_priv *priv = mmc->priv;
1142 1142
1143 return esdhc_getcd_common(priv); 1143 return esdhc_getcd_common(priv);
1144 } 1144 }
1145 1145
1146 static int esdhc_init(struct mmc *mmc) 1146 static int esdhc_init(struct mmc *mmc)
1147 { 1147 {
1148 struct fsl_esdhc_priv *priv = mmc->priv; 1148 struct fsl_esdhc_priv *priv = mmc->priv;
1149 1149
1150 return esdhc_init_common(priv, mmc); 1150 return esdhc_init_common(priv, mmc);
1151 } 1151 }
1152 1152
1153 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 1153 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1154 struct mmc_data *data) 1154 struct mmc_data *data)
1155 { 1155 {
1156 struct fsl_esdhc_priv *priv = mmc->priv; 1156 struct fsl_esdhc_priv *priv = mmc->priv;
1157 1157
1158 return esdhc_send_cmd_common(priv, mmc, cmd, data); 1158 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1159 } 1159 }
1160 1160
1161 static int esdhc_set_ios(struct mmc *mmc) 1161 static int esdhc_set_ios(struct mmc *mmc)
1162 { 1162 {
1163 struct fsl_esdhc_priv *priv = mmc->priv; 1163 struct fsl_esdhc_priv *priv = mmc->priv;
1164 1164
1165 return esdhc_set_ios_common(priv, mmc); 1165 return esdhc_set_ios_common(priv, mmc);
1166 } 1166 }
1167 1167
1168 static const struct mmc_ops esdhc_ops = { 1168 static const struct mmc_ops esdhc_ops = {
1169 .getcd = esdhc_getcd, 1169 .getcd = esdhc_getcd,
1170 .init = esdhc_init, 1170 .init = esdhc_init,
1171 .send_cmd = esdhc_send_cmd, 1171 .send_cmd = esdhc_send_cmd,
1172 .set_ios = esdhc_set_ios, 1172 .set_ios = esdhc_set_ios,
1173 }; 1173 };
1174 #endif 1174 #endif
1175 1175
1176 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, 1176 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1177 struct fsl_esdhc_plat *plat) 1177 struct fsl_esdhc_plat *plat)
1178 { 1178 {
1179 struct mmc_config *cfg; 1179 struct mmc_config *cfg;
1180 struct fsl_esdhc *regs; 1180 struct fsl_esdhc *regs;
1181 u32 caps, voltage_caps; 1181 u32 caps, voltage_caps;
1182 int ret; 1182 int ret;
1183 1183
1184 if (!priv) 1184 if (!priv)
1185 return -EINVAL; 1185 return -EINVAL;
1186 1186
1187 regs = priv->esdhc_regs; 1187 regs = priv->esdhc_regs;
1188 1188
1189 /* First reset the eSDHC controller */ 1189 /* First reset the eSDHC controller */
1190 ret = esdhc_reset(regs); 1190 ret = esdhc_reset(regs);
1191 if (ret) 1191 if (ret)
1192 return ret; 1192 return ret;
1193 1193
1194 #ifdef CONFIG_MCF5441x 1194 #ifdef CONFIG_MCF5441x
1195 /* ColdFire, using SDHC_DATA[3] for card detection */ 1195 /* ColdFire, using SDHC_DATA[3] for card detection */
1196 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); 1196 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1197 #endif 1197 #endif
1198 1198
1199 #ifndef CONFIG_FSL_USDHC 1199 #ifndef CONFIG_FSL_USDHC
1200 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN 1200 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1201 | SYSCTL_IPGEN | SYSCTL_CKEN); 1201 | SYSCTL_IPGEN | SYSCTL_CKEN);
1202 /* Clearing tuning bits in case ROM has set it already */ 1202 /* Clearing tuning bits in case ROM has set it already */
1203 esdhc_write32(&regs->mixctrl, 0); 1203 esdhc_write32(&regs->mixctrl, 0);
1204 esdhc_write32(&regs->autoc12err, 0); 1204 esdhc_write32(&regs->autoc12err, 0);
1205 esdhc_write32(&regs->clktunectrlstatus, 0); 1205 esdhc_write32(&regs->clktunectrlstatus, 0);
1206 #else 1206 #else
1207 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | 1207 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
1208 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); 1208 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1209 #endif 1209 #endif
1210 1210
1211 if (priv->vs18_enable) 1211 if (priv->vs18_enable)
1212 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); 1212 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1213 1213
1214 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); 1214 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
1215 cfg = &plat->cfg; 1215 cfg = &plat->cfg;
1216 #ifndef CONFIG_DM_MMC 1216 #ifndef CONFIG_DM_MMC
1217 memset(cfg, '\0', sizeof(*cfg)); 1217 memset(cfg, '\0', sizeof(*cfg));
1218 #endif 1218 #endif
1219 1219
1220 voltage_caps = 0; 1220 voltage_caps = 0;
1221 caps = esdhc_read32(&regs->hostcapblt); 1221 caps = esdhc_read32(&regs->hostcapblt);
1222 1222
1223 #ifdef CONFIG_MCF5441x 1223 #ifdef CONFIG_MCF5441x
1224 /* 1224 /*
1225 * MCF5441x RM declares in more points that sdhc clock speed must 1225 * MCF5441x RM declares in more points that sdhc clock speed must
1226 * never exceed 25 Mhz. From this, the HS bit needs to be disabled 1226 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1227 * from host capabilities. 1227 * from host capabilities.
1228 */ 1228 */
1229 caps &= ~ESDHC_HOSTCAPBLT_HSS; 1229 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1230 #endif 1230 #endif
1231 1231
1232 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 1232 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1233 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | 1233 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1234 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); 1234 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1235 #endif 1235 #endif
1236 1236
1237 /* T4240 host controller capabilities register should have VS33 bit */ 1237 /* T4240 host controller capabilities register should have VS33 bit */
1238 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 1238 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1239 caps = caps | ESDHC_HOSTCAPBLT_VS33; 1239 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1240 #endif 1240 #endif
1241 1241
1242 if (caps & ESDHC_HOSTCAPBLT_VS18) 1242 if (caps & ESDHC_HOSTCAPBLT_VS18)
1243 voltage_caps |= MMC_VDD_165_195; 1243 voltage_caps |= MMC_VDD_165_195;
1244 if (caps & ESDHC_HOSTCAPBLT_VS30) 1244 if (caps & ESDHC_HOSTCAPBLT_VS30)
1245 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; 1245 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1246 if (caps & ESDHC_HOSTCAPBLT_VS33) 1246 if (caps & ESDHC_HOSTCAPBLT_VS33)
1247 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; 1247 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1248 1248
1249 cfg->name = "FSL_SDHC"; 1249 cfg->name = "FSL_SDHC";
1250 #if !CONFIG_IS_ENABLED(DM_MMC) 1250 #if !CONFIG_IS_ENABLED(DM_MMC)
1251 cfg->ops = &esdhc_ops; 1251 cfg->ops = &esdhc_ops;
1252 #endif 1252 #endif
1253 #ifdef CONFIG_SYS_SD_VOLTAGE 1253 #ifdef CONFIG_SYS_SD_VOLTAGE
1254 cfg->voltages = CONFIG_SYS_SD_VOLTAGE; 1254 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1255 #else 1255 #else
1256 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 1256 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1257 #endif 1257 #endif
1258 if ((cfg->voltages & voltage_caps) == 0) { 1258 if ((cfg->voltages & voltage_caps) == 0) {
1259 printf("voltage not supported by controller\n"); 1259 printf("voltage not supported by controller\n");
1260 return -1; 1260 return -1;
1261 } 1261 }
1262 1262
1263 if (priv->bus_width == 8) 1263 if (priv->bus_width == 8)
1264 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1264 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1265 else if (priv->bus_width == 4) 1265 else if (priv->bus_width == 4)
1266 cfg->host_caps = MMC_MODE_4BIT; 1266 cfg->host_caps = MMC_MODE_4BIT;
1267 1267
1268 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 1268 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1269 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE 1269 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1270 cfg->host_caps |= MMC_MODE_DDR_52MHz; 1270 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1271 #endif 1271 #endif
1272 1272
1273 if (priv->bus_width > 0) { 1273 if (priv->bus_width > 0) {
1274 if (priv->bus_width < 8) 1274 if (priv->bus_width < 8)
1275 cfg->host_caps &= ~MMC_MODE_8BIT; 1275 cfg->host_caps &= ~MMC_MODE_8BIT;
1276 if (priv->bus_width < 4) 1276 if (priv->bus_width < 4)
1277 cfg->host_caps &= ~MMC_MODE_4BIT; 1277 cfg->host_caps &= ~MMC_MODE_4BIT;
1278 } 1278 }
1279 1279
1280 if (caps & ESDHC_HOSTCAPBLT_HSS) 1280 if (caps & ESDHC_HOSTCAPBLT_HSS)
1281 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 1281 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1282 1282
1283 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK 1283 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1284 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) 1284 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1285 cfg->host_caps &= ~MMC_MODE_8BIT; 1285 cfg->host_caps &= ~MMC_MODE_8BIT;
1286 #endif 1286 #endif
1287 1287
1288 cfg->host_caps |= priv->caps; 1288 cfg->host_caps |= priv->caps;
1289 1289
1290 cfg->f_min = 400000; 1290 cfg->f_min = 400000;
1291 cfg->f_max = min(priv->sdhc_clk, (u32)200000000); 1291 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1292 1292
1293 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 1293 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1294 1294
1295 writel(0, &regs->dllctrl); 1295 writel(0, &regs->dllctrl);
1296 if (priv->flags & ESDHC_FLAG_USDHC) { 1296 if (priv->flags & ESDHC_FLAG_USDHC) {
1297 if (priv->flags & ESDHC_FLAG_STD_TUNING) { 1297 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1298 u32 val = readl(&regs->tuning_ctrl); 1298 u32 val = readl(&regs->tuning_ctrl);
1299 1299
1300 val |= ESDHC_STD_TUNING_EN; 1300 val |= ESDHC_STD_TUNING_EN;
1301 val &= ~ESDHC_TUNING_START_TAP_MASK; 1301 val &= ~ESDHC_TUNING_START_TAP_MASK;
1302 val |= priv->tuning_start_tap; 1302 val |= priv->tuning_start_tap;
1303 val &= ~ESDHC_TUNING_STEP_MASK; 1303 val &= ~ESDHC_TUNING_STEP_MASK;
1304 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT; 1304 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1305 writel(val, &regs->tuning_ctrl); 1305 writel(val, &regs->tuning_ctrl);
1306 } 1306 }
1307 } 1307 }
1308 1308
1309 return 0; 1309 return 0;
1310 } 1310 }
1311 1311
1312 #if !CONFIG_IS_ENABLED(DM_MMC) 1312 #if !CONFIG_IS_ENABLED(DM_MMC)
1313 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, 1313 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1314 struct fsl_esdhc_priv *priv) 1314 struct fsl_esdhc_priv *priv)
1315 { 1315 {
1316 if (!cfg || !priv) 1316 if (!cfg || !priv)
1317 return -EINVAL; 1317 return -EINVAL;
1318 1318
1319 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); 1319 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1320 priv->bus_width = cfg->max_bus_width; 1320 priv->bus_width = cfg->max_bus_width;
1321 priv->sdhc_clk = cfg->sdhc_clk; 1321 priv->sdhc_clk = cfg->sdhc_clk;
1322 priv->wp_enable = cfg->wp_enable; 1322 priv->wp_enable = cfg->wp_enable;
1323 priv->vs18_enable = cfg->vs18_enable; 1323 priv->vs18_enable = cfg->vs18_enable;
1324 1324
1325 return 0; 1325 return 0;
1326 }; 1326 };
1327 1327
1328 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 1328 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1329 { 1329 {
1330 struct fsl_esdhc_plat *plat; 1330 struct fsl_esdhc_plat *plat;
1331 struct fsl_esdhc_priv *priv; 1331 struct fsl_esdhc_priv *priv;
1332 struct mmc *mmc; 1332 struct mmc *mmc;
1333 int ret; 1333 int ret;
1334 1334
1335 if (!cfg) 1335 if (!cfg)
1336 return -EINVAL; 1336 return -EINVAL;
1337 1337
1338 priv = calloc(sizeof(struct fsl_esdhc_priv), 1); 1338 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1339 if (!priv) 1339 if (!priv)
1340 return -ENOMEM; 1340 return -ENOMEM;
1341 plat = calloc(sizeof(struct fsl_esdhc_plat), 1); 1341 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1342 if (!plat) { 1342 if (!plat) {
1343 free(priv); 1343 free(priv);
1344 return -ENOMEM; 1344 return -ENOMEM;
1345 } 1345 }
1346 1346
1347 ret = fsl_esdhc_cfg_to_priv(cfg, priv); 1347 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1348 if (ret) { 1348 if (ret) {
1349 debug("%s xlate failure\n", __func__); 1349 debug("%s xlate failure\n", __func__);
1350 free(plat); 1350 free(plat);
1351 free(priv); 1351 free(priv);
1352 return ret; 1352 return ret;
1353 } 1353 }
1354 1354
1355 #ifdef CONFIG_MX6 1355 #ifdef CONFIG_MX6
1356 if (mx6_esdhc_fused(cfg->esdhc_base)) { 1356 if (mx6_esdhc_fused(cfg->esdhc_base)) {
1357 printf("ESDHC@0x%lx is fused, disable it\n", cfg->esdhc_base); 1357 printf("ESDHC@0x%lx is fused, disable it\n", cfg->esdhc_base);
1358 free(priv); 1358 free(priv);
1359 return -ENODEV; 1359 return -ENODEV;
1360 } 1360 }
1361 #endif 1361 #endif
1362 1362
1363 ret = fsl_esdhc_init(priv, plat); 1363 ret = fsl_esdhc_init(priv, plat);
1364 if (ret) { 1364 if (ret) {
1365 debug("%s init failure\n", __func__); 1365 debug("%s init failure\n", __func__);
1366 free(plat); 1366 free(plat);
1367 free(priv); 1367 free(priv);
1368 return ret; 1368 return ret;
1369 } 1369 }
1370 1370
1371 mmc = mmc_create(&plat->cfg, priv); 1371 mmc = mmc_create(&plat->cfg, priv);
1372 if (!mmc) 1372 if (!mmc)
1373 return -EIO; 1373 return -EIO;
1374 1374
1375 priv->mmc = mmc; 1375 priv->mmc = mmc;
1376 1376
1377 return 0; 1377 return 0;
1378 } 1378 }
1379 1379
1380 int fsl_esdhc_mmc_init(bd_t *bis) 1380 int fsl_esdhc_mmc_init(bd_t *bis)
1381 { 1381 {
1382 struct fsl_esdhc_cfg *cfg; 1382 struct fsl_esdhc_cfg *cfg;
1383 1383
1384 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); 1384 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1385 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 1385 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1386 cfg->sdhc_clk = gd->arch.sdhc_clk; 1386 cfg->sdhc_clk = gd->arch.sdhc_clk;
1387 return fsl_esdhc_initialize(bis, cfg); 1387 return fsl_esdhc_initialize(bis, cfg);
1388 } 1388 }
1389 #endif 1389 #endif
1390 1390
1391 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1391 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1392 void mmc_adapter_card_type_ident(void) 1392 void mmc_adapter_card_type_ident(void)
1393 { 1393 {
1394 u8 card_id; 1394 u8 card_id;
1395 u8 value; 1395 u8 value;
1396 1396
1397 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; 1397 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1398 gd->arch.sdhc_adapter = card_id; 1398 gd->arch.sdhc_adapter = card_id;
1399 1399
1400 switch (card_id) { 1400 switch (card_id) {
1401 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: 1401 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1402 value = QIXIS_READ(brdcfg[5]); 1402 value = QIXIS_READ(brdcfg[5]);
1403 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); 1403 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1404 QIXIS_WRITE(brdcfg[5], value); 1404 QIXIS_WRITE(brdcfg[5], value);
1405 break; 1405 break;
1406 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: 1406 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1407 value = QIXIS_READ(pwr_ctl[1]); 1407 value = QIXIS_READ(pwr_ctl[1]);
1408 value |= QIXIS_EVDD_BY_SDHC_VS; 1408 value |= QIXIS_EVDD_BY_SDHC_VS;
1409 QIXIS_WRITE(pwr_ctl[1], value); 1409 QIXIS_WRITE(pwr_ctl[1], value);
1410 break; 1410 break;
1411 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: 1411 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1412 value = QIXIS_READ(brdcfg[5]); 1412 value = QIXIS_READ(brdcfg[5]);
1413 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); 1413 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1414 QIXIS_WRITE(brdcfg[5], value); 1414 QIXIS_WRITE(brdcfg[5], value);
1415 break; 1415 break;
1416 case QIXIS_ESDHC_ADAPTER_TYPE_RSV: 1416 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1417 break; 1417 break;
1418 case QIXIS_ESDHC_ADAPTER_TYPE_MMC: 1418 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1419 break; 1419 break;
1420 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 1420 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1421 break; 1421 break;
1422 case QIXIS_ESDHC_NO_ADAPTER: 1422 case QIXIS_ESDHC_NO_ADAPTER:
1423 break; 1423 break;
1424 default: 1424 default:
1425 break; 1425 break;
1426 } 1426 }
1427 } 1427 }
1428 #endif 1428 #endif
1429 1429
1430 #ifdef CONFIG_OF_LIBFDT 1430 #ifdef CONFIG_OF_LIBFDT
1431 __weak int esdhc_status_fixup(void *blob, const char *compat) 1431 __weak int esdhc_status_fixup(void *blob, const char *compat)
1432 { 1432 {
1433 #ifdef CONFIG_FSL_ESDHC_PIN_MUX 1433 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1434 if (!hwconfig("esdhc")) { 1434 if (!hwconfig("esdhc")) {
1435 do_fixup_by_compat(blob, compat, "status", "disabled", 1435 do_fixup_by_compat(blob, compat, "status", "disabled",
1436 sizeof("disabled"), 1); 1436 sizeof("disabled"), 1);
1437 return 1; 1437 return 1;
1438 } 1438 }
1439 #endif 1439 #endif
1440 return 0; 1440 return 0;
1441 } 1441 }
1442 1442
1443 void fdt_fixup_esdhc(void *blob, bd_t *bd) 1443 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1444 { 1444 {
1445 const char *compat = "fsl,esdhc"; 1445 const char *compat = "fsl,esdhc";
1446 1446
1447 if (esdhc_status_fixup(blob, compat)) 1447 if (esdhc_status_fixup(blob, compat))
1448 return; 1448 return;
1449 1449
1450 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 1450 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1451 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", 1451 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1452 gd->arch.sdhc_clk, 1); 1452 gd->arch.sdhc_clk, 1);
1453 #else 1453 #else
1454 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 1454 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1455 gd->arch.sdhc_clk, 1); 1455 gd->arch.sdhc_clk, 1);
1456 #endif 1456 #endif
1457 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1457 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1458 do_fixup_by_compat_u32(blob, compat, "adapter-type", 1458 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1459 (u32)(gd->arch.sdhc_adapter), 1); 1459 (u32)(gd->arch.sdhc_adapter), 1);
1460 #endif 1460 #endif
1461 } 1461 }
1462 #endif 1462 #endif
1463 1463
1464 #if CONFIG_IS_ENABLED(DM_MMC) 1464 #if CONFIG_IS_ENABLED(DM_MMC)
1465 #include <asm/arch/clock.h> 1465 #include <asm/arch/clock.h>
1466 __weak void init_clk_usdhc(u32 index) 1466 __weak void init_clk_usdhc(u32 index)
1467 { 1467 {
1468 } 1468 }
1469 1469
1470 static int fsl_esdhc_probe(struct udevice *dev) 1470 static int fsl_esdhc_probe(struct udevice *dev)
1471 { 1471 {
1472 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1472 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1473 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1473 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1474 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1474 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1475 const void *fdt = gd->fdt_blob; 1475 const void *fdt = gd->fdt_blob;
1476 int node = dev_of_offset(dev); 1476 int node = dev_of_offset(dev);
1477 struct esdhc_soc_data *data = 1477 struct esdhc_soc_data *data =
1478 (struct esdhc_soc_data *)dev_get_driver_data(dev); 1478 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1479 #if CONFIG_IS_ENABLED(DM_REGULATOR) 1479 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1480 struct udevice *vqmmc_dev; 1480 struct udevice *vqmmc_dev;
1481 #endif 1481 #endif
1482 fdt_addr_t addr; 1482 fdt_addr_t addr;
1483 unsigned int val; 1483 unsigned int val;
1484 struct mmc *mmc; 1484 struct mmc *mmc;
1485 int ret; 1485 int ret;
1486 1486
1487 addr = dev_read_addr(dev); 1487 addr = dev_read_addr(dev);
1488 if (addr == FDT_ADDR_T_NONE) 1488 if (addr == FDT_ADDR_T_NONE)
1489 return -EINVAL; 1489 return -EINVAL;
1490 1490
1491 #ifdef CONFIG_MX6 1491 #ifdef CONFIG_MX6
1492 if (mx6_esdhc_fused(addr)) { 1492 if (mx6_esdhc_fused(addr)) {
1493 printf("ESDHC@0x%lx is fused, disable it\n", addr); 1493 printf("ESDHC@0x%lx is fused, disable it\n", addr);
1494 return -ENODEV; 1494 return -ENODEV;
1495 } 1495 }
1496 #endif 1496 #endif
1497 1497
1498 priv->esdhc_regs = (struct fsl_esdhc *)addr; 1498 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1499 priv->dev = dev; 1499 priv->dev = dev;
1500 priv->mode = -1; 1500 priv->mode = -1;
1501 if (data) { 1501 if (data) {
1502 priv->flags = data->flags; 1502 priv->flags = data->flags;
1503 priv->caps = data->caps; 1503 priv->caps = data->caps;
1504 } 1504 }
1505 1505
1506 val = dev_read_u32_default(dev, "bus-width", -1); 1506 val = dev_read_u32_default(dev, "bus-width", -1);
1507 if (val == 8) 1507 if (val == 8)
1508 priv->bus_width = 8; 1508 priv->bus_width = 8;
1509 else if (val == 4) 1509 else if (val == 4)
1510 priv->bus_width = 4; 1510 priv->bus_width = 4;
1511 else 1511 else
1512 priv->bus_width = 1; 1512 priv->bus_width = 1;
1513 1513
1514 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1); 1514 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1515 priv->tuning_step = val; 1515 priv->tuning_step = val;
1516 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", 1516 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1517 ESDHC_TUNING_START_TAP_DEFAULT); 1517 ESDHC_TUNING_START_TAP_DEFAULT);
1518 priv->tuning_start_tap = val; 1518 priv->tuning_start_tap = val;
1519 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", 1519 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1520 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); 1520 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1521 priv->strobe_dll_delay_target = val; 1521 priv->strobe_dll_delay_target = val;
1522 1522
1523 if (dev_read_bool(dev, "non-removable")) { 1523 if (dev_read_bool(dev, "non-removable")) {
1524 priv->non_removable = 1; 1524 priv->non_removable = 1;
1525 } else { 1525 } else {
1526 priv->non_removable = 0; 1526 priv->non_removable = 0;
1527 #ifdef CONFIG_DM_GPIO 1527 #ifdef CONFIG_DM_GPIO
1528 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 1528 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1529 GPIOD_IS_IN); 1529 GPIOD_IS_IN);
1530 #endif 1530 #endif
1531 } 1531 }
1532 1532
1533 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) { 1533 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1534 priv->wp_enable = 1; 1534 priv->wp_enable = 1;
1535 } else { 1535 } else {
1536 priv->wp_enable = 0; 1536 priv->wp_enable = 0;
1537 #ifdef CONFIG_DM_GPIO 1537 #ifdef CONFIG_DM_GPIO
1538 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 1538 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1539 GPIOD_IS_IN); 1539 GPIOD_IS_IN);
1540 #endif 1540 #endif
1541 } 1541 }
1542 1542
1543 priv->vs18_enable = 0; 1543 priv->vs18_enable = 0;
1544 1544
1545 #if CONFIG_IS_ENABLED(DM_REGULATOR) 1545 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1546 /* 1546 /*
1547 * If emmc I/O has a fixed voltage at 1.8V, this must be provided, 1547 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1548 * otherwise, emmc will work abnormally. 1548 * otherwise, emmc will work abnormally.
1549 */ 1549 */
1550 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 1550 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1551 if (ret) { 1551 if (ret) {
1552 dev_dbg(dev, "no vqmmc-supply\n"); 1552 dev_dbg(dev, "no vqmmc-supply\n");
1553 } else { 1553 } else {
1554 ret = regulator_set_enable(vqmmc_dev, true); 1554 ret = regulator_set_enable(vqmmc_dev, true);
1555 if (ret) { 1555 if (ret) {
1556 dev_err(dev, "fail to enable vqmmc-supply\n"); 1556 dev_err(dev, "fail to enable vqmmc-supply\n");
1557 return ret; 1557 return ret;
1558 } 1558 }
1559 1559
1560 if (regulator_get_value(vqmmc_dev) == 1800000) 1560 if (regulator_get_value(vqmmc_dev) == 1800000)
1561 priv->vs18_enable = 1; 1561 priv->vs18_enable = 1;
1562 } 1562 }
1563 #endif 1563 #endif
1564 1564
1565 if (fdt_get_property(fdt, node, "no-1-8-v", NULL)) 1565 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1566 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); 1566 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES);
1567 1567
1568 /* 1568 /*
1569 * TODO: 1569 * TODO:
1570 * Because lack of clk driver, if SDHC clk is not enabled, 1570 * Because lack of clk driver, if SDHC clk is not enabled,
1571 * need to enable it first before this driver is invoked. 1571 * need to enable it first before this driver is invoked.
1572 * 1572 *
1573 * we use MXC_ESDHC_CLK to get clk freq. 1573 * we use MXC_ESDHC_CLK to get clk freq.
1574 * If one would like to make this function work, 1574 * If one would like to make this function work,
1575 * the aliases should be provided in dts as this: 1575 * the aliases should be provided in dts as this:
1576 * 1576 *
1577 * aliases { 1577 * aliases {
1578 * mmc0 = &usdhc1; 1578 * mmc0 = &usdhc1;
1579 * mmc1 = &usdhc2; 1579 * mmc1 = &usdhc2;
1580 * mmc2 = &usdhc3; 1580 * mmc2 = &usdhc3;
1581 * mmc3 = &usdhc4; 1581 * mmc3 = &usdhc4;
1582 * }; 1582 * };
1583 * Then if your board only supports mmc2 and mmc3, but we can 1583 * Then if your board only supports mmc2 and mmc3, but we can
1584 * correctly get the seq as 2 and 3, then let mxc_get_clock 1584 * correctly get the seq as 2 and 3, then let mxc_get_clock
1585 * work as expected. 1585 * work as expected.
1586 */ 1586 */
1587 1587
1588 if (CONFIG_IS_ENABLED(CLK)) { 1588 if (CONFIG_IS_ENABLED(CLK)) {
1589 /* Assigned clock already set clock */ 1589 /* Assigned clock already set clock */
1590 ret = clk_get_by_name(dev, "per", &priv->per_clk); 1590 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1591 if (ret) { 1591 if (ret) {
1592 printf("Failed to get per_clk\n"); 1592 printf("Failed to get per_clk\n");
1593 return ret; 1593 return ret;
1594 } 1594 }
1595 ret = clk_enable(&priv->per_clk); 1595 ret = clk_enable(&priv->per_clk);
1596 if (ret) { 1596 if (ret) {
1597 printf("Failed to enable per_clk\n"); 1597 printf("Failed to enable per_clk\n");
1598 return ret; 1598 return ret;
1599 } 1599 }
1600 1600
1601 priv->sdhc_clk = clk_get_rate(&priv->per_clk); 1601 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1602 } else { 1602 } else {
1603 init_clk_usdhc(dev->seq); 1603 init_clk_usdhc(dev->seq);
1604 1604
1605 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); 1605 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1606 if (priv->sdhc_clk <= 0) { 1606 if (priv->sdhc_clk <= 0) {
1607 dev_err(dev, "Unable to get clk for %s\n", dev->name); 1607 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1608 return -EINVAL; 1608 return -EINVAL;
1609 } 1609 }
1610 } 1610 }
1611 1611
1612 ret = fsl_esdhc_init(priv, plat); 1612 ret = fsl_esdhc_init(priv, plat);
1613 if (ret) { 1613 if (ret) {
1614 dev_err(dev, "fsl_esdhc_init failure\n"); 1614 dev_err(dev, "fsl_esdhc_init failure\n");
1615 return ret; 1615 return ret;
1616 } 1616 }
1617 1617
1618 mmc = &plat->mmc; 1618 mmc = &plat->mmc;
1619 mmc->cfg = &plat->cfg; 1619 mmc->cfg = &plat->cfg;
1620 mmc->dev = dev; 1620 mmc->dev = dev;
1621 upriv->mmc = mmc; 1621 upriv->mmc = mmc;
1622 1622
1623 return esdhc_init_common(priv, mmc); 1623 return esdhc_init_common(priv, mmc);
1624 } 1624 }
1625 1625
1626 #if CONFIG_IS_ENABLED(DM_MMC) 1626 #if CONFIG_IS_ENABLED(DM_MMC)
1627 static int fsl_esdhc_get_cd(struct udevice *dev) 1627 static int fsl_esdhc_get_cd(struct udevice *dev)
1628 { 1628 {
1629 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1629 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1630 1630
1631 return esdhc_getcd_common(priv); 1631 return esdhc_getcd_common(priv);
1632 } 1632 }
1633 1633
1634 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 1634 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1635 struct mmc_data *data) 1635 struct mmc_data *data)
1636 { 1636 {
1637 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1637 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1638 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1638 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1639 1639
1640 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); 1640 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1641 } 1641 }
1642 1642
1643 static int fsl_esdhc_set_ios(struct udevice *dev) 1643 static int fsl_esdhc_set_ios(struct udevice *dev)
1644 { 1644 {
1645 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1645 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1646 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1646 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1647 1647
1648 return esdhc_set_ios_common(priv, &plat->mmc); 1648 return esdhc_set_ios_common(priv, &plat->mmc);
1649 } 1649 }
1650 1650
1651 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 1651 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1652 static void fsl_esdhc_set_enhanced_strobe(struct udevice *dev) 1652 static void fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1653 { 1653 {
1654 struct fsl_esdhc_priv *priv = dev_get_priv(dev); 1654 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1655 struct fsl_esdhc *regs = priv->esdhc_regs; 1655 struct fsl_esdhc *regs = priv->esdhc_regs;
1656 u32 m; 1656 u32 m;
1657 1657
1658 m = readl(&regs->mixctrl); 1658 m = readl(&regs->mixctrl);
1659 m |= MIX_CTRL_HS400_ES; 1659 m |= MIX_CTRL_HS400_ES;
1660 writel(m, &regs->mixctrl); 1660 writel(m, &regs->mixctrl);
1661 } 1661 }
1662 #endif 1662 #endif
1663 1663
1664 static const struct dm_mmc_ops fsl_esdhc_ops = { 1664 static const struct dm_mmc_ops fsl_esdhc_ops = {
1665 .get_cd = fsl_esdhc_get_cd, 1665 .get_cd = fsl_esdhc_get_cd,
1666 .send_cmd = fsl_esdhc_send_cmd, 1666 .send_cmd = fsl_esdhc_send_cmd,
1667 .set_ios = fsl_esdhc_set_ios, 1667 .set_ios = fsl_esdhc_set_ios,
1668 #ifdef MMC_SUPPORTS_TUNING 1668 #ifdef MMC_SUPPORTS_TUNING
1669 .execute_tuning = fsl_esdhc_execute_tuning, 1669 .execute_tuning = fsl_esdhc_execute_tuning,
1670 #endif 1670 #endif
1671 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 1671 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1672 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe, 1672 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1673 #endif 1673 #endif
1674 }; 1674 };
1675 #endif 1675 #endif
1676 1676
1677 static struct esdhc_soc_data usdhc_imx7d_data = { 1677 static struct esdhc_soc_data usdhc_imx7d_data = {
1678 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1678 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1679 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 1679 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1680 | ESDHC_FLAG_HS400, 1680 | ESDHC_FLAG_HS400,
1681 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | 1681 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1682 MMC_MODE_HS_52MHz | MMC_MODE_HS, 1682 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1683 }; 1683 };
1684 1684
1685 static struct esdhc_soc_data usdhc_imx8qm_data = { 1685 static struct esdhc_soc_data usdhc_imx8x_imx8m_data = {
1686 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 1686 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1687 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 1687 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1688 | ESDHC_FLAG_HS400 |ESDHC_FLAG_HS400_ES, 1688 | ESDHC_FLAG_HS400 |ESDHC_FLAG_HS400_ES,
1689 .caps = UHS_CAPS | MMC_MODE_HS400 | MMC_MODE_HS400_ES | 1689 .caps = UHS_CAPS | MMC_MODE_HS400 | MMC_MODE_HS400_ES |
1690 MMC_MODE_HS200 | MMC_MODE_DDR_52MHz | 1690 MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1691 MMC_MODE_HS_52MHz | MMC_MODE_HS, 1691 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1692 }; 1692 };
1693 1693
1694 static const struct udevice_id fsl_esdhc_ids[] = { 1694 static const struct udevice_id fsl_esdhc_ids[] = {
1695 { .compatible = "fsl,imx53-esdhc", }, 1695 { .compatible = "fsl,imx53-esdhc", },
1696 { .compatible = "fsl,imx6ul-usdhc", }, 1696 { .compatible = "fsl,imx6ul-usdhc", },
1697 { .compatible = "fsl,imx6sx-usdhc", }, 1697 { .compatible = "fsl,imx6sx-usdhc", },
1698 { .compatible = "fsl,imx6sl-usdhc", }, 1698 { .compatible = "fsl,imx6sl-usdhc", },
1699 { .compatible = "fsl,imx6q-usdhc", }, 1699 { .compatible = "fsl,imx6q-usdhc", },
1700 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, 1700 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1701 { .compatible = "fsl,imx7ulp-usdhc", }, 1701 { .compatible = "fsl,imx7ulp-usdhc", },
1702 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, 1702 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8x_imx8m_data,},
1703 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8x_imx8m_data,},
1704 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8x_imx8m_data,},
1703 { .compatible = "fsl,esdhc", }, 1705 { .compatible = "fsl,esdhc", },
1704 { /* sentinel */ } 1706 { /* sentinel */ }
1705 }; 1707 };
1706 1708
1707 #if CONFIG_IS_ENABLED(BLK) 1709 #if CONFIG_IS_ENABLED(BLK)
1708 static int fsl_esdhc_bind(struct udevice *dev) 1710 static int fsl_esdhc_bind(struct udevice *dev)
1709 { 1711 {
1710 struct fsl_esdhc_plat *plat = dev_get_platdata(dev); 1712 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1711 1713
1712 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1714 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1713 } 1715 }
1714 #endif 1716 #endif
1715 1717
1716 U_BOOT_DRIVER(fsl_esdhc) = { 1718 U_BOOT_DRIVER(fsl_esdhc) = {
1717 .name = "fsl-esdhc-mmc", 1719 .name = "fsl-esdhc-mmc",
1718 .id = UCLASS_MMC, 1720 .id = UCLASS_MMC,
1719 .of_match = fsl_esdhc_ids, 1721 .of_match = fsl_esdhc_ids,
1720 .ops = &fsl_esdhc_ops, 1722 .ops = &fsl_esdhc_ops,
1721 #if CONFIG_IS_ENABLED(BLK) 1723 #if CONFIG_IS_ENABLED(BLK)
1722 .bind = fsl_esdhc_bind, 1724 .bind = fsl_esdhc_bind,
1723 #endif 1725 #endif
1724 .probe = fsl_esdhc_probe, 1726 .probe = fsl_esdhc_probe,
1725 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), 1727 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1726 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), 1728 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1727 }; 1729 };
1728 #endif 1730 #endif
1729 1731