Eric Lee / smarc-uboot

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Commit 52aaddd6f415397bb2eae0d68a8cc1c5c4a98bb3

Authored by Jagan Teki
Committed by Stefano Babic
1 parent 539b1e228f
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

i.MX6: engicam: Add imx6q/imx6ul boards for existing boards 

Add new board names for existing board support
imx6q - icore and icore_rqs boards
imx6ul - geam6ul and isiot boards

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Showing 40 changed files with 469 additions and 691 deletions Side-by-side Diff

arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ 52aaddd
... ... @@ -205,8 +205,8 @@
205 205 config TARGET_MX6QARM2
206 206 bool "mx6qarm2"
207 207  
208   -config TARGET_MX6Q_ICORE
209   - bool "Support Engicam i.Core"
  208 +config TARGET_MX6Q_ENGICAM
  209 + bool "Support Engicam i.Core(RQS)"
210 210 select BOARD_LATE_INIT
211 211 select MX6QDL
212 212 select OF_CONTROL
... ... @@ -224,25 +224,6 @@
224 224 select SPL_SEPARATE_BSS if SPL
225 225 select SPL_PINCTRL if SPL
226 226  
227   -config TARGET_MX6Q_ICORE_RQS
228   - bool "Support Engicam i.Core RQS"
229   - select BOARD_LATE_INIT
230   - select MX6QDL
231   - select OF_CONTROL
232   - select SPL_OF_LIBFDT
233   - select DM
234   - select DM_ETH
235   - select DM_GPIO
236   - select DM_I2C
237   - select DM_MMC
238   - select DM_THERMAL
239   - select SUPPORT_SPL
240   - select SPL_LOAD_FIT
241   - select SPL_DM if SPL
242   - select SPL_OF_CONTROL if SPL
243   - select SPL_SEPARATE_BSS if SPL
244   - select SPL_PINCTRL if SPL
245   -
246 227 config TARGET_MX6SABREAUTO
247 228 bool "mx6sabreauto"
248 229 select MX6QDL
... ... @@ -304,8 +285,8 @@
304 285 select DM_THERMAL
305 286 select SUPPORT_SPL
306 287  
307   -config TARGET_MX6UL_GEAM
308   - bool "Support Engicam GEAM6UL"
  288 +config TARGET_MX6UL_ENGICAM
  289 + bool "Support Engicam GEAM6UL/Is.IoT"
309 290 select BOARD_LATE_INIT
310 291 select MX6UL
311 292 select OF_CONTROL
... ... @@ -321,23 +302,6 @@
321 302 select SPL_SEPARATE_BSS if SPL
322 303 select SPL_PINCTRL if SPL
323 304  
324   -config TARGET_MX6UL_ISIOT
325   - bool "Support Engicam Is.IoT MX6UL"
326   - select BOARD_LATE_INIT
327   - select MX6UL
328   - select OF_CONTROL
329   - select DM
330   - select DM_ETH
331   - select DM_GPIO
332   - select DM_I2C
333   - select DM_MMC
334   - select DM_THERMAL
335   - select SUPPORT_SPL
336   - select SPL_DM if SPL
337   - select SPL_OF_CONTROL if SPL
338   - select SPL_SEPARATE_BSS if SPL
339   - select SPL_PINCTRL if SPL
340   -
341 305 config TARGET_MX6ULL_14X14_EVK
342 306 bool "Support mx6ull_14x14_evk"
343 307 select BOARD_LATE_INIT
... ... @@ -474,10 +438,8 @@
474 438 source "board/dhelectronics/dh_imx6/Kconfig"
475 439 source "board/el/el6x/Kconfig"
476 440 source "board/embest/mx6boards/Kconfig"
477   -source "board/engicam/geam6ul/Kconfig"
478   -source "board/engicam/icorem6/Kconfig"
479   -source "board/engicam/icorem6_rqs/Kconfig"
480   -source "board/engicam/isiotmx6ul/Kconfig"
  441 +source "board/engicam/imx6q/Kconfig"
  442 +source "board/engicam/imx6ul/Kconfig"
481 443 source "board/freescale/mx6qarm2/Kconfig"
482 444 source "board/freescale/mx6sabreauto/Kconfig"
483 445 source "board/freescale/mx6sabresd/Kconfig"
board/engicam/common/board.c
Diff comments   View file @ 52aaddd
... ... @@ -49,7 +49,7 @@
49 49 } else if (!strcmp(cmp_dtb, "imx6ul-geam-kit"))
50 50 env_set("fdt_file", "imx6ul-geam-kit.dtb");
51 51 else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc"))
52   - env_set("fdt_file", "imx6ul-isiot-mmc.dtb");
  52 + env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
53 53 else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
54 54 env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
55 55 else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
board/engicam/common/spl.c
Diff comments   View file @ 52aaddd
... ... @@ -55,6 +55,32 @@
55 55 }
56 56 #endif
57 57  
  58 +#ifdef CONFIG_ENV_IS_IN_MMC
  59 +void board_boot_order(u32 *spl_boot_list)
  60 +{
  61 + u32 bmode = imx6_src_get_boot_mode();
  62 + u8 boot_dev = BOOT_DEVICE_MMC1;
  63 +
  64 + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
  65 + case IMX6_BMODE_SD:
  66 + case IMX6_BMODE_ESD:
  67 + /* SD/eSD - BOOT_DEVICE_MMC1 */
  68 + break;
  69 + case IMX6_BMODE_MMC:
  70 + case IMX6_BMODE_EMMC:
  71 + /* MMC/eMMC */
  72 + boot_dev = BOOT_DEVICE_MMC2;
  73 + break;
  74 + default:
  75 + /* Default - BOOT_DEVICE_MMC1 */
  76 + printf("Wrong board boot order\n");
  77 + break;
  78 + }
  79 +
  80 + spl_boot_list[0] = boot_dev;
  81 +}
  82 +#endif
  83 +
58 84 #ifdef CONFIG_SPL_OS_BOOT
59 85 int spl_start_uboot(void)
60 86 {
board/engicam/geam6ul/Kconfig
View file @ 52aaddd
1   -if TARGET_MX6UL_GEAM
2   -
3   -config SYS_BOARD
4   - default "geam6ul"
5   -
6   -config SYS_VENDOR
7   - default "engicam"
8   -
9   -config SYS_CONFIG_NAME
10   - default "imx6-engicam"
11   -
12   -endif
board/engicam/geam6ul/MAINTAINERS
View file @ 52aaddd
1   -GEAM6UL BOARD
2   -M: Jagan Teki <jagan@amarulasolutions.com>
3   -S: Maintained
4   -F: board/engicam/geam6ul
5   -F: include/configs/imx6-engicam.h
6   -F: configs/imx6ul_geam_mmc_defconfig
7   -F: configs/imx6ul_geam_nand_defconfig
8   -F: arch/arm/dts/imx6ul-geam-kit.dts
board/engicam/geam6ul/Makefile
View file @ 52aaddd
1   -# Copyright (C) 2016 Amarula Solutions B.V.
2   -#
3   -# SPDX-License-Identifier: GPL-2.0+
4   -#
5   -
6   -obj-y := geam6ul.o
board/engicam/geam6ul/README
View file @ 52aaddd
1   -How to use U-Boot on Engicam GEAM6UL Starter Kit:
2   --------------------------------------------------
3   -
4   -- Configure U-Boot for Engicam GEAM6UL:
5   -
6   -$ make mrproper
7   -$ make imx6ul_geam_mmc_defconfig
8   -$ make
9   -
10   -This will generate the SPL image called SPL and the u-boot-dtb.img.
11   -
12   -- Flash the SPL image into the micro SD card:
13   -
14   -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
15   -
16   -- Flash the u-boot-dtb.img image into the micro SD card:
17   -
18   -sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
19   -
20   -- Jumper settings:
21   -
22   -MMC Boot: JM3 Closed
23   -
24   -- Connect the Serial cable between the Starter Kit and the PC for the console.
25   -(J28 is the Linux Serial console connector)
26   -
27   -- Insert the micro SD card in the board, power it up and U-Boot messages should
28   -come up.
board/engicam/geam6ul/geam6ul.c
View file @ 52aaddd
1   -/*
2   - * Copyright (C) 2016 Amarula Solutions B.V.
3   - * Copyright (C) 2016 Engicam S.r.l.
4   - * Author: Jagan Teki <jagan@amarulasolutions.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -
11   -#include <asm/io.h>
12   -#include <asm/gpio.h>
13   -#include <linux/sizes.h>
14   -
15   -#include <asm/arch/clock.h>
16   -#include <asm/arch/crm_regs.h>
17   -#include <asm/arch/iomux.h>
18   -#include <asm/arch/mx6-pins.h>
19   -#include <asm/arch/sys_proto.h>
20   -#include <asm/mach-imx/iomux-v3.h>
21   -
22   -#include "../common/board.h"
23   -
24   -DECLARE_GLOBAL_DATA_PTR;
25   -
26   -#ifdef CONFIG_NAND_MXS
27   -
28   -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
29   -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
30   - PAD_CTL_SRE_FAST)
31   -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
32   -
33   -static iomux_v3_cfg_t const nand_pads[] = {
34   - IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
35   - IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
36   - IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
37   - IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
38   - IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
39   - IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
40   - IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
41   - IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
42   - IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43   - IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44   - IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45   - IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
46   - IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
47   - IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
48   - IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
49   -};
50   -
51   -void setup_gpmi_nand(void)
52   -{
53   - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
54   -
55   - /* config gpmi nand iomux */
56   - SETUP_IOMUX_PADS(nand_pads);
57   -
58   - clrbits_le32(&mxc_ccm->CCGR4,
59   - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
60   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
61   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
62   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
63   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
64   -
65   - /*
66   - * config gpmi and bch clock to 100 MHz
67   - * bch/gpmi select PLL2 PFD2 400M
68   - * 100M = 400M / 4
69   - */
70   - clrbits_le32(&mxc_ccm->cscmr1,
71   - MXC_CCM_CSCMR1_BCH_CLK_SEL |
72   - MXC_CCM_CSCMR1_GPMI_CLK_SEL);
73   - clrsetbits_le32(&mxc_ccm->cscdr1,
74   - MXC_CCM_CSCDR1_BCH_PODF_MASK |
75   - MXC_CCM_CSCDR1_GPMI_PODF_MASK,
76   - (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
77   - (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
78   -
79   - /* enable gpmi and bch clock gating */
80   - setbits_le32(&mxc_ccm->CCGR4,
81   - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
82   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
83   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
84   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
85   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
86   -
87   - /* enable apbh clock gating */
88   - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
89   -}
90   -#endif /* CONFIG_NAND_MXS */
board/engicam/icorem6/Kconfig
View file @ 52aaddd
1   -if TARGET_MX6Q_ICORE
2   -
3   -config SYS_BOARD
4   - default "icorem6"
5   -
6   -config SYS_VENDOR
7   - default "engicam"
8   -
9   -config SYS_CONFIG_NAME
10   - default "imx6-engicam"
11   -
12   -endif
board/engicam/icorem6/MAINTAINERS
View file @ 52aaddd
1   -ICOREM6QDL BOARD
2   -M: Jagan Teki <jagan@amarulasolutions.com>
3   -S: Maintained
4   -F: board/engicam/icorem6
5   -F: include/configs/imx6-engicam.h
6   -F: configs/imx6qdl_icore_mmc_defconfig
7   -F: configs/imx6qdl_icore_nand_defconfig
8   -F: arch/arm/dts/imx6qdl-icore.dtsi
9   -F: arch/arm/dts/imx6q-icore.dts
10   -F: arch/arm/dts/imx6dl-icore.dts
board/engicam/icorem6/Makefile
View file @ 52aaddd
1   -# Copyright (C) 2016 Amarula Solutions B.V.
2   -#
3   -# SPDX-License-Identifier: GPL-2.0+
4   -#
5   -
6   -obj-y := icorem6.o
board/engicam/icorem6/README
View file @ 52aaddd
1   -How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
2   ------------------------------------------------------------------------------
3   -
4   -$ make mrproper
5   -
6   -- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
7   -$ make imx6qdl_icore_mmc_defconfig
8   -
9   -- Build U-Boot
10   -$ make
11   -
12   -This will generate the SPL image called SPL and the u-boot-dtb.img.
13   -
14   -- Flash the SPL image into the micro SD card:
15   -
16   -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
17   -
18   -- Flash the u-boot-dtb.img image into the micro SD card:
19   -
20   -sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
21   -
22   -- Jumper settings:
23   -
24   -MMC Boot: JM3 Closed
25   -
26   -- Connect the Serial cable between the Starter Kit and the PC for the console.
27   -(J28 is the Linux Serial console connector)
28   -
29   -- Insert the micro SD card in the board, power it up and U-Boot messages should
30   -come up.
board/engicam/icorem6/icorem6.c
View file @ 52aaddd
1   -/*
2   - * Copyright (C) 2016 Amarula Solutions B.V.
3   - * Copyright (C) 2016 Engicam S.r.l.
4   - * Author: Jagan Teki <jagan@amarulasolutions.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -
11   -#include <asm/io.h>
12   -#include <asm/gpio.h>
13   -#include <linux/sizes.h>
14   -
15   -#include <asm/arch/clock.h>
16   -#include <asm/arch/crm_regs.h>
17   -#include <asm/arch/iomux.h>
18   -#include <asm/arch/mx6-pins.h>
19   -#include <asm/arch/sys_proto.h>
20   -#include <asm/mach-imx/iomux-v3.h>
21   -#include <asm/mach-imx/video.h>
22   -
23   -#include "../common/board.h"
24   -
25   -DECLARE_GLOBAL_DATA_PTR;
26   -
27   -#ifdef CONFIG_NAND_MXS
28   -
29   -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
30   -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
31   - PAD_CTL_SRE_FAST)
32   -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
33   -
34   -iomux_v3_cfg_t gpmi_pads[] = {
35   - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
36   - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
37   - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
38   - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
39   - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
40   - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
41   - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
42   - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43   - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44   - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45   - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
46   - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
47   - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
48   - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
49   - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
50   -};
51   -
52   -void setup_gpmi_nand(void)
53   -{
54   - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
55   -
56   - /* config gpmi nand iomux */
57   - SETUP_IOMUX_PADS(gpmi_pads);
58   -
59   - /* gate ENFC_CLK_ROOT clock first,before clk source switch */
60   - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
61   -
62   - /* config gpmi and bch clock to 100 MHz */
63   - clrsetbits_le32(&mxc_ccm->cs2cdr,
64   - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
65   - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
66   - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
67   - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
68   - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
69   - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
70   -
71   - /* enable ENFC_CLK_ROOT clock */
72   - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
73   -
74   - /* enable gpmi and bch clock gating */
75   - setbits_le32(&mxc_ccm->CCGR4,
76   - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
77   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
78   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
79   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
80   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
81   -
82   - /* enable apbh clock gating */
83   - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
84   -}
85   -#endif
86   -
87   -#if defined(CONFIG_VIDEO_IPUV3)
88   -static iomux_v3_cfg_t const rgb_pads[] = {
89   - IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
90   - IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
91   - IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
92   - IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
93   - IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
94   - IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
95   - IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
96   - IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
97   - IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
98   - IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
99   - IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
100   - IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
101   - IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
102   - IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
103   - IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
104   - IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
105   - IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
106   - IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
107   - IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
108   - IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
109   - IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
110   - IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
111   -};
112   -
113   -static void enable_rgb(struct display_info_t const *dev)
114   -{
115   - SETUP_IOMUX_PADS(rgb_pads);
116   -}
117   -
118   -struct display_info_t const displays[] = {
119   - {
120   - .bus = -1,
121   - .addr = 0,
122   - .pixfmt = IPU_PIX_FMT_RGB666,
123   - .detect = NULL,
124   - .enable = enable_rgb,
125   - .mode = {
126   - .name = "Amp-WD",
127   - .refresh = 60,
128   - .xres = 800,
129   - .yres = 480,
130   - .pixclock = 30000,
131   - .left_margin = 30,
132   - .right_margin = 30,
133   - .upper_margin = 5,
134   - .lower_margin = 5,
135   - .hsync_len = 64,
136   - .vsync_len = 20,
137   - .sync = FB_SYNC_EXT,
138   - .vmode = FB_VMODE_NONINTERLACED
139   - }
140   - },
141   -};
142   -
143   -size_t display_count = ARRAY_SIZE(displays);
144   -
145   -void setup_display(void)
146   -{
147   - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
148   - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
149   - int reg;
150   -
151   - enable_ipu_clock();
152   -
153   - /* Turn on LDB0,IPU,IPU DI0 clocks */
154   - reg = __raw_readl(&mxc_ccm->CCGR3);
155   - reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
156   - writel(reg, &mxc_ccm->CCGR3);
157   -
158   - /* set LDB0, LDB1 clk select to 011/011 */
159   - reg = readl(&mxc_ccm->cs2cdr);
160   - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
161   - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
162   - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
163   - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
164   - writel(reg, &mxc_ccm->cs2cdr);
165   -
166   - reg = readl(&mxc_ccm->cscmr2);
167   - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
168   - writel(reg, &mxc_ccm->cscmr2);
169   -
170   - reg = readl(&mxc_ccm->chsccdr);
171   - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
172   - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
173   - writel(reg, &mxc_ccm->chsccdr);
174   -
175   - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
176   - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
177   - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
178   - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
179   - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
180   - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
181   - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
182   - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
183   - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
184   - writel(reg, &iomux->gpr[2]);
185   -
186   - reg = readl(&iomux->gpr[3]);
187   - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
188   - (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
189   - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
190   - writel(reg, &iomux->gpr[3]);
191   -}
192   -#endif /* CONFIG_VIDEO_IPUV3 */
board/engicam/icorem6_rqs/Kconfig
View file @ 52aaddd
1   -if TARGET_MX6Q_ICORE_RQS
2   -
3   -config SYS_BOARD
4   - default "icorem6_rqs"
5   -
6   -config SYS_VENDOR
7   - default "engicam"
8   -
9   -config SYS_CONFIG_NAME
10   - default "imx6-engicam"
11   -
12   -endif
board/engicam/icorem6_rqs/MAINTAINERS
View file @ 52aaddd
1   -ICOREM6QDL_RQS BOARD
2   -M: Jagan Teki <jagan@amarulasolutions.com>
3   -S: Maintained
4   -F: board/engicam/icorem6_rqs
5   -F: include/configs/imx6-engicam.h
6   -F: configs/imx6qdl_icore_rqs_defconfig
7   -F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
8   -F: arch/arm/dts/imx6q-icore-rqs.dts
9   -F: arch/arm/dts/imx6dl-icore-rqs.dts
board/engicam/icorem6_rqs/Makefile
View file @ 52aaddd
1   -# Copyright (C) 2016 Amarula Solutions B.V.
2   -#
3   -# SPDX-License-Identifier: GPL-2.0+
4   -#
5   -
6   -obj-y := icorem6_rqs.o
board/engicam/icorem6_rqs/README
View file @ 52aaddd
1   -How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit:
2   -----------------------------------------------------------------------------------
3   -
4   -$ make mrproper
5   -
6   -- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
7   -$ make imx6qdl_icore_rqs_defconfig
8   -
9   -- Build U-Boot
10   -$ make
11   -
12   -This will generate the SPL image called SPL and the u-boot-dtb.img.
13   -
14   -- Flash the SPL image into the micro SD card:
15   -
16   -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
17   -
18   -- Flash the u-boot-dtb.img image into the micro SD card:
19   -
20   -sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
21   -
22   -- Jumper settings:
23   -
24   -MMC Boot: JM3 Closed
25   -
26   -- Connect the Serial cable between the Starter Kit and the PC for the console.
27   -(J28 is the Linux Serial console connector)
28   -
29   -- Insert the micro SD card in the board, power it up and U-Boot messages should
30   -come up.
board/engicam/imx6q/Kconfig
Diff comments   View file @ 52aaddd
  1 +if TARGET_MX6Q_ENGICAM
  2 +
  3 +config SYS_BOARD
  4 + default "imx6q"
  5 +
  6 +config SYS_VENDOR
  7 + default "engicam"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx6-engicam"
  11 +
  12 +endif
board/engicam/imx6q/MAINTAINERS
Diff comments   View file @ 52aaddd
  1 +MX6Q_ENGICAM BOARD
  2 +M: Jagan Teki <jagan@amarulasolutions.com>
  3 +S: Maintained
  4 +F: board/engicam/imx6q
  5 +F: include/configs/imx6-engicam.h
  6 +F: configs/imx6qdl_icore_mmc_defconfig
  7 +F: configs/imx6qdl_icore_nand_defconfig
  8 +F: configs/imx6qdl_icore_rqs_defconfig
  9 +F: arch/arm/dts/imx6qdl-icore.dtsi
  10 +F: arch/arm/dts/imx6q-icore.dts
  11 +F: arch/arm/dts/imx6dl-icore.dts
  12 +F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
  13 +F: arch/arm/dts/imx6q-icore-rqs.dts
  14 +F: arch/arm/dts/imx6dl-icore-rqs.dts
board/engicam/imx6q/Makefile
Diff comments   View file @ 52aaddd
  1 +# Copyright (C) 2016 Amarula Solutions B.V.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := imx6q.o
board/engicam/imx6q/README
Diff comments   View file @ 52aaddd
  1 +Hsow to use U-Boot on Engicam i.CoreM6 (RQS) Solo/DualLite/Quad/Dual Starter Kit:
  2 +--------------------------------------------------------------------------------
  3 +
  4 +$ make mrproper
  5 +
  6 +- Configure U-Boot for Engicam i.CoreM6 Quad/Duali/Solo/DualLite:
  7 +$ make imx6qdl_icore_mmc_defconfig
  8 +
  9 +- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Duali/Solo/DualLite:
  10 +$ make imx6qdl_icore_rqs_defconfig
  11 +
  12 +- Build U-Boot
  13 +$ make
  14 +
  15 +This will generate the SPL image called SPL and the u-boot-dtb.img.
  16 +
  17 +- Flash the SPL image into the micro SD card:
  18 +
  19 +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
  20 +
  21 +- Flash the u-boot-dtb.img image into the micro SD card:
  22 +
  23 +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
  24 +
  25 +- Jumper settings:
  26 +
  27 +MMC Boot: JM3 Closed
  28 +
  29 +- Connect the Serial cable between the Starter Kit and the PC for the console.
  30 +(J28 is the Linux Serial console connector)
  31 +
  32 +- Insert the micro SD card in the board, power it up and U-Boot messages should
  33 +come up.
board/engicam/imx6q/imx6q.c
Diff comments   View file @ 52aaddd
  1 +/*
  2 + * Copyright (C) 2016 Amarula Solutions B.V.
  3 + * Copyright (C) 2016 Engicam S.r.l.
  4 + * Author: Jagan Teki <jagan@amarulasolutions.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +
  11 +#include <asm/io.h>
  12 +#include <asm/gpio.h>
  13 +#include <linux/sizes.h>
  14 +
  15 +#include <asm/arch/clock.h>
  16 +#include <asm/arch/crm_regs.h>
  17 +#include <asm/arch/iomux.h>
  18 +#include <asm/arch/mx6-pins.h>
  19 +#include <asm/arch/sys_proto.h>
  20 +#include <asm/mach-imx/iomux-v3.h>
  21 +#include <asm/mach-imx/video.h>
  22 +
  23 +#include "../common/board.h"
  24 +
  25 +DECLARE_GLOBAL_DATA_PTR;
  26 +
  27 +#ifdef CONFIG_NAND_MXS
  28 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  29 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  30 + PAD_CTL_SRE_FAST)
  31 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  32 +
  33 +static iomux_v3_cfg_t gpmi_pads[] = {
  34 + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  35 + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  36 + IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  37 + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
  38 + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  39 + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  40 + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  41 + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  42 + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  43 + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  44 + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  45 + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  46 + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  47 + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  48 + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  49 +};
  50 +
  51 +void setup_gpmi_nand(void)
  52 +{
  53 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  54 +
  55 + /* config gpmi nand iomux */
  56 + SETUP_IOMUX_PADS(gpmi_pads);
  57 +
  58 + /* gate ENFC_CLK_ROOT clock first,before clk source switch */
  59 + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  60 +
  61 + /* config gpmi and bch clock to 100 MHz */
  62 + clrsetbits_le32(&mxc_ccm->cs2cdr,
  63 + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  64 + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  65 + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  66 + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  67 + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  68 + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  69 +
  70 + /* enable ENFC_CLK_ROOT clock */
  71 + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  72 +
  73 + /* enable gpmi and bch clock gating */
  74 + setbits_le32(&mxc_ccm->CCGR4,
  75 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  76 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  77 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  78 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  79 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  80 +
  81 + /* enable apbh clock gating */
  82 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  83 +}
  84 +#endif
  85 +
  86 +#if defined(CONFIG_VIDEO_IPUV3)
  87 +static iomux_v3_cfg_t const rgb_pads[] = {
  88 + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
  89 + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
  90 + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
  91 + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
  92 + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
  93 + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
  94 + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
  95 + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
  96 + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
  97 + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
  98 + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
  99 + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
  100 + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
  101 + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
  102 + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
  103 + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
  104 + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
  105 + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
  106 + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
  107 + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
  108 + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
  109 + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
  110 +};
  111 +
  112 +static void enable_rgb(struct display_info_t const *dev)
  113 +{
  114 + SETUP_IOMUX_PADS(rgb_pads);
  115 +}
  116 +
  117 +struct display_info_t const displays[] = {
  118 + {
  119 + .bus = -1,
  120 + .addr = 0,
  121 + .pixfmt = IPU_PIX_FMT_RGB666,
  122 + .detect = NULL,
  123 + .enable = enable_rgb,
  124 + .mode = {
  125 + .name = "Amp-WD",
  126 + .refresh = 60,
  127 + .xres = 800,
  128 + .yres = 480,
  129 + .pixclock = 30000,
  130 + .left_margin = 30,
  131 + .right_margin = 30,
  132 + .upper_margin = 5,
  133 + .lower_margin = 5,
  134 + .hsync_len = 64,
  135 + .vsync_len = 20,
  136 + .sync = FB_SYNC_EXT,
  137 + .vmode = FB_VMODE_NONINTERLACED
  138 + }
  139 + },
  140 +};
  141 +
  142 +size_t display_count = ARRAY_SIZE(displays);
  143 +
  144 +void setup_display(void)
  145 +{
  146 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  147 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  148 + int reg;
  149 +
  150 + enable_ipu_clock();
  151 +
  152 + /* Turn on LDB0,IPU,IPU DI0 clocks */
  153 + reg = __raw_readl(&mxc_ccm->CCGR3);
  154 + reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
  155 + writel(reg, &mxc_ccm->CCGR3);
  156 +
  157 + /* set LDB0, LDB1 clk select to 011/011 */
  158 + reg = readl(&mxc_ccm->cs2cdr);
  159 + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  160 + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  161 + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  162 + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  163 + writel(reg, &mxc_ccm->cs2cdr);
  164 +
  165 + reg = readl(&mxc_ccm->cscmr2);
  166 + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  167 + writel(reg, &mxc_ccm->cscmr2);
  168 +
  169 + reg = readl(&mxc_ccm->chsccdr);
  170 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
  171 + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  172 + writel(reg, &mxc_ccm->chsccdr);
  173 +
  174 + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  175 + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  176 + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  177 + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  178 + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  179 + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  180 + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  181 + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
  182 + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  183 + writel(reg, &iomux->gpr[2]);
  184 +
  185 + reg = readl(&iomux->gpr[3]);
  186 + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
  187 + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  188 + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  189 + writel(reg, &iomux->gpr[3]);
  190 +}
  191 +#endif /* CONFIG_VIDEO_IPUV3 */
  192 +
  193 +#ifdef CONFIG_ENV_IS_IN_MMC
  194 +int board_mmc_get_env_dev(int devno)
  195 +{
  196 + return devno - 1;
  197 +}
  198 +#endif
board/engicam/imx6ul/Kconfig
Diff comments   View file @ 52aaddd
  1 +if TARGET_MX6UL_ENGICAM
  2 +
  3 +config SYS_BOARD
  4 + default "imx6ul"
  5 +
  6 +config SYS_VENDOR
  7 + default "engicam"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx6-engicam"
  11 +
  12 +endif
board/engicam/imx6ul/MAINTAINERS
Diff comments   View file @ 52aaddd
  1 +MX6UL_ENGICAM BOARD
  2 +M: Jagan Teki <jagan@amarulasolutions.com>
  3 +S: Maintained
  4 +F: board/engicam/imx6ul
  5 +F: include/configs/imx6-engicam.h
  6 +F: configs/imx6ul_geam_mmc_defconfig
  7 +F: configs/imx6ul_geam_nand_defconfig
  8 +F: configs/imx6ul_isiot_emmc_defconfig
  9 +F: configs/imx6ul_isiot_mmc_defconfig
  10 +F: configs/imx6ul_isiot_nand_defconfig
  11 +F: arch/arm/dts/imx6ul-geam-kit.dts
  12 +F: arch/arm/dts/imx6ul-isiot.dtsi
  13 +F: arch/arm/dts/imx6ul-isiot-mmc.dts
  14 +F: arch/arm/dts/imx6ul-isiot-emmc.dts
  15 +F: arch/arm/dts/imx6ul-isiot-nand.dts
board/engicam/imx6ul/Makefile
Diff comments   View file @ 52aaddd
  1 +# Copyright (C) 2016 Amarula Solutions B.V.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := imx6ul.o
board/engicam/imx6ul/README
Diff comments   View file @ 52aaddd
  1 +Hsow to use U-Boot on Engicam GEAM6UL and Is.IoT MX6UL Starter Kit:
  2 +-------------------------------------------------------------------
  3 +
  4 +$ make mrproper
  5 +
  6 +- Configure U-Boot for Engicam GEAM6UL:
  7 +$ make imx6ul_geam_mmc_defconfig
  8 +
  9 +- Configure U-Boot for Engicam Is.IoT MX6UL:
  10 +$ make imx6ul_isiot_mmc_defconfig
  11 +
  12 +- Build U-Boot
  13 +$ make
  14 +
  15 +This will generate the SPL image called SPL and the u-boot-dtb.img.
  16 +
  17 +- Flash the SPL image into the micro SD card:
  18 +
  19 +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
  20 +
  21 +- Flash the u-boot-dtb.img image into the micro SD card:
  22 +
  23 +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
  24 +
  25 +- Jumper settings:
  26 +
  27 +MMC Boot: JM3 Closed
  28 +
  29 +- Connect the Serial cable between the Starter Kit and the PC for the console.
  30 +(J28 is the Linux Serial console connector)
  31 +
  32 +- Insert the micro SD card in the board, power it up and U-Boot messages should
  33 +come up.
board/engicam/imx6ul/imx6ul.c
Diff comments   View file @ 52aaddd
  1 +/*
  2 + * Copyright (C) 2016 Amarula Solutions B.V.
  3 + * Copyright (C) 2016 Engicam S.r.l.
  4 + * Author: Jagan Teki <jagan@amarulasolutions.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <mmc.h>
  11 +
  12 +#include <asm/io.h>
  13 +#include <asm/gpio.h>
  14 +#include <linux/sizes.h>
  15 +
  16 +#include <asm/arch/clock.h>
  17 +#include <asm/arch/crm_regs.h>
  18 +#include <asm/arch/iomux.h>
  19 +#include <asm/arch/mx6-pins.h>
  20 +#include <asm/arch/sys_proto.h>
  21 +#include <asm/mach-imx/iomux-v3.h>
  22 +
  23 +#include "../common/board.h"
  24 +
  25 +DECLARE_GLOBAL_DATA_PTR;
  26 +
  27 +#ifdef CONFIG_NAND_MXS
  28 +
  29 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  30 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  31 + PAD_CTL_SRE_FAST)
  32 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  33 +
  34 +static iomux_v3_cfg_t const nand_pads[] = {
  35 + IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  36 + IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  37 + IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  38 + IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  39 + IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  40 + IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  41 + IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  42 + IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  43 + IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  44 + IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  45 + IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  46 + IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  47 + IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  48 + IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  49 + IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  50 +};
  51 +
  52 +void setup_gpmi_nand(void)
  53 +{
  54 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  55 +
  56 + /* config gpmi nand iomux */
  57 + SETUP_IOMUX_PADS(nand_pads);
  58 +
  59 + clrbits_le32(&mxc_ccm->CCGR4,
  60 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  65 +
  66 + /*
  67 + * config gpmi and bch clock to 100 MHz
  68 + * bch/gpmi select PLL2 PFD2 400M
  69 + * 100M = 400M / 4
  70 + */
  71 + clrbits_le32(&mxc_ccm->cscmr1,
  72 + MXC_CCM_CSCMR1_BCH_CLK_SEL |
  73 + MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  74 + clrsetbits_le32(&mxc_ccm->cscdr1,
  75 + MXC_CCM_CSCDR1_BCH_PODF_MASK |
  76 + MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  77 + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  78 + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  79 +
  80 + /* enable gpmi and bch clock gating */
  81 + setbits_le32(&mxc_ccm->CCGR4,
  82 + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  83 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  84 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  85 + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  86 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  87 +
  88 + /* enable apbh clock gating */
  89 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  90 +}
  91 +#endif /* CONFIG_NAND_MXS */
  92 +
  93 +#ifdef CONFIG_ENV_IS_IN_MMC
  94 +int board_mmc_get_env_dev(int devno)
  95 +{
  96 + /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
  97 + return (devno == 0) ? 0 : 1;
  98 +}
  99 +#endif
board/engicam/isiotmx6ul/Kconfig
View file @ 52aaddd
1   -if TARGET_MX6UL_ISIOT
2   -
3   -config SYS_BOARD
4   - default "isiotmx6ul"
5   -
6   -config SYS_VENDOR
7   - default "engicam"
8   -
9   -config SYS_CONFIG_NAME
10   - default "imx6-engicam"
11   -
12   -endif
board/engicam/isiotmx6ul/MAINTAINERS
View file @ 52aaddd
1   -ISIOTMX6UL BOARD
2   -M: Jagan Teki <jagan@amarulasolutions.com>
3   -S: Maintained
4   -F: board/engicam/isiotmx6ul
5   -F: include/configs/imx6-engicam.h
6   -F: configs/imx6ul_isiot_mmc_defconfig
7   -F: configs/imx6ul_isiot_emmc_defconfig
8   -F: configs/imx6ul_isiot_nand_defconfig
9   -F: arch/arm/dts/imx6ul-isiot.dtsi
10   -F: arch/arm/dts/imx6ul-isiot-mmc.dts
11   -F: arch/arm/dts/imx6ul-isiot-emmc.dts
12   -F: arch/arm/dts/imx6ul-isiot-nand.dts
board/engicam/isiotmx6ul/Makefile
View file @ 52aaddd
1   -# Copyright (C) 2016 Amarula Solutions B.V.
2   -#
3   -# SPDX-License-Identifier: GPL-2.0+
4   -#
5   -
6   -obj-y := isiotmx6ul.o
board/engicam/isiotmx6ul/README
View file @ 52aaddd
1   -How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit:
2   ------------------------------------------------------
3   -
4   -- Configure U-Boot for Engicam Is.IoT MX6UL
5   -
6   -$ make mrproper
7   -$ make imx6ul_isiot_mmc_defconfig
8   -$ make
9   -
10   -This will generate the SPL image called SPL and the u-boot-dtb.img.
11   -
12   -- Flash the SPL image into the micro SD card:
13   -
14   -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
15   -
16   -- Flash the u-boot-dtb.img image into the micro SD card:
17   -
18   -sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
19   -
20   -- Jumper settings:
21   -
22   -MMC Boot: JM3 Closed
23   -
24   -- Connect the Serial cable between the Starter Kit and the PC for the console.
25   -(J28 is the Linux Serial console connector)
26   -
27   -- Insert the micro SD card in the board, power it up and U-Boot messages should
28   -come up.
board/engicam/isiotmx6ul/isiotmx6ul.c
View file @ 52aaddd
1   -/*
2   - * Copyright (C) 2016 Amarula Solutions B.V.
3   - * Copyright (C) 2016 Engicam S.r.l.
4   - * Author: Jagan Teki <jagan@amarulasolutions.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <mmc.h>
11   -
12   -#include <asm/io.h>
13   -#include <asm/gpio.h>
14   -#include <linux/sizes.h>
15   -
16   -#include <asm/arch/clock.h>
17   -#include <asm/arch/crm_regs.h>
18   -#include <asm/arch/iomux.h>
19   -#include <asm/arch/mx6-pins.h>
20   -#include <asm/arch/sys_proto.h>
21   -#include <asm/mach-imx/iomux-v3.h>
22   -
23   -#include "../common/board.h"
24   -
25   -DECLARE_GLOBAL_DATA_PTR;
26   -
27   -#ifdef CONFIG_NAND_MXS
28   -
29   -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
30   -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
31   - PAD_CTL_SRE_FAST)
32   -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
33   -
34   -static iomux_v3_cfg_t const nand_pads[] = {
35   - IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
36   - IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
37   - IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
38   - IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
39   - IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
40   - IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
41   - IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
42   - IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43   - IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44   - IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45   - IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
46   - IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
47   - IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
48   - IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
49   - IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
50   -};
51   -
52   -void setup_gpmi_nand(void)
53   -{
54   - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
55   -
56   - /* config gpmi nand iomux */
57   - SETUP_IOMUX_PADS(nand_pads);
58   -
59   - clrbits_le32(&mxc_ccm->CCGR4,
60   - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
61   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
62   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
63   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
64   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
65   -
66   - /*
67   - * config gpmi and bch clock to 100 MHz
68   - * bch/gpmi select PLL2 PFD2 400M
69   - * 100M = 400M / 4
70   - */
71   - clrbits_le32(&mxc_ccm->cscmr1,
72   - MXC_CCM_CSCMR1_BCH_CLK_SEL |
73   - MXC_CCM_CSCMR1_GPMI_CLK_SEL);
74   - clrsetbits_le32(&mxc_ccm->cscdr1,
75   - MXC_CCM_CSCDR1_BCH_PODF_MASK |
76   - MXC_CCM_CSCDR1_GPMI_PODF_MASK,
77   - (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
78   - (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
79   -
80   - /* enable gpmi and bch clock gating */
81   - setbits_le32(&mxc_ccm->CCGR4,
82   - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
83   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
84   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
85   - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
86   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
87   -
88   - /* enable apbh clock gating */
89   - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
90   -}
91   -#endif /* CONFIG_NAND_MXS */
92   -
93   -#ifdef CONFIG_ENV_IS_IN_MMC
94   -int board_mmc_get_env_dev(int devno)
95   -{
96   - /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
97   - return (devno == 0) ? 0 : 1;
98   -}
99   -#endif
100   -
101   -#ifdef CONFIG_SPL_BUILD
102   -#include <spl.h>
103   -
104   -#ifdef CONFIG_ENV_IS_IN_MMC
105   -void board_boot_order(u32 *spl_boot_list)
106   -{
107   - u32 bmode = imx6_src_get_boot_mode();
108   - u8 boot_dev = BOOT_DEVICE_MMC1;
109   -
110   - switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
111   - case IMX6_BMODE_SD:
112   - case IMX6_BMODE_ESD:
113   - /* SD/eSD - BOOT_DEVICE_MMC1 */
114   - break;
115   - case IMX6_BMODE_MMC:
116   - case IMX6_BMODE_EMMC:
117   - /* MMC/eMMC */
118   - boot_dev = BOOT_DEVICE_MMC2;
119   - break;
120   - default:
121   - /* Default - BOOT_DEVICE_MMC1 */
122   - printf("Wrong board boot order\n");
123   - break;
124   - }
125   -
126   - spl_boot_list[0] = boot_dev;
127   -}
128   -#endif
129   -#endif /* CONFIG_SPL_BUILD */
configs/imx6qdl_icore_mmc_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6Q_ICORE=y
  6 +CONFIG_TARGET_MX6Q_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_LIBDISK_SUPPORT=y
9 9 CONFIG_SPL_WATCHDOG_SUPPORT=y
configs/imx6qdl_icore_nand_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6Q_ICORE=y
  6 +CONFIG_TARGET_MX6Q_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_WATCHDOG_SUPPORT=y
9 9 # CONFIG_CMD_BMODE is not set
configs/imx6qdl_icore_rqs_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6Q_ICORE_RQS=y
  6 +CONFIG_TARGET_MX6Q_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_LIBDISK_SUPPORT=y
9 9 CONFIG_SPL_WATCHDOG_SUPPORT=y
configs/imx6ul_geam_mmc_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6UL_GEAM=y
  6 +CONFIG_TARGET_MX6UL_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_LIBDISK_SUPPORT=y
9 9 CONFIG_SPL_WATCHDOG_SUPPORT=y
configs/imx6ul_geam_nand_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6UL_GEAM=y
  6 +CONFIG_TARGET_MX6UL_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_WATCHDOG_SUPPORT=y
9 9 # CONFIG_CMD_BMODE is not set
configs/imx6ul_isiot_emmc_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6UL_ISIOT=y
  6 +CONFIG_TARGET_MX6UL_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_LIBDISK_SUPPORT=y
9 9 CONFIG_SPL_WATCHDOG_SUPPORT=y
configs/imx6ul_isiot_mmc_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6UL_ISIOT=y
  6 +CONFIG_TARGET_MX6UL_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_LIBDISK_SUPPORT=y
9 9 CONFIG_SPL_WATCHDOG_SUPPORT=y
configs/imx6ul_isiot_nand_defconfig
Diff comments   View file @ 52aaddd
... ... @@ -3,7 +3,7 @@
3 3 CONFIG_SPL_GPIO_SUPPORT=y
4 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
5 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
6   -CONFIG_TARGET_MX6UL_ISIOT=y
  6 +CONFIG_TARGET_MX6UL_ENGICAM=y
7 7 CONFIG_SPL_SERIAL_SUPPORT=y
8 8 CONFIG_SPL_WATCHDOG_SUPPORT=y
9 9 # CONFIG_CMD_BMODE is not set