ls102xa: etsec: Add etsec support for LS102xA

This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>

ls102xa: etsec: Add etsec support for LS102xA
This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
Alison Wang · York Sun · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent d2614ea0ff
Showing 2 changed files with 13 additions and 1 deletions Side-by-side Diff
drivers/net/tsec.c
include/tsec.h
@@ -20,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
+#include <asm/io.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -270,6 +271,9 @@
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
  
 	do {
 		uint16_t status;
@@ -366,6 +370,9 @@
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 }
  
 /* This returns the status bits of the device.	The return value
@@ -20,10 +20,14 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <fsl_mdio.h>
  
+#ifdef CONFIG_LS102XA
+#define TSEC_SIZE		0x40000
+#define TSEC_MDIO_OFFSET	0x40000
+#else
 #define TSEC_SIZE 		0x01000
 #define TSEC_MDIO_OFFSET	0x01000
+#endif
  
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
  
@@ -128,6 +132,7 @@
 #define DMACTRL_INIT_SETTINGS	0x000000c3
 #define DMACTRL_GRS		0x00000010
 #define DMACTRL_GTS		0x00000008
+#define DMACTRL_LE		0x00008000
  
 #define TSTAT_CLEAR_THALT	0x80000000
 #define RSTAT_CLEAR_RHALT	0x00800000
...	...	@@ -20,6 +20,7 @@
20	20	#include <fsl_mdio.h>
21	21	#include <asm/errno.h>
22	22	#include <asm/processor.h>
	23	+#include <asm/io.h>
23	24
24	25	DECLARE_GLOBAL_DATA_PTR;
25	26
...	...	@@ -270,6 +271,9 @@
270	271	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
271	272	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
272	273	clrbits_be32(&regs->dmactrl, DMACTRL_GRS \| DMACTRL_GTS);
	274	+#ifdef CONFIG_LS102XA
	275	+ setbits_be32(&regs->dmactrl, DMACTRL_LE);
	276	+#endif
273	277
274	278	do {
275	279	uint16_t status;
...	...	@@ -366,6 +370,9 @@
366	370	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
367	371	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
368	372	clrbits_be32(&regs->dmactrl, DMACTRL_GRS \| DMACTRL_GTS);
	373	+#ifdef CONFIG_LS102XA
	374	+ setbits_be32(&regs->dmactrl, DMACTRL_LE);
	375	+#endif
369	376	}
370	377
371	378	/* This returns the status bits of the device. The return value
...	...	@@ -20,10 +20,14 @@
20	20	#include <net.h>
21	21	#include <config.h>
22	22	#include <phy.h>
23		-#include <fsl_mdio.h>
24	23
	24	+#ifdef CONFIG_LS102XA
	25	+#define TSEC_SIZE 0x40000
	26	+#define TSEC_MDIO_OFFSET 0x40000
	27	+#else
25	28	#define TSEC_SIZE 0x01000
26	29	#define TSEC_MDIO_OFFSET 0x01000
	30	+#endif
27	31
28	32	#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
29	33
...	...	@@ -128,6 +132,7 @@
128	132	#define DMACTRL_INIT_SETTINGS 0x000000c3
129	133	#define DMACTRL_GRS 0x00000010
130	134	#define DMACTRL_GTS 0x00000008
	135	+#define DMACTRL_LE 0x00008000
131	136
132	137	#define TSTAT_CLEAR_THALT 0x80000000
133	138	#define RSTAT_CLEAR_RHALT 0x00800000