Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 52d093112a307b2dd1ae46f8bd6ba7904760ac57

Authored by Siarhei Siamashka
Committed by Hans de Goede
1 parent 0404d53f2f
Exists in v2017.01-smarct4x and in 31 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3 

The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
This can be verified by reading the value of the AHB1_APB1_CFG_REG
register via /dev/mem. It always reads as 0x3180 regardless of
the current cpufreq operating point. So this configuration should
be safe for use in U-Boot too.

PLL6 also needs to be configured before it is used as the clock
source, according to the "CCU / Programming Guidelines" section
of the Allwinner manual.

The current low AHB1 clock speed is limiting the USB transfer
speed when booting via FEL. This patch can increase the FEL USB
transfer speed from ~510 KB/s to ~950 KB/s.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Showing 2 changed files with 10 additions and 3 deletions Side-by-side Diff

arch/arm/cpu/armv7/sunxi/clock_sun6i.c
Diff comments   View file @ 52d0931
... ... @@ -34,9 +34,11 @@
34 34  
35 35 clock_set_pll1(408000000);
36 36  
37   - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
38   -
39 37 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  38 + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
  39 + ;
  40 +
  41 + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
40 42  
41 43 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
42 44 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
Diff comments   View file @ 52d0931
... ... @@ -201,6 +201,7 @@
201 201 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
202 202 #define CCM_PLL6_CTRL_K_SHIFT 4
203 203 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
  204 +#define CCM_PLL6_CTRL_LOCK (1 << 28)
204 205  
205 206 #define CCM_MIPI_PLL_CTRL_M_SHIFT 0
206 207 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
... ... @@ -219,7 +220,11 @@
219 220 #define CCM_PLL11_CTRL_UPD (0x1 << 30)
220 221 #define CCM_PLL11_CTRL_EN (0x1 << 31)
221 222  
222   -#define AHB1_ABP1_DIV_DEFAULT 0x00002020
  223 +#if defined CONFIG_MACH_SUN8I_H3
  224 +#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
  225 +#else
  226 +#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
  227 +#endif
223 228  
224 229 #define AXI_GATE_OFFSET_DRAM 0
225 230