Eric Lee / smarc-uboot | Embedian Git Server

Commit 52f69f818c016a05fb81cfc51b42eecfb7240a6c

Authored by Vladimir Zapolskiy 2012-04-19 12:33:08 +0800

Committed by Albert ARIBAUD 2012-05-15 14:31:21 +0800

Exists in master and in 54 other branches

arm926ejs: add NXP LPC32x0 cpu series support

This change adds initial support for NXP LPC32x0 SoC series.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>

Showing 13 changed files with 985 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/arm926ejs/lpc32xx/Makefile
arch/arm/cpu/arm926ejs/lpc32xx/clk.c
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
arch/arm/cpu/arm926ejs/lpc32xx/devices.c
arch/arm/cpu/arm926ejs/lpc32xx/timer.c
arch/arm/include/asm/arch-lpc32xx/clk.h
arch/arm/include/asm/arch-lpc32xx/config.h
arch/arm/include/asm/arch-lpc32xx/cpu.h
arch/arm/include/asm/arch-lpc32xx/emc.h
arch/arm/include/asm/arch-lpc32xx/sys_proto.h
arch/arm/include/asm/arch-lpc32xx/timer.h
arch/arm/include/asm/arch-lpc32xx/uart.h
arch/arm/include/asm/arch-lpc32xx/wdt.h

arch/arm/cpu/arm926ejs/lpc32xx/Makefile

Diff comments View file @ 52f69f8

	1	+#
	2	+# (C) Copyright 2000-2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License
	10	+# as published by the Free Software Foundation; either version 2
	11	+# of the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	+# MA 02110-1301, USA.
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = $(obj)lib$(SOC).o
	27	+
	28	+COBJS = cpu.o clk.o devices.o timer.o
	29	+
	30	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	31	+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
	32	+
	33	+all: $(obj).depend $(LIB)
	34	+
	35	+$(LIB): $(OBJS)
	36	+ $(call cmd_link_o_target, $(OBJS))
	37	+
	38	+#########################################################################
	39	+
	40	+# defines $(obj).depend target
	41	+include $(SRCTREE)/rules.mk
	42	+
	43	+sinclude $(obj).depend
	44	+
	45	+#########################################################################

arch/arm/cpu/arm926ejs/lpc32xx/clk.c

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#include <common.h>
	21	+#include <div64.h>
	22	+#include <asm/arch/cpu.h>
	23	+#include <asm/arch/clk.h>
	24	+#include <asm/io.h>
	25	+
	26	+static struct clk_pm_regs clk = (struct clk_pm_regs )CLK_PM_BASE;
	27	+
	28	+unsigned int get_sys_clk_rate(void)
	29	+{
	30	+ if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
	31	+ return RTC_CLK_FREQUENCY * 397;
	32	+ else
	33	+ return OSC_CLK_FREQUENCY;
	34	+}
	35	+
	36	+unsigned int get_hclk_pll_rate(void)
	37	+{
	38	+ unsigned long long fin, fref, fcco, fout;
	39	+ u32 val, m_div, n_div, p_div;
	40	+
	41	+ /*
	42	+ * Valid frequency ranges:
	43	+ * 1 * 10^6 <= Fin <= 20 * 10^6
	44	+ * 1 * 10^6 <= Fref <= 27 * 10^6
	45	+ * 156 * 10^6 <= Fcco <= 320 * 10^6
	46	+ */
	47	+
	48	+ fref = fin = get_sys_clk_rate();
	49	+ if (fin > 20000000ULL \|\| fin < 1000000ULL)
	50	+ return 0;
	51	+
	52	+ val = readl(&clk->hclkpll_ctrl);
	53	+ m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
	54	+ n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
	55	+ if (val & CLK_HCLK_PLL_DIRECT)
	56	+ p_div = 0;
	57	+ else
	58	+ p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
	59	+ p_div = 1 << p_div;
	60	+
	61	+ if (val & CLK_HCLK_PLL_BYPASS) {
	62	+ do_div(fin, p_div);
	63	+ return fin;
	64	+ }
	65	+
	66	+ do_div(fref, n_div);
	67	+ if (fref > 27000000ULL \|\| fref < 1000000ULL)
	68	+ return 0;
	69	+
	70	+ fout = fref * m_div;
	71	+ if (val & CLK_HCLK_PLL_FEEDBACK) {
	72	+ fcco = fout;
	73	+ do_div(fout, p_div);
	74	+ } else
	75	+ fcco = fout * p_div;
	76	+
	77	+ if (fcco > 320000000ULL \|\| fcco < 156000000ULL)
	78	+ return 0;
	79	+
	80	+ return fout;
	81	+}
	82	+
	83	+unsigned int get_hclk_clk_div(void)
	84	+{
	85	+ u32 val;
	86	+
	87	+ val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
	88	+
	89	+ return 1 << val;
	90	+}
	91	+
	92	+unsigned int get_hclk_clk_rate(void)
	93	+{
	94	+ return get_hclk_pll_rate() / get_hclk_clk_div();
	95	+}
	96	+
	97	+unsigned int get_periph_clk_div(void)
	98	+{
	99	+ u32 val;
	100	+
	101	+ val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
	102	+
	103	+ return (val >> 2) + 1;
	104	+}
	105	+
	106	+unsigned int get_periph_clk_rate(void)
	107	+{
	108	+ if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
	109	+ return get_sys_clk_rate();
	110	+
	111	+ return get_hclk_pll_rate() / get_periph_clk_div();
	112	+}
	113	+
	114	+int get_serial_clock(void)
	115	+{
	116	+ return get_periph_clk_rate();
	117	+}

arch/arm/cpu/arm926ejs/lpc32xx/cpu.c

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#include <common.h>
	21	+#include <asm/arch/cpu.h>
	22	+#include <asm/arch/clk.h>
	23	+#include <asm/arch/wdt.h>
	24	+#include <asm/io.h>
	25	+
	26	+static struct clk_pm_regs clk = (struct clk_pm_regs )CLK_PM_BASE;
	27	+static struct wdt_regs wdt = (struct wdt_regs )WDT_BASE;
	28	+
	29	+void reset_cpu(ulong addr)
	30	+{
	31	+ /* Enable watchdog clock */
	32	+ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
	33	+
	34	+ /* Reset pulse length is 13005 peripheral clock frames */
	35	+ writel(13000, &wdt->pulse);
	36	+
	37	+ /* Force WDOG_RESET2 and RESOUT_N signal active */
	38	+ writel(WDTIM_MCTRL_RESFRC2 \| WDTIM_MCTRL_RESFRC1 \| WDTIM_MCTRL_M_RES2,
	39	+ &wdt->mctrl);
	40	+
	41	+ while (1)
	42	+ /* NOP */;
	43	+}
	44	+
	45	+#if defined(CONFIG_ARCH_CPU_INIT)
	46	+int arch_cpu_init(void)
	47	+{
	48	+ /*
	49	+ * It might be necessary to flush data cache, if U-boot is loaded
	50	+ * from kickstart bootloader, e.g. from S1L loader
	51	+ */
	52	+ flush_dcache_all();
	53	+
	54	+ return 0;
	55	+}
	56	+#else
	57	+#error "You have to select CONFIG_ARCH_CPU_INIT"
	58	+#endif
	59	+
	60	+#if defined(CONFIG_DISPLAY_CPUINFO)
	61	+int print_cpuinfo(void)
	62	+{
	63	+ printf("CPU: NXP LPC32XX\n");
	64	+ printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
	65	+ printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
	66	+ printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
	67	+
	68	+ return 0;
	69	+}
	70	+#endif

arch/arm/cpu/arm926ejs/lpc32xx/devices.c

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#include <common.h>
	21	+#include <asm/arch/cpu.h>
	22	+#include <asm/arch/clk.h>
	23	+#include <asm/arch/uart.h>
	24	+#include <asm/io.h>
	25	+
	26	+static struct clk_pm_regs clk = (struct clk_pm_regs )CLK_PM_BASE;
	27	+static struct uart_ctrl_regs ctrl = (struct uart_ctrl_regs )UART_CTRL_BASE;
	28	+
	29	+void lpc32xx_uart_init(unsigned int uart_id)
	30	+{
	31	+ if (uart_id < 1 \|\| uart_id > 7)
	32	+ return;
	33	+
	34	+ /* Disable loopback mode, if it is set by S1L bootloader */
	35	+ clrbits_le32(&ctrl->loop,
	36	+ UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
	37	+
	38	+ if (uart_id < 3 \|\| uart_id > 6)
	39	+ return;
	40	+
	41	+ /* Enable UART system clock */
	42	+ setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
	43	+
	44	+ /* Set UART into autoclock mode */
	45	+ clrsetbits_le32(&ctrl->clkmode,
	46	+ UART_CLKMODE_MASK(uart_id),
	47	+ UART_CLKMODE_AUTO(uart_id));
	48	+
	49	+ /* Bypass pre-divider of UART clock */
	50	+ writel(CLK_UART_X_DIV(1) \| CLK_UART_Y_DIV(1),
	51	+ &clk->u3clk + (uart_id - 3));
	52	+}

arch/arm/cpu/arm926ejs/lpc32xx/timer.c

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#include <common.h>
	21	+#include <asm/arch/cpu.h>
	22	+#include <asm/arch/clk.h>
	23	+#include <asm/arch/timer.h>
	24	+#include <asm/io.h>
	25	+
	26	+static struct timer_regs timer0 = (struct timer_regs )TIMER0_BASE;
	27	+static struct timer_regs timer1 = (struct timer_regs )TIMER1_BASE;
	28	+static struct clk_pm_regs clk = (struct clk_pm_regs )CLK_PM_BASE;
	29	+
	30	+static void lpc32xx_timer_clock(u32 bit, int enable)
	31	+{
	32	+ if (enable)
	33	+ setbits_le32(&clk->timclk_ctrl1, bit);
	34	+ else
	35	+ clrbits_le32(&clk->timclk_ctrl1, bit);
	36	+}
	37	+
	38	+static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
	39	+{
	40	+ writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
	41	+ writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
	42	+ writel(0, &timer->tc);
	43	+ writel(0, &timer->pr);
	44	+
	45	+ /* Count mode is every rising PCLK edge */
	46	+ writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
	47	+
	48	+ /* Set prescale counter value */
	49	+ writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
	50	+}
	51	+
	52	+static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
	53	+{
	54	+ if (enable)
	55	+ writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
	56	+ else
	57	+ writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
	58	+}
	59	+
	60	+int timer_init(void)
	61	+{
	62	+ lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
	63	+ lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
	64	+ lpc32xx_timer_count(timer0, 1);
	65	+
	66	+ return 0;
	67	+}
	68	+
	69	+ulong get_timer(ulong base)
	70	+{
	71	+ return readl(&timer0->tc) - base;
	72	+}
	73	+
	74	+void __udelay(unsigned long usec)
	75	+{
	76	+ lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
	77	+ lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
	78	+ lpc32xx_timer_count(timer1, 1);
	79	+
	80	+ while (readl(&timer1->tc) < usec)
	81	+ /* NOP */;
	82	+
	83	+ lpc32xx_timer_count(timer1, 0);
	84	+ lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
	85	+}
	86	+
	87	+unsigned long long get_ticks(void)
	88	+{
	89	+ return get_timer(0);
	90	+}
	91	+
	92	+ulong get_tbclk(void)
	93	+{
	94	+ return CONFIG_SYS_HZ;
	95	+}

arch/arm/include/asm/arch-lpc32xx/clk.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_CLK_H
	21	+#define _LPC32XX_CLK_H
	22	+
	23	+#include <asm/types.h>
	24	+
	25	+#define OSC_CLK_FREQUENCY 13000000
	26	+#define RTC_CLK_FREQUENCY 32768
	27	+
	28	+/* Clocking and Power Control Registers */
	29	+struct clk_pm_regs {
	30	+ u32 reserved0[5];
	31	+ u32 boot_map; /* Boot Map Control Register */
	32	+ u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */
	33	+ u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
	34	+ /* Internal Start Signal Sources Registers */
	35	+ u32 start_er_int; /* Start Enable Register */
	36	+ u32 start_rsr_int; /* Start Raw Status Register */
	37	+ u32 start_sr_int; /* Start Status Register */
	38	+ u32 start_apr_int; /* Start Activation Polarity Register */
	39	+ /* Device Pin Start Signal Sources Registers */
	40	+ u32 start_er_pin; /* Start Enable Register */
	41	+ u32 start_rsr_pin; /* Start Raw Status Register */
	42	+ u32 start_sr_pin; /* Start Status Register */
	43	+ u32 start_apr_pin; /* Start Activation Polarity Register */
	44	+ /* Clock Control Registers */
	45	+ u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
	46	+ u32 pwr_ctrl; /* Power Control Register */
	47	+ u32 pll397_ctrl; /* PLL397 Control Register */
	48	+ u32 osc_ctrl; /* Main Oscillator Control Register */
	49	+ u32 sysclk_ctrl; /* SYSCLK Control Register */
	50	+ u32 lcdclk_ctrl; /* LCD Clock Control Register */
	51	+ u32 hclkpll_ctrl; /* HCLK PLL Control Register */
	52	+ u32 reserved1;
	53	+ u32 adclk_ctrl1; /* ADC Clock Control1 Register */
	54	+ u32 usb_ctrl; /* USB Control Register */
	55	+ u32 sdramclk_ctrl; /* SDRAM Clock Control Register */
	56	+ u32 ddr_lap_nom; /* DDR Calibration Nominal Value */
	57	+ u32 ddr_lap_count; /* DDR Calibration Measured Value */
	58	+ u32 ddr_cal_delay; /* DDR Calibration Delay Value */
	59	+ u32 ssp_ctrl; /* SSP Control Register */
	60	+ u32 i2s_ctrl; /* I2S Clock Control Register */
	61	+ u32 ms_ctrl; /* Memory Card Control Register */
	62	+ u32 reserved2[3];
	63	+ u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */
	64	+ u32 reserved3[4];
	65	+ u32 test_clk; /* Test Clock Selection Register */
	66	+ u32 sw_int; /* Software Interrupt Register */
	67	+ u32 i2cclk_ctrl; /* I2C Clock Control Register */
	68	+ u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */
	69	+ u32 adclk_ctrl; /* ADC Clock Control Register */
	70	+ u32 pwmclk_ctrl; /* PWM Clock Control Register */
	71	+ u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */
	72	+ u32 timclk_ctrl1; /* Motor and Timer Clock Control */
	73	+ u32 spi_ctrl; /* SPI Control Register */
	74	+ u32 flashclk_ctrl; /* NAND Flash Clock Control Register */
	75	+ u32 reserved4;
	76	+ u32 u3clk; /* UART 3 Clock Control Register */
	77	+ u32 u4clk; /* UART 4 Clock Control Register */
	78	+ u32 u5clk; /* UART 5 Clock Control Register */
	79	+ u32 u6clk; /* UART 6 Clock Control Register */
	80	+ u32 irdaclk; /* IrDA Clock Control Register */
	81	+ u32 uartclk_ctrl; /* UART Clock Control Register */
	82	+ u32 dmaclk_ctrl; /* DMA Clock Control Register */
	83	+ u32 autoclk_ctrl; /* Autoclock Control Register */
	84	+};
	85	+
	86	+/* HCLK Divider Control Register bits */
	87	+#define CLK_HCLK_DDRAM_HALF (0x2 << 7)
	88	+#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7)
	89	+#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7)
	90	+#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2)
	91	+#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2)
	92	+#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0)
	93	+#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0)
	94	+#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0)
	95	+#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0)
	96	+
	97	+/* Power Control Register bits */
	98	+#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10)
	99	+#define CLK_PWR_EMC_SREFREQ (1 << 9)
	100	+#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8)
	101	+#define CLK_PWR_SDRAM_SREFREQ (1 << 7)
	102	+#define CLK_PWR_HIGHCORE_LEVEL (1 << 5)
	103	+#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4)
	104	+#define CLK_PWR_SYSCLKEN_CTRL (1 << 3)
	105	+#define CLK_PWR_NORMAL_RUN (1 << 2)
	106	+#define CLK_PWR_HIGHCORE_CTRL (1 << 1)
	107	+#define CLK_PWR_STOP_MODE (1 << 0)
	108	+
	109	+/* SYSCLK Control Register bits */
	110	+#define CLK_SYSCLK_PLL397 (1 << 1)
	111	+#define CLK_SYSCLK_MUX (1 << 0)
	112	+
	113	+/* HCLK PLL Control Register bits */
	114	+#define CLK_HCLK_PLL_OPERATING (1 << 16)
	115	+#define CLK_HCLK_PLL_BYPASS (1 << 15)
	116	+#define CLK_HCLK_PLL_DIRECT (1 << 14)
	117	+#define CLK_HCLK_PLL_FEEDBACK (1 << 13)
	118	+#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11)
	119	+#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11)
	120	+#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11)
	121	+#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11)
	122	+#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11)
	123	+#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9)
	124	+#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9)
	125	+#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9)
	126	+#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9)
	127	+#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9)
	128	+#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1)
	129	+#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1)
	130	+#define CLK_HCLK_PLL_LOCKED (1 << 0)
	131	+
	132	+/* Ethernet MAC Clock Control Register bits */
	133	+#define CLK_MAC_RMII (0x3 << 3)
	134	+#define CLK_MAC_MII (0x1 << 3)
	135	+#define CLK_MAC_MASTER (1 << 2)
	136	+#define CLK_MAC_SLAVE (1 << 1)
	137	+#define CLK_MAC_REG (1 << 0)
	138	+
	139	+/* Timer Clock Control1 Register bits */
	140	+#define CLK_TIMCLK_MOTOR (1 << 6)
	141	+#define CLK_TIMCLK_TIMER3 (1 << 5)
	142	+#define CLK_TIMCLK_TIMER2 (1 << 4)
	143	+#define CLK_TIMCLK_TIMER1 (1 << 3)
	144	+#define CLK_TIMCLK_TIMER0 (1 << 2)
	145	+#define CLK_TIMCLK_TIMER5 (1 << 1)
	146	+#define CLK_TIMCLK_TIMER4 (1 << 0)
	147	+
	148	+/* Timer Clock Control Register bits */
	149	+#define CLK_TIMCLK_HSTIMER (1 << 1)
	150	+#define CLK_TIMCLK_WATCHDOG (1 << 0)
	151	+
	152	+/* UART Clock Control Register bits */
	153	+#define CLK_UART(n) (1 << ((n) - 3))
	154	+
	155	+/* UARTn Clock Select Registers bits */
	156	+#define CLK_UART_HCLK (1 << 16)
	157	+#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8)
	158	+#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0)
	159	+
	160	+/* DMA Clock Control Register bits */
	161	+#define CLK_DMA_ENABLE (1 << 0)
	162	+
	163	+unsigned int get_sys_clk_rate(void);
	164	+unsigned int get_hclk_pll_rate(void);
	165	+unsigned int get_hclk_clk_div(void);
	166	+unsigned int get_hclk_clk_rate(void);
	167	+unsigned int get_periph_clk_div(void);
	168	+unsigned int get_periph_clk_rate(void);
	169	+
	170	+#endif /* _LPC32XX_CLK_H */

arch/arm/include/asm/arch-lpc32xx/config.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Common definitions for LPC32XX board configurations
	3	+ *
	4	+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or
	7	+ * modify it under the terms of the GNU General Public License
	8	+ * as published by the Free Software Foundation; either version 2
	9	+ * of the License, or (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	19	+ * MA 02110-1301, USA.
	20	+ */
	21	+
	22	+#ifndef _LPC32XX_CONFIG_H
	23	+#define _LPC32XX_CONFIG_H
	24	+
	25	+/* Basic CPU architecture */
	26	+#define CONFIG_ARM926EJS
	27	+#define CONFIG_ARCH_CPU_INIT
	28	+
	29	+#define CONFIG_NR_DRAM_BANKS_MAX 2
	30	+
	31	+/* 1KHz clock tick */
	32	+#define CONFIG_SYS_HZ 1000
	33	+
	34	+/* UART configuration */
	35	+#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
	36	+#define CONFIG_SYS_NS16550_SERIAL
	37	+#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
	38	+#elif (CONFIG_SYS_LPC32XX_UART == 1) \|\| (CONFIG_SYS_LPC32XX_UART == 2) \|\| \
	39	+ (CONFIG_SYS_LPC32XX_UART == 7)
	40	+#define CONFIG_LPC32XX_HSUART
	41	+#else
	42	+#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
	43	+#endif
	44	+
	45	+#if defined(CONFIG_SYS_NS16550_SERIAL)
	46	+#define CONFIG_SYS_NS16550
	47	+
	48	+#define CONFIG_SYS_NS16550_REG_SIZE -4
	49	+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	50	+
	51	+#define CONFIG_SYS_NS16550_COM1 UART3_BASE
	52	+#define CONFIG_SYS_NS16550_COM2 UART4_BASE
	53	+#define CONFIG_SYS_NS16550_COM3 UART5_BASE
	54	+#define CONFIG_SYS_NS16550_COM4 UART6_BASE
	55	+#endif
	56	+
	57	+#if defined(CONFIG_LPC32XX_HSUART)
	58	+#if CONFIG_SYS_LPC32XX_UART == 1
	59	+#define HS_UART_BASE HS_UART1_BASE
	60	+#elif CONFIG_SYS_LPC32XX_UART == 2
	61	+#define HS_UART_BASE HS_UART2_BASE
	62	+#else /* CONFIG_SYS_LPC32XX_UART == 7 */
	63	+#define HS_UART_BASE HS_UART7_BASE
	64	+#endif
	65	+#endif
	66	+
	67	+#define CONFIG_SYS_BAUDRATE_TABLE \
	68	+ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
	69	+
	70	+/* NOR Flash */
	71	+#if defined(CONFIG_SYS_FLASH_CFI)
	72	+#define CONFIG_FLASH_CFI_DRIVER
	73	+#define CONFIG_SYS_FLASH_PROTECTION
	74	+#endif
	75	+
	76	+#endif /* _LPC32XX_CONFIG_H */

arch/arm/include/asm/arch-lpc32xx/cpu.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_CPU_H
	21	+#define _LPC32XX_CPU_H
	22	+
	23	+/* LPC32XX Memory map */
	24	+
	25	+/* AHB physical base addresses */
	26	+#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
	27	+#define SSP0_BASE 0x20084000 /* SSP0 registers base */
	28	+#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
	29	+#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
	30	+#define DMA_BASE 0x31000000 /* DMA controller registers base */
	31	+#define USB_BASE 0x31020000 /* USB registers base */
	32	+#define LCD_BASE 0x31040000 /* LCD registers base */
	33	+#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
	34	+#define EMC_BASE 0x31080000 /* EMC configuration registers base */
	35	+
	36	+/* FAB peripherals base addresses */
	37	+#define CLK_PM_BASE 0x40004000 /* System control registers base */
	38	+#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */
	39	+#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */
	40	+#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
	41	+#define RTC_BASE 0x40024000 /* RTC registers base */
	42	+#define GPIO_BASE 0x40028000 /* GPIO registers base */
	43	+#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
	44	+#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
	45	+#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
	46	+#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */
	47	+
	48	+/* APB peripherals base addresses */
	49	+#define UART3_BASE 0x40080000 /* UART 3 registers base */
	50	+#define UART4_BASE 0x40088000 /* UART 4 registers base */
	51	+#define UART5_BASE 0x40090000 /* UART 5 registers base */
	52	+#define UART6_BASE 0x40098000 /* UART 6 registers base */
	53	+
	54	+/* External SDRAM Memory Bank base addresses */
	55	+#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
	56	+#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */
	57	+
	58	+/* External Static Memory Bank base addresses */
	59	+#define EMC_CS0_BASE 0xE0000000
	60	+#define EMC_CS1_BASE 0xE1000000
	61	+#define EMC_CS2_BASE 0xE2000000
	62	+#define EMC_CS3_BASE 0xE3000000
	63	+
	64	+#endif /* _LPC32XX_CPU_H */

arch/arm/include/asm/arch-lpc32xx/emc.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_EMC_H
	21	+#define _LPC32XX_EMC_H
	22	+
	23	+#include <asm/types.h>
	24	+
	25	+/* EMC Registers */
	26	+struct emc_regs {
	27	+ u32 ctrl; /* Controls operation of the EMC */
	28	+ u32 status; /* Provides EMC status information */
	29	+ u32 config; /* Configures operation of the EMC */
	30	+ u32 reserved0[5];
	31	+ u32 control; /* Controls dyn memory operation */
	32	+ u32 refresh; /* Configures dyn memory refresh operation */
	33	+ u32 read_config; /* Configures the dyn memory read strategy */
	34	+ u32 reserved1;
	35	+ u32 t_rp; /* Precharge command period */
	36	+ u32 t_ras; /* Active to precharge command period */
	37	+ u32 t_srex; /* Self-refresh exit time */
	38	+ u32 reserved2[2];
	39	+ u32 t_wr; /* Write recovery time */
	40	+ u32 t_rc; /* Active to active command period */
	41	+ u32 t_rfc; /* Auto-refresh period */
	42	+ u32 t_xsr; /* Exit self-refresh to active command time */
	43	+ u32 t_rrd; /* Active bank A to active bank B latency */
	44	+ u32 t_mrd; /* Load mode register to active command time */
	45	+ u32 t_cdlr; /* Last data in to read command time */
	46	+ u32 reserved3[8];
	47	+ u32 extended_wait; /* time for static memory rd/wr transfers */
	48	+ u32 reserved4[31];
	49	+ u32 config0; /* Configuration information for the SDRAM */
	50	+ u32 rascas0; /* RAS and CAS latencies for the SDRAM */
	51	+ u32 reserved5[6];
	52	+ u32 config1; /* Configuration information for the SDRAM */
	53	+ u32 rascas1; /* RAS and CAS latencies for the SDRAM */
	54	+ u32 reserved6[54];
	55	+ struct emc_stat_t {
	56	+ u32 config; /* Static memory configuration */
	57	+ u32 waitwen; /* Delay from chip select to write enable */
	58	+ u32 waitoen; /* Delay to output enable */
	59	+ u32 waitrd; /* Delay to a read access */
	60	+ u32 waitpage; /* Delay for async page mode read */
	61	+ u32 waitwr; /* Delay to a write access */
	62	+ u32 waitturn; /* Number of bus turnaround cycles */
	63	+ u32 reserved;
	64	+ } stat[4];
	65	+ u32 reserved7[96];
	66	+ struct emc_ahb_t {
	67	+ u32 control; /* Control register for AHB */
	68	+ u32 status; /* Status register for AHB */
	69	+ u32 timeout; /* Timeout register for AHB */
	70	+ u32 reserved[5];
	71	+ } ahb[5];
	72	+};
	73	+
	74	+/* Static Memory Configuration Register bits */
	75	+#define EMC_STAT_CONFIG_WP (1 << 20)
	76	+#define EMC_STAT_CONFIG_EW (1 << 8)
	77	+#define EMC_STAT_CONFIG_PB (1 << 7)
	78	+#define EMC_STAT_CONFIG_PC (1 << 6)
	79	+#define EMC_STAT_CONFIG_PM (1 << 3)
	80	+#define EMC_STAT_CONFIG_32BIT (2 << 0)
	81	+#define EMC_STAT_CONFIG_16BIT (1 << 0)
	82	+#define EMC_STAT_CONFIG_8BIT (0 << 0)
	83	+
	84	+/* Static Memory Delay Registers */
	85	+#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
	86	+#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
	87	+#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
	88	+#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
	89	+#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
	90	+#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
	91	+
	92	+#endif /* _LPC32XX_EMC_H */

arch/arm/include/asm/arch-lpc32xx/sys_proto.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_SYS_PROTO_H
	21	+#define _LPC32XX_SYS_PROTO_H
	22	+
	23	+void lpc32xx_uart_init(unsigned int uart_id);
	24	+
	25	+#endif /* _LPC32XX_SYS_PROTO_H */

arch/arm/include/asm/arch-lpc32xx/timer.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_TIMER_H
	21	+#define _LPC32XX_TIMER_H
	22	+
	23	+#include <asm/types.h>
	24	+
	25	+/* Timer/Counter Registers */
	26	+struct timer_regs {
	27	+ u32 ir; /* Interrupt Register */
	28	+ u32 tcr; /* Timer Control Register */
	29	+ u32 tc; /* Timer Counter */
	30	+ u32 pr; /* Prescale Register */
	31	+ u32 pc; /* Prescale Counter */
	32	+ u32 mcr; /* Match Control Register */
	33	+ u32 mr[4]; /* Match Registers */
	34	+ u32 ccr; /* Capture Control Register */
	35	+ u32 cr[4]; /* Capture Registers */
	36	+ u32 emr; /* External Match Register */
	37	+ u32 reserved[12];
	38	+ u32 ctcr; /* Count Control Register */
	39	+};
	40	+
	41	+/* Timer/Counter Interrupt Register bits */
	42	+#define TIMER_IR_CR(n) (1 << ((n) + 4))
	43	+#define TIMER_IR_MR(n) (1 << (n))
	44	+
	45	+/* Timer/Counter Timer Control Register bits */
	46	+#define TIMER_TCR_COUNTER_RESET (1 << 1)
	47	+#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
	48	+#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
	49	+
	50	+/* Timer/Counter Match Control Register bits */
	51	+#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
	52	+#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
	53	+#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
	54	+
	55	+/* Timer/Counter Capture Control Register bits */
	56	+#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
	57	+#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
	58	+#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
	59	+
	60	+/* Timer/Counter External Match Register bits */
	61	+#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
	62	+#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
	63	+#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
	64	+#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
	65	+#define TIMER_EMR_EM(n) (1 << (n))
	66	+
	67	+/* Timer/Counter Count Control Register bits */
	68	+#define TIMER_CTCR_INPUT(n) ((n) << 2)
	69	+#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
	70	+#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
	71	+#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
	72	+#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
	73	+
	74	+#endif /* _LPC32XX_TIMER_H */

arch/arm/include/asm/arch-lpc32xx/uart.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_UART_H
	21	+#define _LPC32XX_UART_H
	22	+
	23	+#include <asm/types.h>
	24	+
	25	+/* UART Control Registers */
	26	+struct uart_ctrl_regs {
	27	+ u32 ctrl; /* Control Register */
	28	+ u32 clkmode; /* Clock Mode Register */
	29	+ u32 loop; /* Loopback Control Register */
	30	+};
	31	+
	32	+/* UART Control Register bits */
	33	+#define UART_CTRL_UART3_MD_CTRL (1 << 11)
	34	+#define UART_CTRL_HDPX_INV (1 << 10)
	35	+#define UART_CTRL_HDPX_EN (1 << 9)
	36	+#define UART_CTRL_UART6_IRDA (1 << 5)
	37	+#define UART_CTRL_IR_TX6_INV (1 << 4)
	38	+#define UART_CTRL_IR_RX6_INV (1 << 3)
	39	+#define UART_CTRL_IR_RX_LENGTH (1 << 2)
	40	+#define UART_CTRL_IR_TX_LENGTH (1 << 1)
	41	+#define UART_CTRL_UART5_USB_MODE (1 << 0)
	42	+
	43	+/* UART Clock Mode Register bits */
	44	+#define UART_CLKMODE_STATX(n) (1 << ((n) + 16))
	45	+#define UART_CLKMODE_STAT (1 << 14)
	46	+#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2))
	47	+#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2))
	48	+#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2))
	49	+#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2))
	50	+
	51	+/* UART Loopback Control Register bits */
	52	+#define UART_LOOPBACK(n) (1 << ((n) - 1))
	53	+
	54	+#endif /* _LPC32XX_UART_H */

arch/arm/include/asm/arch-lpc32xx/wdt.h

Diff comments View file @ 52f69f8

	1	+/*
	2	+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * as published by the Free Software Foundation; either version 2
	7	+ * of the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	+ * MA 02110-1301, USA.
	18	+ */
	19	+
	20	+#ifndef _LPC32XX_WDT_H
	21	+#define _LPC32XX_WDT_H
	22	+
	23	+#include <asm/types.h>
	24	+
	25	+/* Watchdog Timer Registers */
	26	+struct wdt_regs {
	27	+ u32 isr; /* Interrupt Status Register */
	28	+ u32 ctrl; /* Control Register */
	29	+ u32 counter; /* Counter Value Register */
	30	+ u32 mctrl; /* Match Control Register */
	31	+ u32 match0; /* Match 0 Register */
	32	+ u32 emr; /* External Match Control Register */
	33	+ u32 pulse; /* Reset Pulse Length Register */
	34	+ u32 res; /* Reset Source Register */
	35	+};
	36	+
	37	+/* Watchdog Timer Control Register bits */
	38	+#define WDTIM_CTRL_PAUSE_EN (1 << 2)
	39	+#define WDTIM_CTRL_RESET_COUNT (1 << 1)
	40	+#define WDTIM_CTRL_COUNT_ENAB (1 << 0)
	41	+
	42	+/* Watchdog Timer Match Control Register bits */
	43	+#define WDTIM_MCTRL_RESFRC2 (1 << 6)
	44	+#define WDTIM_MCTRL_RESFRC1 (1 << 5)
	45	+#define WDTIM_MCTRL_M_RES2 (1 << 4)
	46	+#define WDTIM_MCTRL_M_RES1 (1 << 3)
	47	+#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2)
	48	+#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1)
	49	+#define WDTIM_MCTRL_MR0_INT (1 << 0)
	50	+
	51	+#endif /* _LPC32XX_WDT_H */