am335x:Handle worst case scenario for Errata 1.0.24

In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>

am335x:Handle worst case scenario for Errata 1.0.24
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>
Steve Kipisz · Tom Rini
1 parent 9721027aae
Showing 6 changed files with 30 additions and 8 deletions Side-by-side Diff
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
board/ti/am335x/board.c
include/configs/pcm051.h
include/power/tps65217.h
@@ -144,6 +144,8 @@
  */
 __weak void am33xx_spl_board_init(void)
 {
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
  
 static void rtc32k_enable(void)
@@ -51,10 +51,14 @@
 	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
 };
  
-const struct dpll_params dpll_mpu = {
+struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
+const struct dpll_params dpll_core_opp100 = {
 		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		50, OSC-1, -1, -1, 1, 1, 1};
 const struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
  
@@ -29,6 +29,8 @@
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
  
 extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
  
 #endif	/* endif _CLOCKS_AM33XX_H_ */
@@ -249,14 +249,13 @@
 void am33xx_spl_board_init(void)
 {
 	struct am335x_baseboard_id header;
-	struct dpll_params dpll_mpu = {0, OSC-1, 1, -1, -1, -1, -1};
 	int mpu_vdd;
  
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
  
 	/* Get the frequency */
-	dpll_mpu.m = am335x_get_efuse_mpu_max_freq(cdev);
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  
 	if (board_is_bone(&header) || board_is_bone_lt(&header)) {
 		/* BeagleBone PMIC Code */
  
@@ -293,13 +292,13 @@
 		 * a Beaglebone Black it supports 1GHz.
 		 */
 		if (board_is_bone_lt(&header))
-			dpll_mpu.m = MPUPLL_M_1000;
+			dpll_mpu_opp100.m = MPUPLL_M_1000;
  
 		/*
 		 * Increase USB current limit to 1300mA or 1800mA and set
 		 * the MPU voltage controller as needed.
 		 */
-		if (dpll_mpu.m == MPUPLL_M_1000) {
+		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 		} else {
  
@@ -313,7 +312,16 @@
 				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 			puts("tps65217_reg_write failure\n");
  
+		/* Set DCDC3 (CORE) voltage to 1.125V */
+		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+			puts("tps65217_voltage_update failure\n");
+			return;
+		}
  
+		/* Set CORE Frequencies to OPP100 */
+		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
 		/* Set DCDC2 (MPU) voltage */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 			puts("tps65217_voltage_update failure\n");
@@ -360,7 +368,8 @@
 		 * VDD to drive at that speed.
 		 */
 		sil_rev = readl(&cdev->deviceid) >> 28;
-		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu.m);
+		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+						      dpll_mpu_opp100.m);
  
 		/* Tell the TPS65910 to use i2c */
 		tps65910_set_i2c_control();
  
@@ -372,10 +381,13 @@
 		/* Second, update the CORE voltage. */
 		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 			return;
+
+		/* Set CORE Frequencies to OPP100 */
+		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 	}
  
 	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
  
 const struct dpll_params *get_dpll_ddr_params(void)
@@ -201,6 +201,7 @@
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 /*
  * Place the image at the start of the ROM defined image space.
  * We limit our size to the ROM-defined downloaded image area, and use the
@@ -65,6 +65,7 @@
 #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
  
+#define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
 #define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
 #define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
...	...	@@ -144,6 +144,8 @@
144	144	*/
145	145	__weak void am33xx_spl_board_init(void)
146	146	{
	147	+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
	148	+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
147	149	}
148	150
149	151	static void rtc32k_enable(void)
...	...	@@ -51,10 +51,14 @@
51	51	.cm_div_m2_dpll = CM_WKUP + 0xA0,
52	52	};
53	53
54		-const struct dpll_params dpll_mpu = {
	54	+struct dpll_params dpll_mpu_opp100 = {
55	55	CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
56		-const struct dpll_params dpll_core = {
	56	+const struct dpll_params dpll_core_opp100 = {
57	57	1000, OSC-1, -1, -1, 10, 8, 4};
	58	+const struct dpll_params dpll_mpu = {
	59	+ MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
	60	+const struct dpll_params dpll_core = {
	61	+ 50, OSC-1, -1, -1, 1, 1, 1};
58	62	const struct dpll_params dpll_per = {
59	63	960, OSC-1, 5, -1, -1, -1, -1};
60	64
...	...	@@ -29,6 +29,8 @@
29	29	#define UART_SMART_IDLE_EN (0x1 << 0x3)
30	30
31	31	extern void enable_dmm_clocks(void);
	32	+extern const struct dpll_params dpll_core_opp100;
	33	+extern struct dpll_params dpll_mpu_opp100;
32	34
33	35	#endif /* endif _CLOCKS_AM33XX_H_ */
...	...	@@ -249,14 +249,13 @@
249	249	void am33xx_spl_board_init(void)
250	250	{
251	251	struct am335x_baseboard_id header;
252		- struct dpll_params dpll_mpu = {0, OSC-1, 1, -1, -1, -1, -1};
253	252	int mpu_vdd;
254	253
255	254	if (read_eeprom(&header) < 0)
256	255	puts("Could not get board ID.\n");
257	256
258	257	/* Get the frequency */
259		- dpll_mpu.m = am335x_get_efuse_mpu_max_freq(cdev);
	258	+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
260	259
261	260	if (board_is_bone(&header) \|\| board_is_bone_lt(&header)) {
262	261	/* BeagleBone PMIC Code */
263	262
...	...	@@ -293,13 +292,13 @@
293	292	* a Beaglebone Black it supports 1GHz.
294	293	*/
295	294	if (board_is_bone_lt(&header))
296		- dpll_mpu.m = MPUPLL_M_1000;
	295	+ dpll_mpu_opp100.m = MPUPLL_M_1000;
297	296
298	297	/*
299	298	* Increase USB current limit to 1300mA or 1800mA and set
300	299	* the MPU voltage controller as needed.
301	300	*/
302		- if (dpll_mpu.m == MPUPLL_M_1000) {
	301	+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
303	302	usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
304	303	mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
305	304	} else {
306	305
...	...	@@ -313,7 +312,16 @@
313	312	TPS65217_USB_INPUT_CUR_LIMIT_MASK))
314	313	puts("tps65217_reg_write failure\n");
315	314
	315	+ /* Set DCDC3 (CORE) voltage to 1.125V */
	316	+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
	317	+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
	318	+ puts("tps65217_voltage_update failure\n");
	319	+ return;
	320	+ }
316	321
	322	+ /* Set CORE Frequencies to OPP100 */
	323	+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
	324	+
317	325	/* Set DCDC2 (MPU) voltage */
318	326	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
319	327	puts("tps65217_voltage_update failure\n");
...	...	@@ -360,7 +368,8 @@
360	368	* VDD to drive at that speed.
361	369	*/
362	370	sil_rev = readl(&cdev->deviceid) >> 28;
363		- mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu.m);
	371	+ mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
	372	+ dpll_mpu_opp100.m);
364	373
365	374	/* Tell the TPS65910 to use i2c */
366	375	tps65910_set_i2c_control();
367	376
...	...	@@ -372,10 +381,13 @@
372	381	/* Second, update the CORE voltage. */
373	382	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
374	383	return;
	384	+
	385	+ /* Set CORE Frequencies to OPP100 */
	386	+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
375	387	}
376	388
377	389	/* Set MPU Frequency to what we detected now that voltages are set */
378		- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
	390	+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
379	391	}
380	392
381	393	const struct dpll_params *get_dpll_ddr_params(void)
...	...	@@ -201,6 +201,7 @@
201	201	/* Defines for SPL */
202	202	#define CONFIG_SPL
203	203	#define CONFIG_SPL_FRAMEWORK
	204	+#define CONFIG_SPL_BOARD_INIT
204	205	/*
205	206	* Place the image at the start of the ROM defined image space.
206	207	* We limit our size to the ROM-defined downloaded image area, and use the
...	...	@@ -65,6 +65,7 @@
65	65	#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02
66	66	#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03
67	67
	68	+#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09
68	69	#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F
69	70	#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11
70	71