MX5: mx51evk: use new pmic driver

Switch to new pmic generic driver. Signed-off-by: Stefano Babic <sbabic@denx.de>

MX5: mx51evk: use new pmic driver
Switch to new pmic generic driver. Signed-off-by: Stefano Babic <sbabic@denx.de>
Stefano Babic · Albert ARIBAUD
1 parent 5213d6e48e
Showing 2 changed files with 31 additions and 22 deletions Side-by-side Diff
board/freescale/mx51evk/mx51evk.c
include/configs/mx51evk.h
@@ -32,6 +32,7 @@
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <pmic.h>
 #include <fsl_pmic.h>
 #include <mc13892.h>
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -182,34 +183,38 @@
 {
 	unsigned int val;
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+	struct pmic *p;
  
+	pmic_init();
+	p = get_pmic();
+
 	/* Write needed to Power Gate 2 register */
-	val = pmic_reg_read(REG_POWER_MISC);
+	pmic_reg_read(p, REG_POWER_MISC, &val);
 	val &= ~PWGT2SPIEN;
-	pmic_reg_write(REG_POWER_MISC, val);
+	pmic_reg_write(p, REG_POWER_MISC, val);
  
 	/* Externally powered */
-	val = pmic_reg_read(REG_CHARGE);
+	pmic_reg_read(p, REG_CHARGE, &val);
 	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
-	pmic_reg_write(REG_CHARGE, val);
+	pmic_reg_write(p, REG_CHARGE, val);
  
 	/* power up the system first */
-	pmic_reg_write(REG_POWER_MISC, PWUP);
+	pmic_reg_write(p, REG_POWER_MISC, PWUP);
  
 	/* Set core voltage to 1.1V */
-	val = pmic_reg_read(REG_SW_0);
+	pmic_reg_read(p, REG_SW_0, &val);
 	val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
-	pmic_reg_write(REG_SW_0, val);
+	pmic_reg_write(p, REG_SW_0, val);
  
 	/* Setup VCC (SW2) to 1.25 */
-	val = pmic_reg_read(REG_SW_1);
+	pmic_reg_read(p, REG_SW_1, &val);
 	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
-	pmic_reg_write(REG_SW_1, val);
+	pmic_reg_write(p, REG_SW_1, val);
  
 	/* Setup 1V2_DIG1 (SW3) to 1.25 */
-	val = pmic_reg_read(REG_SW_2);
+	pmic_reg_read(p, REG_SW_2, &val);
 	val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
-	pmic_reg_write(REG_SW_2, val);
+	pmic_reg_write(p, REG_SW_2, val);
 	udelay(50);
  
 	/* Raise the core frequency to 800MHz */
  
  
  
  
  
  
  
  
@@ -217,36 +222,36 @@
  
 	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
 	/* Setup the switcher mode for SW1 & SW2*/
-	val = pmic_reg_read(REG_SW_4);
+	pmic_reg_read(p, REG_SW_4, &val);
 	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 		(SWMODE_MASK << SWMODE2_SHIFT)));
 	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
-	pmic_reg_write(REG_SW_4, val);
+	pmic_reg_write(p, REG_SW_4, val);
  
 	/* Setup the switcher mode for SW3 & SW4 */
-	val = pmic_reg_read(REG_SW_5);
+	pmic_reg_read(p, REG_SW_5, &val);
 	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 		(SWMODE_MASK << SWMODE4_SHIFT)));
 	val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 		(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
-	pmic_reg_write(REG_SW_5, val);
+	pmic_reg_write(p, REG_SW_5, val);
  
 	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
-	val = pmic_reg_read(REG_SETTING_0);
+	pmic_reg_read(p, REG_SETTING_0, &val);
 	val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 	val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
-	pmic_reg_write(REG_SETTING_0, val);
+	pmic_reg_write(p, REG_SETTING_0, val);
  
 	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
-	val = pmic_reg_read(REG_SETTING_1);
+	pmic_reg_read(p, REG_SETTING_1, &val);
 	val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 	val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
-	pmic_reg_write(REG_SETTING_1, val);
+	pmic_reg_write(p, REG_SETTING_1, val);
  
 	/* Configure VGEN3 and VCAM regulators to use external PNP */
 	val = VGEN3CONFIG | VCAMCONFIG;
-	pmic_reg_write(REG_MODE_1, val);
+	pmic_reg_write(p, REG_MODE_1, val);
 	udelay(200);
  
 	gpio_direction_output(46, 0);
@@ -257,7 +262,7 @@
 	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 		VVIDEOEN | VAUDIOEN  | VSDEN;
-	pmic_reg_write(REG_MODE_1, val);
+	pmic_reg_write(p, REG_MODE_1, val);
  
 	udelay(500);
  
@@ -70,11 +70,15 @@
  
 #define CONFIG_MXC_SPI
  
-#define CONFIG_FSL_PMIC
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_SPI
+#define CONFIG_PMIC_FSL
 #define CONFIG_FSL_PMIC_BUS	0
 #define CONFIG_FSL_PMIC_CS	0
 #define CONFIG_FSL_PMIC_CLK	2500000
 #define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
  
 /*
  * MMC Configs
...	...	@@ -32,6 +32,7 @@
32	32	#include <i2c.h>
33	33	#include <mmc.h>
34	34	#include <fsl_esdhc.h>
	35	+#include <pmic.h>
35	36	#include <fsl_pmic.h>
36	37	#include <mc13892.h>
37	38
38	39
39	40
40	41
41	42
42	43
43	44
44	45
45	46
46	47
47	48
48	49
49	50
...	...	@@ -182,34 +183,38 @@
182	183	{
183	184	unsigned int val;
184	185	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
	186	+ struct pmic *p;
185	187
	188	+ pmic_init();
	189	+ p = get_pmic();
	190	+
186	191	/* Write needed to Power Gate 2 register */
187		- val = pmic_reg_read(REG_POWER_MISC);
	192	+ pmic_reg_read(p, REG_POWER_MISC, &val);
188	193	val &= ~PWGT2SPIEN;
189		- pmic_reg_write(REG_POWER_MISC, val);
	194	+ pmic_reg_write(p, REG_POWER_MISC, val);
190	195
191	196	/* Externally powered */
192		- val = pmic_reg_read(REG_CHARGE);
	197	+ pmic_reg_read(p, REG_CHARGE, &val);
193	198	val \|= ICHRG0 \| ICHRG1 \| ICHRG2 \| ICHRG3 \| CHGAUTOB;
194		- pmic_reg_write(REG_CHARGE, val);
	199	+ pmic_reg_write(p, REG_CHARGE, val);
195	200
196	201	/* power up the system first */
197		- pmic_reg_write(REG_POWER_MISC, PWUP);
	202	+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
198	203
199	204	/* Set core voltage to 1.1V */
200		- val = pmic_reg_read(REG_SW_0);
	205	+ pmic_reg_read(p, REG_SW_0, &val);
201	206	val = (val & ~SWx_VOLT_MASK) \| SWx_1_100V;
202		- pmic_reg_write(REG_SW_0, val);
	207	+ pmic_reg_write(p, REG_SW_0, val);
203	208
204	209	/* Setup VCC (SW2) to 1.25 */
205		- val = pmic_reg_read(REG_SW_1);
	210	+ pmic_reg_read(p, REG_SW_1, &val);
206	211	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
207		- pmic_reg_write(REG_SW_1, val);
	212	+ pmic_reg_write(p, REG_SW_1, val);
208	213
209	214	/* Setup 1V2_DIG1 (SW3) to 1.25 */
210		- val = pmic_reg_read(REG_SW_2);
	215	+ pmic_reg_read(p, REG_SW_2, &val);
211	216	val = (val & ~SWx_VOLT_MASK) \| SWx_1_250V;
212		- pmic_reg_write(REG_SW_2, val);
	217	+ pmic_reg_write(p, REG_SW_2, val);
213	218	udelay(50);
214	219
215	220	/* Raise the core frequency to 800MHz */
216	221
217	222
218	223
219	224
220	225
221	226
222	227
223	228
...	...	@@ -217,36 +222,36 @@
217	222
218	223	/* Set switchers in Auto in NORMAL mode & STANDBY mode */
219	224	/* Setup the switcher mode for SW1 & SW2*/
220		- val = pmic_reg_read(REG_SW_4);
	225	+ pmic_reg_read(p, REG_SW_4, &val);
221	226	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) \|
222	227	(SWMODE_MASK << SWMODE2_SHIFT)));
223	228	val \|= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) \|
224	229	(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
225		- pmic_reg_write(REG_SW_4, val);
	230	+ pmic_reg_write(p, REG_SW_4, val);
226	231
227	232	/* Setup the switcher mode for SW3 & SW4 */
228		- val = pmic_reg_read(REG_SW_5);
	233	+ pmic_reg_read(p, REG_SW_5, &val);
229	234	val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) \|
230	235	(SWMODE_MASK << SWMODE4_SHIFT)));
231	236	val \|= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) \|
232	237	(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
233		- pmic_reg_write(REG_SW_5, val);
	238	+ pmic_reg_write(p, REG_SW_5, val);
234	239
235	240	/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
236		- val = pmic_reg_read(REG_SETTING_0);
	241	+ pmic_reg_read(p, REG_SETTING_0, &val);
237	242	val &= ~(VCAM_MASK \| VGEN3_MASK \| VDIG_MASK);
238	243	val \|= VDIG_1_65 \| VGEN3_1_8 \| VCAM_2_6;
239		- pmic_reg_write(REG_SETTING_0, val);
	244	+ pmic_reg_write(p, REG_SETTING_0, val);
240	245
241	246	/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
242		- val = pmic_reg_read(REG_SETTING_1);
	247	+ pmic_reg_read(p, REG_SETTING_1, &val);
243	248	val &= ~(VVIDEO_MASK \| VSD_MASK \| VAUDIO_MASK);
244	249	val \|= VSD_3_15 \| VAUDIO_3_0 \| VVIDEO_2_775;
245		- pmic_reg_write(REG_SETTING_1, val);
	250	+ pmic_reg_write(p, REG_SETTING_1, val);
246	251
247	252	/* Configure VGEN3 and VCAM regulators to use external PNP */
248	253	val = VGEN3CONFIG \| VCAMCONFIG;
249		- pmic_reg_write(REG_MODE_1, val);
	254	+ pmic_reg_write(p, REG_MODE_1, val);
250	255	udelay(200);
251	256
252	257	gpio_direction_output(46, 0);
...	...	@@ -257,7 +262,7 @@
257	262	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
258	263	val = VGEN3EN \| VGEN3CONFIG \| VCAMEN \| VCAMCONFIG \|
259	264	VVIDEOEN \| VAUDIOEN \| VSDEN;
260		- pmic_reg_write(REG_MODE_1, val);
	265	+ pmic_reg_write(p, REG_MODE_1, val);
261	266
262	267	udelay(500);
263	268
...	...	@@ -70,11 +70,15 @@
70	70
71	71	#define CONFIG_MXC_SPI
72	72
73		-#define CONFIG_FSL_PMIC
	73	+/* PMIC Controller */
	74	+#define CONFIG_PMIC
	75	+#define CONFIG_PMIC_SPI
	76	+#define CONFIG_PMIC_FSL
74	77	#define CONFIG_FSL_PMIC_BUS 0
75	78	#define CONFIG_FSL_PMIC_CS 0
76	79	#define CONFIG_FSL_PMIC_CLK 2500000
77	80	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
	81	+#define CONFIG_FSL_PMIC_BITLEN 32
78	82
79	83	/*
80	84	* MMC Configs