Commit 536d87470869c4c3257d70f387146703a2dee7c5

Authored by Lokesh Vutla
Committed by Tom Rini
1 parent a5c5c5b500

ARM: DRA7: Update DDR IO registers

Update DDR IO register values.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 1 changed file with 8 additions and 8 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/hw_data.c
... ... @@ -592,11 +592,11 @@
592 592 .ctrl_ddrch = 0x40404040,
593 593 .ctrl_lpddr2ch = 0x40404040,
594 594 .ctrl_ddr3ch = 0x80808080,
595   - .ctrl_ddrio_0 = 0xA2084210,
596   - .ctrl_ddrio_1 = 0x84210840,
  595 + .ctrl_ddrio_0 = 0x00094A40,
  596 + .ctrl_ddrio_1 = 0x04A52000,
597 597 .ctrl_ddrio_2 = 0x84210000,
598   - .ctrl_emif_sdram_config_ext = 0x0001C1A7,
599   - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
  598 + .ctrl_emif_sdram_config_ext = 0x0001C127,
  599 + .ctrl_emif_sdram_config_ext_final = 0x0001C127,
600 600 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
601 601 };
602 602  
603 603  
... ... @@ -604,11 +604,11 @@
604 604 .ctrl_ddrch = 0x40404040,
605 605 .ctrl_lpddr2ch = 0x40404040,
606 606 .ctrl_ddr3ch = 0x60606080,
607   - .ctrl_ddrio_0 = 0xA2084210,
608   - .ctrl_ddrio_1 = 0x84210840,
  607 + .ctrl_ddrio_0 = 0x00094A40,
  608 + .ctrl_ddrio_1 = 0x04A52000,
609 609 .ctrl_ddrio_2 = 0x84210000,
610   - .ctrl_emif_sdram_config_ext = 0x0001C1A7,
611   - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
  610 + .ctrl_emif_sdram_config_ext = 0x0001C127,
  611 + .ctrl_emif_sdram_config_ext_final = 0x0001C127,
612 612 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
613 613 };
614 614