Eric Lee / smarc-uboot

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Commit 53cf9435ccf9eaef84d35d00c3a2702f91f7886c

Authored by stroese
1 parent c602883592
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

- CFG_RX_ETH_BUFFER added.

Showing 16 changed files with 54 additions and 36 deletions Side-by-side Diff

... ... @@ -690,7 +690,7 @@
690 690 - NETWORK Support (PCI):
691 691 CONFIG_E1000
692 692 Support for Intel 8254x gigabit chips.
693   -
  693 +
694 694 CONFIG_EEPRO100
695 695 Support for Intel 82557/82559/82559ER chips.
696 696 Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
... ... @@ -1441,6 +1441,14 @@
1441 1441 - CFG_FLASH_CFI:
1442 1442 Define if the flash driver uses extra elements in the
1443 1443 common flash structure for storing flash geometry
  1444 +
  1445 +- CFG_RX_ETH_BUFFER:
  1446 + Defines the number of ethernet receive buffers. On some
  1447 + ethernet controllers it is recommended to set this value
  1448 + to 8 or even higher (EEPRO100 or 405 EMAC), since all
  1449 + buffers can be full shortly after enabling the interface
  1450 + on high ethernet traffic.
  1451 + Defaults to 4 if not defined.
1444 1452  
1445 1453 The following definitions that deal with the placement and management
1446 1454 of environment data (variable area); in general, we support the
include/configs/ASH405.h
Diff comments   View file @ 53cf943
... ... @@ -125,6 +125,10 @@
125 125  
126 126 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
127 127  
  128 +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  129 +
  130 +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  131 +
128 132 /*-----------------------------------------------------------------------
129 133 * NAND-FLASH stuff
130 134 *-----------------------------------------------------------------------
include/configs/CPC45.h
Diff comments   View file @ 53cf943
... ... @@ -144,7 +144,7 @@
144 144 /*
145 145 * NS16550 Configuration
146 146 */
147   -#define CFG_NS16550
  147 +#define CFG_NS16550
148 148 #define CFG_NS16550_SERIAL
149 149  
150 150 #define CFG_NS16550_REG_SIZE 1
... ... @@ -171,7 +171,7 @@
171 171 * Memory configuration using SPD information stored on the SODIMMs
172 172 * not yet supported.
173 173 */
174   -
  174 +
175 175 #define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
176 176  
177 177 /* Bit-field values for MCCR1.
... ... @@ -186,7 +186,7 @@
186 186 #else
187 187 # error "SDRAM size not supported"
188 188 #endif
189   -#define CFG_BANK1_ROW 0
  189 +#define CFG_BANK1_ROW 0
190 190 #define CFG_BANK2_ROW 0
191 191 #define CFG_BANK3_ROW 0
192 192 #define CFG_BANK4_ROW 0
... ... @@ -361,7 +361,7 @@
361 361 /* IRQ_ENA_2 bit definitions */
362 362 #define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
363 363 #define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
364   -#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
  364 +#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
365 365 #define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
366 366 #define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
367 367 #define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
368 368  
... ... @@ -371,9 +371,9 @@
371 371 /* IRQ_STAT_2 bit definitions */
372 372 #define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
373 373 #define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
374   -#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
  374 +#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
375 375 #define I_STAT_2_RTC 0x10 /* RTC IRQ status */
376   -#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
  376 +#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
377 377 #define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
378 378 #define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
379 379 #define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
380 380  
381 381  
... ... @@ -421,14 +421,14 @@
421 421 #define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
422 422 #define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
423 423  
424   -#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
425   -#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
  424 +#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
  425 +#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
426 426 #define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
427   -#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
428   -#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
  427 +#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
  428 +#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
429 429 #define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
430   -#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
431   -#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
  430 +#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
  431 +#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
432 432  
433 433  
434 434 /*-----------------------------------------------------------------------
... ... @@ -441,6 +441,7 @@
441 441 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
442 442  
443 443 #define CONFIG_EEPRO100
  444 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
444 445  
445 446 #define PCI_ENET0_IOADDR 0x00104000
446 447 #define PCI_ENET0_MEMADDR 0x82000000
include/configs/CPCI4052.h
Diff comments   View file @ 53cf943
... ... @@ -146,6 +146,8 @@
146 146  
147 147 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
148 148  
  149 +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  150 +
149 151 /*-----------------------------------------------------------------------
150 152 * PCI stuff
151 153 *-----------------------------------------------------------------------
include/configs/CPCI405AB.h
Diff comments   View file @ 53cf943
... ... @@ -55,15 +55,7 @@
55 55 #endif
56 56  
57 57 #undef CONFIG_BOOTARGS
58   -#define CONFIG_RAMBOOTCOMMAND \
59   - "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
60   - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
61   - "bootm ffc00000 ffca0000"
62   -#define CONFIG_NFSBOOTCOMMAND \
63   - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
64   - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
65   - "bootm ffc00000"
66   -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  58 +#define CONFIG_BOOTCOMMAND "bootm 100000" /* default boot command */
67 59  
68 60 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69 61 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
70 62  
... ... @@ -73,12 +65,7 @@
73 65  
74 66 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
75 67  
76   -#if 0 /* test-only */
77   -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
78   - CONFIG_BOOTP_VENDOREX)
79   -#else
80 68 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT)
81   -#endif
82 69  
83 70 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
84 71 CFG_CMD_DHCP | \
... ... @@ -147,6 +134,8 @@
147 134  
148 135 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
149 136  
  137 +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  138 +
150 139 /*-----------------------------------------------------------------------
151 140 * PCI stuff
152 141 *-----------------------------------------------------------------------
... ... @@ -202,7 +191,7 @@
202 191 #define CFG_FLASH_BASE 0xFFFC0000
203 192 #define CFG_MONITOR_BASE CFG_FLASH_BASE
204 193 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
205   -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  194 +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
206 195  
207 196 /*
208 197 * For booting Linux, the board info and command line data
... ... @@ -360,7 +349,7 @@
360 349 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
361 350  
362 351 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
363   -#define CFG_FPGA_MAX_SIZE 64*1024 /* 64kByte is enough for XC2S15 */
  352 +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */
364 353  
365 354 /* FPGA program pin configuration */
366 355 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
include/configs/CU824.h
Diff comments   View file @ 53cf943
... ... @@ -304,6 +304,7 @@
304 304 #define CFG_ETH_IOBASE 0x00104000
305 305  
306 306 #define CONFIG_EEPRO100
  307 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
307 308 #define PCI_ENET0_IOADDR 0x00104000
308 309 #define PCI_ENET0_MEMADDR 0x80000000
309 310 #endif /* __CONFIG_H */
include/configs/ELPPC.h
Diff comments   View file @ 53cf943
... ... @@ -333,6 +333,7 @@
333 333  
334 334 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
335 335 #define CONFIG_EEPRO100
  336 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
336 337 #define CONFIG_EEPRO100_SROM_WRITE
337 338  
338 339 #endif /* __CONFIG_H */
include/configs/OXC.h
Diff comments   View file @ 53cf943
... ... @@ -94,6 +94,7 @@
94 94 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
95 95  
96 96 #define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */
  97 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
97 98  
98 99 #define PCI_ENET0_IOADDR 0x80000000
99 100 #define PCI_ENET0_MEMADDR 0x80000000
include/configs/PCIPPC2.h
Diff comments   View file @ 53cf943
... ... @@ -261,6 +261,7 @@
261 261 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
262 262  
263 263 #define CONFIG_EEPRO100
  264 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
264 265 #define CONFIG_TULIP
265 266  
266 267 #endif /* __CONFIG_H */
include/configs/PCIPPC6.h
Diff comments   View file @ 53cf943
... ... @@ -263,6 +263,7 @@
263 263 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
264 264  
265 265 #define CONFIG_EEPRO100
  266 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
266 267 #define CONFIG_TULIP
267 268  
268 269  
include/configs/PM826.h
Diff comments   View file @ 53cf943
... ... @@ -316,6 +316,7 @@
316 316 #ifdef CONFIG_PCI
317 317 #define CONFIG_PCI_PNP
318 318 #define CONFIG_EEPRO100
  319 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
319 320 #endif
320 321  
321 322 /*
include/configs/PMC405.h
Diff comments   View file @ 53cf943
... ... @@ -128,6 +128,10 @@
128 128  
129 129 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
130 130  
  131 +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  132 +
  133 +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  134 +
131 135 /*-----------------------------------------------------------------------
132 136 * PCI stuff
133 137 *-----------------------------------------------------------------------
include/configs/Sandpoint8240.h
Diff comments   View file @ 53cf943
... ... @@ -82,6 +82,7 @@
82 82 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
83 83  
84 84 #define CONFIG_EEPRO100
  85 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
85 86  
86 87 #define PCI_ENET0_IOADDR 0x80000000
87 88 #define PCI_ENET0_MEMADDR 0x80000000
include/configs/Sandpoint8245.h
Diff comments   View file @ 53cf943
... ... @@ -81,6 +81,7 @@
81 81 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
82 82  
83 83 #define CONFIG_EEPRO100
  84 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
84 85 #define CONFIG_NATSEMI
85 86 #define CONFIG_NS8382X
86 87  
include/configs/sc520_spunk.h
Diff comments   View file @ 53cf943
... ... @@ -36,7 +36,7 @@
36 36 #define CONFIG_X86 1 /* This is a X86 CPU */
37 37 #define CONFIG_SC520 1 /* Include support for AMD SC520 */
38 38  
39   -#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
  39 +#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
40 40 #define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
41 41 #define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */
42 42  
... ... @@ -71,7 +71,7 @@
71 71  
72 72 #define CONFIG_BOOTDELAY 15
73 73 #define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
74   -#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
  74 +#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
75 75  
76 76 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
77 77 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
78 78  
79 79  
... ... @@ -123,15 +123,15 @@
123 123 #define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */
124 124 #define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */
125 125 #define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */
126   -
127 126  
  127 +
128 128 /* allow to overwrite serial and ethaddr */
129 129 #define CONFIG_ENV_OVERWRITE
130 130  
131 131  
132 132 #if 0
133 133 /* Environment in flash */
134   -#define CFG_ENV_IS_IN_FLASH 1
  134 +#define CFG_ENV_IS_IN_FLASH 1
135 135 # define CFG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */
136 136 # define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */
137 137 # define CFG_ENV_OFFSET 0
... ... @@ -143,7 +143,7 @@
143 143 # define CONFIG_SPI
144 144 # define CONFIG_SPI_X 1
145 145 # define CFG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */
146   -# define CFG_ENV_OFFSET 0x1c00
  146 +# define CFG_ENV_OFFSET 0x1c00
147 147  
148 148 #endif
149 149  
... ... @@ -155,6 +155,7 @@
155 155 */
156 156 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
157 157 #define CONFIG_EEPRO100
  158 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
158 159  
159 160 /************************************************************
160 161 * IDE/ATA stuff
... ... @@ -204,8 +205,8 @@
204 205 #define CONFIG_PCI_SCAN_SHOW
205 206  
206 207 #define CFG_FIRST_PCI_IRQ 9
207   -#define CFG_SECOND_PCI_IRQ 10
208   -#define CFG_THIRD_PCI_IRQ 11
  208 +#define CFG_SECOND_PCI_IRQ 10
  209 +#define CFG_THIRD_PCI_IRQ 11
209 210 #define CFG_FORTH_PCI_IRQ 12
210 211  
211 212  
include/configs/utx8245.h
Diff comments   View file @ 53cf943
... ... @@ -125,6 +125,7 @@
125 125 #define CONFIG_PCI_SCAN_SHOW
126 126 #define CONFIG_NET_MULTI
127 127 #define CONFIG_EEPRO100
  128 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
128 129 #define CONFIG_EEPRO100_SROM_WRITE
129 130  
130 131 #define PCI_ENET0_IOADDR 0xF0000000