Add support for KVME080 board

Patch by Sangmoon Kim, 18 Aug 2005

Add support for KVME080 board
Patch by Sangmoon Kim, 18 Aug 2005
Wolfgang Denk
1 parent 8623c11e08
Showing 12 changed files with 1026 additions and 3 deletions Side-by-side Diff
CHANGELOG
CREDITS
MAINTAINERS
MAKEALL
Makefile
board/etin/kvme080/Makefile
board/etin/kvme080/config.mk
board/etin/kvme080/kvme080.c
board/etin/kvme080/multiverse.c
board/etin/kvme080/multiverse.h
board/etin/kvme080/u-boot.lds
include/configs/kvme080.h
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
  
+* Add support for KVME080 board
+  Patch by Sangmoon Kim, 18 Aug 2005
+
 * Fix MIPS LE build problem
   Patch by Matej Kupljen, 10 Aug 2005
  
@@ -233,6 +233,7 @@
 N: Sangmoon Kim
 E: dogoil@etinsys.com
 D: Support for debris board
+D: Support for KVME080 board
  
 N: Frederick W. Klatt
 E: fred.klatt@windriver.com
@@ -197,6 +197,7 @@
 Sangmoon Kim <dogoil@etinsys.com>
  
 	debris			MPC8245
+	KVME080			MPC8245
  
 Thomas Lange <thomas@corelatus.se>
  
@@ -95,9 +95,9 @@
 LIST_824x="	\
 	A3000		barco		BMW		CPC45		\
 	CU824		debris		eXalion		HIDDEN_DRAGON	\
-	MOUSSE		MUSENKI		MVBLUE		OXC		\
-	PN62		Sandpoint8240	Sandpoint8245	sbc8240		\
-	SL8245		utx8245						\
+	kvme080		MOUSSE		MUSENKI		MVBLUE		\
+	OXC		PN62		Sandpoint8240	Sandpoint8245	\
+	sbc8240		SL8245		utx8245				\
 "
  
 #########################################################################
@@ -1063,6 +1063,9 @@
 HIDDEN_DRAGON_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
  
+kvme080_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x kvme080 etin
+
 MOUSSE_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x mousse
  
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o multiverse.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
+#
+# (C) Copyright 2005
+# Sangmoon, Etin Systems, dogoil@etinsys.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# KVME080 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	puts ("Board: KVME080\n");
+	return 0;
+}
+
+unsigned long setdram(int m, int row, int col, int bank)
+{
+	int i;
+	unsigned long start, end;
+	uint32_t mccr1;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+long int initdram(int board_type)
+{
+	unsigned int msr;
+	long int size = 0;
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
+	mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
+	mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
+	mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
+	mtmsr(msr);
+
+	if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
+		size = 0x20000000;	/* 512MB */
+	else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+		size = 0x10000000;	/* 256MB */
+	else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+		size = 0x10000000;	/* 256MB */
+	else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+		size = 0x08000000;	/* 128MB */
+	else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+		size = 0x08000000;	/* 128MB */
+	else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
+		size = 0x04000000;	/* 64MB */
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT2L, CFG_IBAT2L);
+	mtspr(IBAT2U, CFG_IBAT2U);
+	mtspr(DBAT2L, CFG_DBAT2L);
+	mtspr(DBAT2U, CFG_DBAT2U);
+	mtmsr(msr);
+
+	return size;
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_early_init_f(void)
+{
+	*(volatile unsigned char *)(0xff080120) = 0xfb;
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	unsigned int msr;
+
+	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
+	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
+	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_IR | MSR_DR));
+	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtmsr(msr);
+
+	return 0;
+}
+
+extern int multiverse_init(void);
+
+int misc_init_r(void)
+{
+	multiverse_init();
+	return 0;
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*) dest;
+	volatile uchar *s = (volatile uchar*) src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+	return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*)dest;
+	volatile uchar *s = (volatile uchar*)src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+}
+/*
+ * multiverse.c
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ *	    dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "multiverse.h"
+
+static unsigned long vme_asi_addr;
+static unsigned long vme_iack_addr;
+static unsigned long pci_reg_addr;
+static unsigned long vme_reg_addr;
+
+int multiv_reset(unsigned long base)
+{
+	writeb(0x09, base + VME_SLAVE32_AM);
+	writeb(0x39, base + VME_SLAVE24_AM);
+	writeb(0x29, base + VME_SLAVE16_AM);
+	writeb(0x2f, base + VME_SLAVE_REG_AM);
+	writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
+	writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
+	writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
+#ifdef A32_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
+				base + VME_SLAVE32_MASK);
+		writeb(0x01, base + VME_SLAVE32_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE32_MASK);
+		writeb(0x00, base + VME_SLAVE32_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE32_MASK);
+	writeb(0x00, base + VME_SLAVE32_EN);
+#endif
+#ifdef A24_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
+				base + VME_SLAVE24_MASK);
+		writeb(0x01, base + VME_SLAVE24_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE24_MASK);
+		writeb(0x00, base + VME_SLAVE24_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE24_MASK);
+	writeb(0x00, base + VME_SLAVE24_EN);
+#endif
+#ifdef A16_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
+				base + VME_SLAVE16_MASK);
+		writeb(0x01, base + VME_SLAVE16_EN);
+	} else {
+		writeb(0xff, base + VME_SLAVE16_MASK);
+		writeb(0x00, base + VME_SLAVE16_EN);
+	}
+#else
+	writeb(0xff, base + VME_SLAVE16_MASK);
+	writeb(0x00, base + VME_SLAVE16_EN);
+#endif
+#ifdef REG_SLV_WINDOW
+	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+		writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
+				base + VME_SLAVE_REG_MASK);
+		writeb(0x01, base + VME_SLAVE_REG_EN);
+	} else {
+		writeb(0xf8, base + VME_SLAVE_REG_MASK);
+	}
+#else
+	writeb(0xf8, base + VME_SLAVE_REG_MASK);
+#endif
+	writeb(0x09, base + VME_MASTER32_AM);
+	writeb(0x39, base + VME_MASTER24_AM);
+	writeb(0x29, base + VME_MASTER16_AM);
+	writeb(0x2f, base + VME_MASTER_REG_AM);
+	writel(0x00000000, base + VME_RMW_ADRS);
+	writeb(0x00, base + VME_IRQ);
+	writeb(0x00, base + VME_INT_EN);
+	writel(0x00000000, base + VME_IRQ1_REG);
+	writel(0x00000000, base + VME_IRQ2_REG);
+	writel(0x00000000, base + VME_IRQ3_REG);
+	writel(0x00000000, base + VME_IRQ4_REG);
+	writel(0x00000000, base + VME_IRQ5_REG);
+	writel(0x00000000, base + VME_IRQ6_REG);
+	writel(0x00000000, base + VME_IRQ7_REG);
+	return 0;
+}
+
+void multiv_auto_slot_id(unsigned long base)
+{
+	unsigned int vector;
+	int slot_id = 1;
+	if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
+		*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
+		writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
+		writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
+				base + VME_CTRL);
+		while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
+		if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
+			while (readb(base + VME_INT) & 0x04) {
+				vector = *(volatile unsigned int*)
+					(vme_iack_addr + VME_IACK2);
+				*(unsigned char*)(vme_asi_addr + 0x7ffff)
+					= (slot_id << 3) & 0xff;
+				slot_id ++;
+				if (slot_id > 31)
+					break;
+			}
+		}
+	}
+}
+
+int multiverse_init(void)
+{
+	int i;
+	pci_dev_t pdev;
+	unsigned int bar[6];
+
+	pdev = pci_find_device(0x1895, 0x0001, 0);
+
+	if (pdev == 0)
+		return -1;
+
+	for (i = 0; i < 6; i++)
+		pci_read_config_dword (pdev,
+				PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
+
+	pci_reg_addr = bar[0];
+	vme_reg_addr = bar[1] + 0x00F00000;
+	vme_iack_addr = bar[1] + 0x00200000;
+	vme_asi_addr = bar[3];
+
+	pci_write_config_dword (pdev, PCI_COMMAND,
+		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	writel(0xFF000000, pci_reg_addr + P_TA1);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL1);
+	writel(0xf0000000, pci_reg_addr + P_TA2);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL2);
+	writel(0xF1000000, pci_reg_addr + P_TA3);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL3);
+	writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
+	writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
+	writel(0x04, pci_reg_addr + P_IMG_CTRL5);
+
+	writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
+	writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
+	writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL1);
+
+	writel(0xF0000000, pci_reg_addr + W_BA2);
+	writel(0xFF000000, pci_reg_addr + W_AM2);
+	writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL2);
+
+	writel(0xFF000000, pci_reg_addr + W_BA3);
+	writel(0xFF000000, pci_reg_addr + W_AM3);
+	writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
+	writel(0x04, pci_reg_addr + W_IMG_CTRL3);
+
+	writel(0x00000001, pci_reg_addr + W_ERR_CS);
+	writel(0x00000001, pci_reg_addr + P_ERR_CS);
+
+	multiv_reset(vme_reg_addr);
+	writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
+		vme_reg_addr + VME_CTRL);
+
+	multiv_auto_slot_id(vme_reg_addr);
+
+	return 0;
+}
+/*
+ * multiverse.h
+ *
+ * VME driver for Multiverse
+ *
+ * Author : Sangmoon Kim
+ *	    dogoil@etinsys.com
+ *
+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MULTIVERSE_H__
+#define __MULTIVERSE_H__
+
+#define VME_A32_MSTR_BUS	0x90000000
+#define VME_A32_MSTR_SIZE	0x01000000
+
+#define VME_A32_SLV_SIZE	0x01000000
+
+#define VME_A32_SLV_BUS		0x90000000
+#define VME_A24_SLV_BUS		0x00000000
+#define VME_A16_SLV_BUS		0x00000000
+
+#define VME_A32_SLV_LOCAL	0x00000000
+#define VME_A24_SLV_LOCAL	0x00000000
+#define VME_A16_SLV_LOCAL	0x00000000
+
+#define A32_SLV_WINDOW
+#undef	A24_SLV_WINDOW
+#undef	A16_SLV_WINDOW
+#undef	REG_SLV_WINDOW
+
+/* PCI Registers */
+
+#define P_IMG_CTRL0		0x100
+#define P_BA0			0x104
+#define P_AM0			0x108
+#define P_TA0			0x10C
+#define P_IMG_CTRL1		0x110
+#define P_BA1			0x114
+#define P_AM1			0x118
+#define P_TA1			0x11C
+#define P_IMG_CTRL2		0x120
+#define P_BA2			0x124
+#define P_AM2			0x128
+#define P_TA2			0x12C
+#define P_IMG_CTRL3		0x130
+#define P_BA3			0x134
+#define P_AM3			0x138
+#define P_TA3			0x13C
+#define P_IMG_CTRL4		0x140
+#define P_BA4			0x144
+#define P_AM4			0x148
+#define P_TA4			0x14C
+#define P_IMG_CTRL5		0x150
+#define P_BA5			0x154
+#define P_AM5			0x158
+#define P_TA5			0x15C
+#define P_ERR_CS		0x160
+#define P_ERR_ADDR		0x164
+#define P_ERR_DATA		0x168
+
+#define WB_CONF_SPC_BAR		0x180
+#define W_IMG_CTRL1		0x184
+#define W_BA1			0x188
+#define W_AM1			0x18C
+#define W_TA1			0x190
+#define W_IMG_CTRL2		0x194
+#define W_BA2			0x198
+#define W_AM2			0x19C
+#define W_TA2			0x1A0
+#define W_IMG_CTRL3		0x1A4
+#define W_BA3			0x1A8
+#define W_AM3			0x1AC
+#define W_TA3			0x1B0
+#define W_IMG_CTRL4		0x1B4
+#define W_BA4			0x1B8
+#define W_AM4			0x1BC
+#define W_TA4			0x1C0
+#define W_IMG_CTRL5		0x1C4
+#define W_BA5			0x1C8
+#define W_AM5			0x1CC
+#define W_TA5			0x1D0
+#define W_ERR_CS		0x1D4
+#define W_ERR_ADDR		0x1D8
+#define W_ERR_DATA		0x1DC
+#define CNF_ADDR		0x1E0
+#define CNF_DATA		0x1E4
+#define INT_ACK			0x1E8
+#define ICR			0x1EC
+#define ISR			0x1F0
+
+/* VME registers */
+
+#define VME_SLAVE32_AM		0x03
+#define VME_SLAVE24_AM		0x02
+#define VME_SLAVE16_AM		0x01
+#define VME_SLAVE_REG_AM	0x00
+#define VME_SLAVE32_A		0x07
+#define VME_SLAVE24_A		0x06
+#define VME_SLAVE16_A		0x05
+#define VME_SLAVE_REG_A		0x04
+#define VME_SLAVE32_MASK	0x0B
+#define VME_SLAVE24_MASK	0x0A
+#define VME_SLAVE16_MASK	0x09
+#define VME_SLAVE_REG_MASK	0x08
+#define VME_SLAVE32_EN		0x0F
+#define VME_SLAVE24_EN		0x0E
+#define VME_SLAVE16_EN		0x0D
+#define VME_SLAVE_REG_EN	0x0C
+#define VME_MASTER32_AM		0x13
+#define VME_MASTER24_AM		0x12
+#define VME_MASTER16_AM		0x11
+#define VME_MASTER_REG_AM	0x10
+#define VME_RMW_ADRS		0x14
+#define VME_MBOX		0x18
+#define VME_STATUS		0x1E
+#define VME_CTRL		0x1C
+#define VME_IRQ			0x20
+#define VME_INT_EN		0x21
+#define VME_INT			0x22
+#define VME_IRQ1_REG		0x24
+#define VME_IRQ2_REG		0x28
+#define VME_IRQ3_REG		0x2C
+#define VME_IRQ4_REG		0x30
+#define VME_IRQ5_REG		0x34
+#define VME_IRQ6_REG		0x38
+#define VME_IRQ7_REG		0x3C
+
+/* VME control register */
+
+#define VME_CTRL_BRDRST		0x01
+#define VME_CTRL_SYSRST		0x02
+#define VME_CTRL_RMW		0x04
+#define VME_CTRL_SHORT_D	0x08
+#define VME_CTRL_SYSFAIL	0x10
+#define VME_CTRL_VOWN		0x20
+#define VME_CTRL_A16_REG_MODE	0x40
+
+/* VME status register */
+
+#define VME_STATUS_SYSCON	0x01
+#define VME_STATUS_SYSFAIL	0x02
+#define VME_STATUS_ACFAIL	0x04
+#define VME_STATUS_SYSRST	0x08
+#define VME_STATUS_VOWN		0x10
+
+/* Interrupt types */
+
+#define LVL1			0x0002
+#define LVL2			0x0004
+#define LVL3			0x0008
+#define LVL4			0x0010
+#define LVL5			0x0020
+#define LVL6			0x0040
+#define LVL7			0x0080
+#define MULTIVERSE_INTI_INT	0x0100
+#define MULTIVERSE_WB_INT	0x0200
+#define MULTIVERSE_PCI_INT	0x0400
+
+/* interrupt acknowledge */
+
+#define VME_IACK1		0x04
+#define VME_IACK2		0x08
+#define VME_IACK3		0x0c
+#define VME_IACK4		0x10
+#define VME_IACK5		0x14
+#define VME_IACK6		0x18
+#define VME_IACK7		0x1c
+
+#endif /* __MULTIVERSE_H__ */
+/*
+ * (C) Copyright 2001-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_KVME080		1
+
+#define CONFIG_CONS_INDEX	1
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.0.1
+
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,115200 " \
+	"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
+	"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
+	"kvme080:eth0:none " \
+	"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
+
+#define CONFIG_BOOTCOMMAND \
+	"tftp 800000 kvme080/uImage; " \
+	"bootm 800000"
+
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_LOADS_ECHO	1
+#undef	CFG_LOADS_BAUD_CHANGE
+
+#undef	CONFIG_WATCHDOG
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS164x
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_ASKENV	| \
+				  CFG_CMD_CACHE		| \
+				  CFG_CMD_DATE		| \
+				  CFG_CMD_DHCP		| \
+				  CFG_CMD_DIAG		| \
+				  CFG_CMD_EEPROM	| \
+				  CFG_CMD_ELF		| \
+				  CFG_CMD_I2C		| \
+				  CFG_CMD_JFFS2		| \
+				  CFG_CMD_NFS		| \
+				  CFG_CMD_PCI		| \
+				  CFG_CMD_PING		| \
+				  CFG_CMD_SDRAM		| \
+				  CFG_CMD_SNTP)
+
+#define CONFIG_NETCONSOLE
+
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE		CFG_CBSIZE
+
+#define CFG_MEMTEST_START	0x00400000
+#define CFG_MEMTEST_END		0x07C00000
+
+#define CFG_LOAD_ADDR		0x00100000
+#define CFG_HZ			1000
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x7C000000
+#define CFG_EUMB_ADDR		0xFC000000
+#define CFG_NVRAM_BASE_ADDR	0xFF000000
+#define CFG_NS16550_COM1	0xFF080000
+#define CFG_NS16550_COM2	0xFF080010
+#define CFG_NS16550_COM3	0xFF080020
+#define CFG_NS16550_COM4	0xFF080030
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#define CFG_MAX_RAM_SIZE	0x20000000
+#define CFG_FLASH_SIZE		(16 * 1024 * 1024)
+#define CFG_NVRAM_SIZE		0x7FFF8
+
+#define CONFIG_VERY_BIG_RAM
+
+#define CFG_MONITOR_LEN		0x00040000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_LEN		(512 << 10)
+
+#define CFG_BOOTMAPSZ		(8 << 20)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_PROTECTION
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECT_CLEAR
+
+#define CFG_MAX_FLASH_BANKS	1
+#define CFG_MAX_FLASH_SECT	256
+
+#define CFG_FLASH_ERASE_TOUT	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+
+#define CFG_ENV_IS_IN_NVRAM	1
+#define CONFIG_ENV_OVERWRITE	1
+#define CFG_NVRAM_ACCESS_ROUTINE
+#define CFG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+#define CFG_ENV_SIZE		0x400
+#define CFG_ENV_OFFSET		0
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		14745600
+
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define CFG_RX_ETH_BUFFER	8
+
+#define CONFIG_HARD_I2C		1
+#define CFG_I2C_SPEED		400000
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR		0x57
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_CLK_FREQ	33333333
+
+#define CFG_CACHELINE_SIZE	32
+#if CONFIG_COMMANDS & CFG_CMD_KGDB
+#  define CFG_CACHELINE_SHIFT	5
+#endif
+
+#define CFG_DLL_EXTEND		0x00
+#define CFG_PCI_HOLD_DEL	0x20
+
+#define CFG_ROMNAL		15
+#define CFG_ROMFAL		31
+
+#define CFG_REFINT		430
+
+#define CFG_DBUS_SIZE2		1
+
+#define CFG_BSTOPRE		121
+#define CFG_REFREC		8
+#define CFG_RDLAT		4
+#define CFG_PRETOACT		3
+#define CFG_ACTTOPRE		5
+#define CFG_ACTORW		3
+#define CFG_SDMODE_CAS_LAT	3
+#define CFG_SDMODE_WRAP		0
+
+#define CFG_REGISTERD_TYPE_BUFFER	1
+#define CFG_EXTROM			1
+#define CFG_REGDIMM			0
+
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(0x4000000 - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x04000000
+#define CFG_BANK1_END		(0x8000000 - 1)
+#define CFG_BANK1_ENABLE	1
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+
+#define CFG_BANK_ENABLE		0x03
+
+#define CFG_ODCR		0x75
+#define CFG_PGMAX		0x32
+
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+#define BOOTFLAG_COLD	0x01
+#define BOOTFLAG_WARM	0x02
+
+#endif	/* __CONFIG_H */
...	...	@@ -2,6 +2,9 @@
2	2	Changes since U-Boot 1.1.4:
3	3	======================================================================
4	4
	5	+* Add support for KVME080 board
	6	+ Patch by Sangmoon Kim, 18 Aug 2005
	7	+
5	8	* Fix MIPS LE build problem
6	9	Patch by Matej Kupljen, 10 Aug 2005
7	10
...	...	@@ -233,6 +233,7 @@
233	233	N: Sangmoon Kim
234	234	E: dogoil@etinsys.com
235	235	D: Support for debris board
	236	+D: Support for KVME080 board
236	237
237	238	N: Frederick W. Klatt
238	239	E: fred.klatt@windriver.com
...	...	@@ -197,6 +197,7 @@
197	197	Sangmoon Kim <dogoil@etinsys.com>
198	198
199	199	debris MPC8245
	200	+ KVME080 MPC8245
200	201
201	202	Thomas Lange <thomas@corelatus.se>
202	203
...	...	@@ -95,9 +95,9 @@
95	95	LIST_824x=" \
96	96	A3000 barco BMW CPC45 \
97	97	CU824 debris eXalion HIDDEN_DRAGON \
98		- MOUSSE MUSENKI MVBLUE OXC \
99		- PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
100		- SL8245 utx8245 \
	98	+ kvme080 MOUSSE MUSENKI MVBLUE \
	99	+ OXC PN62 Sandpoint8240 Sandpoint8245 \
	100	+ sbc8240 SL8245 utx8245 \
101	101	"
102	102
103	103	#########################################################################
...	...	@@ -1063,6 +1063,9 @@
1063	1063	HIDDEN_DRAGON_config: unconfig
1064	1064	@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
1065	1065
	1066	+kvme080_config: unconfig
	1067	+ @./mkconfig $(@:_config=) ppc mpc824x kvme080 etin
	1068	+
1066	1069	MOUSSE_config: unconfig
1067	1070	@./mkconfig $(@:_config=) ppc mpc824x mousse
1068	1071
	1	+#
	2	+# (C) Copyright 2000-2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = lib$(BOARD).a
	27	+
	28	+OBJS = $(BOARD).o multiverse.o
	29	+
	30	+$(LIB): .depend $(OBJS)
	31	+ $(AR) crv $@ $(OBJS)
	32	+
	33	+#########################################################################
	34	+
	35	+.depend: Makefile $(OBJS:.o=.c)
	36	+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
	37	+
	38	+sinclude .depend
	39	+
	40	+#########################################################################
	1	+#
	2	+# (C) Copyright 2005
	3	+# Sangmoon, Etin Systems, dogoil@etinsys.com.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+#
	25	+# KVME080 board
	26	+#
	27	+
	28	+TEXT_BASE = 0xFFF00000
	29	+
	30	+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
	1	+/*
	2	+ * (C) Copyright 2005
	3	+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <mpc824x.h>
	26	+#include <pci.h>
	27	+#include <i2c.h>
	28	+#include <asm/processor.h>
	29	+
	30	+int checkboard(void)
	31	+{
	32	+ puts ("Board: KVME080\n");
	33	+ return 0;
	34	+}
	35	+
	36	+unsigned long setdram(int m, int row, int col, int bank)
	37	+{
	38	+ int i;
	39	+ unsigned long start, end;
	40	+ uint32_t mccr1;
	41	+ uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	42	+ uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	43	+ uint8_t mber = 0;
	44	+
	45	+ CONFIG_READ_WORD(MCCR1, mccr1);
	46	+ mccr1 &= 0xffff0000;
	47	+
	48	+ start = CFG_SDRAM_BASE;
	49	+ end = start + (1 << (col + row + 3) ) * bank - 1;
	50	+
	51	+ for (i = 0; i < m; i++) {
	52	+ mccr1 \|= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
	53	+ if (i < 4) {
	54	+ msar1 \|= ((start >> 20) & 0xff) << i * 8;
	55	+ emsar1 \|= ((start >> 28) & 0xff) << i * 8;
	56	+ mear1 \|= ((end >> 20) & 0xff) << i * 8;
	57	+ emear1 \|= ((end >> 28) & 0xff) << i * 8;
	58	+ } else {
	59	+ msar2 \|= ((start >> 20) & 0xff) << (i-4) * 8;
	60	+ emsar2 \|= ((start >> 28) & 0xff) << (i-4) * 8;
	61	+ mear2 \|= ((end >> 20) & 0xff) << (i-4) * 8;
	62	+ emear2 \|= ((end >> 28) & 0xff) << (i-4) * 8;
	63	+ }
	64	+ mber \|= 1 << i;
	65	+ start += (1 << (col + row + 3) ) * bank;
	66	+ end += (1 << (col + row + 3) ) * bank;
	67	+ }
	68	+ for (; i < 8; i++) {
	69	+ if (i < 4) {
	70	+ msar1 \|= 0xff << i * 8;
	71	+ emsar1 \|= 0x30 << i * 8;
	72	+ mear1 \|= 0xff << i * 8;
	73	+ emear1 \|= 0x30 << i * 8;
	74	+ } else {
	75	+ msar2 \|= 0xff << (i-4) * 8;
	76	+ emsar2 \|= 0x30 << (i-4) * 8;
	77	+ mear2 \|= 0xff << (i-4) * 8;
	78	+ emear2 \|= 0x30 << (i-4) * 8;
	79	+ }
	80	+ }
	81	+
	82	+ CONFIG_WRITE_WORD(MCCR1, mccr1);
	83	+ CONFIG_WRITE_WORD(MSAR1, msar1);
	84	+ CONFIG_WRITE_WORD(EMSAR1, emsar1);
	85	+ CONFIG_WRITE_WORD(MEAR1, mear1);
	86	+ CONFIG_WRITE_WORD(EMEAR1, emear1);
	87	+ CONFIG_WRITE_WORD(MSAR2, msar2);
	88	+ CONFIG_WRITE_WORD(EMSAR2, emsar2);
	89	+ CONFIG_WRITE_WORD(MEAR2, mear2);
	90	+ CONFIG_WRITE_WORD(EMEAR2, emear2);
	91	+ CONFIG_WRITE_BYTE(MBER, mber);
	92	+
	93	+ return (1 << (col + row + 3) ) * bank * m;
	94	+}
	95	+
	96	+long int initdram(int board_type)
	97	+{
	98	+ unsigned int msr;
	99	+ long int size = 0;
	100	+
	101	+ msr = mfmsr();
	102	+ mtmsr(msr & ~(MSR_IR \| MSR_DR));
	103	+ mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
	104	+ mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
	105	+ mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
	106	+ mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
	107	+ mtmsr(msr);
	108	+
	109	+ if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
	110	+ size = 0x20000000; /* 512MB */
	111	+ else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
	112	+ size = 0x10000000; /* 256MB */
	113	+ else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
	114	+ size = 0x10000000; /* 256MB */
	115	+ else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
	116	+ size = 0x08000000; /* 128MB */
	117	+ else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
	118	+ size = 0x08000000; /* 128MB */
	119	+ else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
	120	+ size = 0x04000000; /* 64MB */
	121	+
	122	+ msr = mfmsr();
	123	+ mtmsr(msr & ~(MSR_IR \| MSR_DR));
	124	+ mtspr(IBAT2L, CFG_IBAT2L);
	125	+ mtspr(IBAT2U, CFG_IBAT2U);
	126	+ mtspr(DBAT2L, CFG_DBAT2L);
	127	+ mtspr(DBAT2U, CFG_DBAT2U);
	128	+ mtmsr(msr);
	129	+
	130	+ return size;
	131	+}
	132	+
	133	+struct pci_controller hose;
	134	+
	135	+void pci_init_board(void)
	136	+{
	137	+ pci_mpc824x_init(&hose);
	138	+}
	139	+
	140	+int board_early_init_f(void)
	141	+{
	142	+ (volatile unsigned char )(0xff080120) = 0xfb;
	143	+
	144	+ return 0;
	145	+}
	146	+
	147	+int board_early_init_r(void)
	148	+{
	149	+ unsigned int msr;
	150	+
	151	+ CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
	152	+ CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
	153	+ CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
	154	+
	155	+ msr = mfmsr();
	156	+ mtmsr(msr & ~(MSR_IR \| MSR_DR));
	157	+ mtspr(IBAT1L, 0x70000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT);
	158	+ mtspr(IBAT1U, 0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP);
	159	+ mtspr(DBAT1L, 0x70000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT);
	160	+ mtspr(DBAT1U, 0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP);
	161	+ mtmsr(msr);
	162	+
	163	+ return 0;
	164	+}
	165	+
	166	+extern int multiverse_init(void);
	167	+
	168	+int misc_init_r(void)
	169	+{
	170	+ multiverse_init();
	171	+ return 0;
	172	+}
	173	+
	174	+void nvram_read(void dest, const long src, size_t count)
	175	+{
	176	+ volatile uchar d = (volatile uchar) dest;
	177	+ volatile uchar s = (volatile uchar) src;
	178	+ while(count--) {
	179	+ d++ = s++;
	180	+ asm volatile("sync");
	181	+ }
	182	+ return dest;
	183	+}
	184	+
	185	+void nvram_write(long dest, const void *src, size_t count)
	186	+{
	187	+ volatile uchar d = (volatile uchar)dest;
	188	+ volatile uchar s = (volatile uchar)src;
	189	+ while(count--) {
	190	+ d++ = s++;
	191	+ asm volatile("sync");
	192	+ }
	193	+}
	1	+/*
	2	+ * multiverse.c
	3	+ *
	4	+ * VME driver for Multiverse
	5	+ *
	6	+ * Author : Sangmoon Kim
	7	+ * dogoil@etinsys.com
	8	+ *
	9	+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or modify it
	12	+ * under the terms of the GNU General Public License as published by the
	13	+ * Free Software Foundation; either version 2 of the License, or (at your
	14	+ * option) any later version.
	15	+ */
	16	+
	17	+#include <common.h>
	18	+#include <asm/io.h>
	19	+#include <pci.h>
	20	+
	21	+#include "multiverse.h"
	22	+
	23	+static unsigned long vme_asi_addr;
	24	+static unsigned long vme_iack_addr;
	25	+static unsigned long pci_reg_addr;
	26	+static unsigned long vme_reg_addr;
	27	+
	28	+int multiv_reset(unsigned long base)
	29	+{
	30	+ writeb(0x09, base + VME_SLAVE32_AM);
	31	+ writeb(0x39, base + VME_SLAVE24_AM);
	32	+ writeb(0x29, base + VME_SLAVE16_AM);
	33	+ writeb(0x2f, base + VME_SLAVE_REG_AM);
	34	+ writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
	35	+ writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
	36	+ writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
	37	+#ifdef A32_SLV_WINDOW
	38	+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
	39	+ writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
	40	+ base + VME_SLAVE32_MASK);
	41	+ writeb(0x01, base + VME_SLAVE32_EN);
	42	+ } else {
	43	+ writeb(0xff, base + VME_SLAVE32_MASK);
	44	+ writeb(0x00, base + VME_SLAVE32_EN);
	45	+ }
	46	+#else
	47	+ writeb(0xff, base + VME_SLAVE32_MASK);
	48	+ writeb(0x00, base + VME_SLAVE32_EN);
	49	+#endif
	50	+#ifdef A24_SLV_WINDOW
	51	+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
	52	+ writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
	53	+ base + VME_SLAVE24_MASK);
	54	+ writeb(0x01, base + VME_SLAVE24_EN);
	55	+ } else {
	56	+ writeb(0xff, base + VME_SLAVE24_MASK);
	57	+ writeb(0x00, base + VME_SLAVE24_EN);
	58	+ }
	59	+#else
	60	+ writeb(0xff, base + VME_SLAVE24_MASK);
	61	+ writeb(0x00, base + VME_SLAVE24_EN);
	62	+#endif
	63	+#ifdef A16_SLV_WINDOW
	64	+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
	65	+ writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
	66	+ base + VME_SLAVE16_MASK);
	67	+ writeb(0x01, base + VME_SLAVE16_EN);
	68	+ } else {
	69	+ writeb(0xff, base + VME_SLAVE16_MASK);
	70	+ writeb(0x00, base + VME_SLAVE16_EN);
	71	+ }
	72	+#else
	73	+ writeb(0xff, base + VME_SLAVE16_MASK);
	74	+ writeb(0x00, base + VME_SLAVE16_EN);
	75	+#endif
	76	+#ifdef REG_SLV_WINDOW
	77	+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
	78	+ writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
	79	+ base + VME_SLAVE_REG_MASK);
	80	+ writeb(0x01, base + VME_SLAVE_REG_EN);
	81	+ } else {
	82	+ writeb(0xf8, base + VME_SLAVE_REG_MASK);
	83	+ }
	84	+#else
	85	+ writeb(0xf8, base + VME_SLAVE_REG_MASK);
	86	+#endif
	87	+ writeb(0x09, base + VME_MASTER32_AM);
	88	+ writeb(0x39, base + VME_MASTER24_AM);
	89	+ writeb(0x29, base + VME_MASTER16_AM);
	90	+ writeb(0x2f, base + VME_MASTER_REG_AM);
	91	+ writel(0x00000000, base + VME_RMW_ADRS);
	92	+ writeb(0x00, base + VME_IRQ);
	93	+ writeb(0x00, base + VME_INT_EN);
	94	+ writel(0x00000000, base + VME_IRQ1_REG);
	95	+ writel(0x00000000, base + VME_IRQ2_REG);
	96	+ writel(0x00000000, base + VME_IRQ3_REG);
	97	+ writel(0x00000000, base + VME_IRQ4_REG);
	98	+ writel(0x00000000, base + VME_IRQ5_REG);
	99	+ writel(0x00000000, base + VME_IRQ6_REG);
	100	+ writel(0x00000000, base + VME_IRQ7_REG);
	101	+ return 0;
	102	+}
	103	+
	104	+void multiv_auto_slot_id(unsigned long base)
	105	+{
	106	+ unsigned int vector;
	107	+ int slot_id = 1;
	108	+ if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
	109	+ (volatile unsigned int)(base + VME_IRQ2_REG) = 0xfe;
	110	+ writeb(readb(base + VME_IRQ) \| 0x04, base + VME_IRQ);
	111	+ writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
	112	+ base + VME_CTRL);
	113	+ while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
	114	+ if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
	115	+ while (readb(base + VME_INT) & 0x04) {
	116	+ vector = (volatile unsigned int)
	117	+ (vme_iack_addr + VME_IACK2);
	118	+ (unsigned char)(vme_asi_addr + 0x7ffff)
	119	+ = (slot_id << 3) & 0xff;
	120	+ slot_id ++;
	121	+ if (slot_id > 31)
	122	+ break;
	123	+ }
	124	+ }
	125	+ }
	126	+}
	127	+
	128	+int multiverse_init(void)
	129	+{
	130	+ int i;
	131	+ pci_dev_t pdev;
	132	+ unsigned int bar[6];
	133	+
	134	+ pdev = pci_find_device(0x1895, 0x0001, 0);
	135	+
	136	+ if (pdev == 0)
	137	+ return -1;
	138	+
	139	+ for (i = 0; i < 6; i++)
	140	+ pci_read_config_dword (pdev,
	141	+ PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
	142	+
	143	+ pci_reg_addr = bar[0];
	144	+ vme_reg_addr = bar[1] + 0x00F00000;
	145	+ vme_iack_addr = bar[1] + 0x00200000;
	146	+ vme_asi_addr = bar[3];
	147	+
	148	+ pci_write_config_dword (pdev, PCI_COMMAND,
	149	+ PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	150	+
	151	+ writel(0xFF000000, pci_reg_addr + P_TA1);
	152	+ writel(0x04, pci_reg_addr + P_IMG_CTRL1);
	153	+ writel(0xf0000000, pci_reg_addr + P_TA2);
	154	+ writel(0x04, pci_reg_addr + P_IMG_CTRL2);
	155	+ writel(0xF1000000, pci_reg_addr + P_TA3);
	156	+ writel(0x04, pci_reg_addr + P_IMG_CTRL3);
	157	+ writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
	158	+ writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
	159	+ writel(0x04, pci_reg_addr + P_IMG_CTRL5);
	160	+
	161	+ writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
	162	+ writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
	163	+ writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
	164	+ writel(0x04, pci_reg_addr + W_IMG_CTRL1);
	165	+
	166	+ writel(0xF0000000, pci_reg_addr + W_BA2);
	167	+ writel(0xFF000000, pci_reg_addr + W_AM2);
	168	+ writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
	169	+ writel(0x04, pci_reg_addr + W_IMG_CTRL2);
	170	+
	171	+ writel(0xFF000000, pci_reg_addr + W_BA3);
	172	+ writel(0xFF000000, pci_reg_addr + W_AM3);
	173	+ writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
	174	+ writel(0x04, pci_reg_addr + W_IMG_CTRL3);
	175	+
	176	+ writel(0x00000001, pci_reg_addr + W_ERR_CS);
	177	+ writel(0x00000001, pci_reg_addr + P_ERR_CS);
	178	+
	179	+ multiv_reset(vme_reg_addr);
	180	+ writeb(readb(vme_reg_addr + VME_CTRL) \| VME_CTRL_SHORT_D,
	181	+ vme_reg_addr + VME_CTRL);
	182	+
	183	+ multiv_auto_slot_id(vme_reg_addr);
	184	+
	185	+ return 0;
	186	+}
	1	+/*
	2	+ * multiverse.h
	3	+ *
	4	+ * VME driver for Multiverse
	5	+ *
	6	+ * Author : Sangmoon Kim
	7	+ * dogoil@etinsys.com
	8	+ *
	9	+ * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or modify it
	12	+ * under the terms of the GNU General Public License as published by the
	13	+ * Free Software Foundation; either version 2 of the License, or (at your
	14	+ * option) any later version.
	15	+ */
	16	+
	17	+#ifndef __MULTIVERSE_H__
	18	+#define __MULTIVERSE_H__
	19	+
	20	+#define VME_A32_MSTR_BUS 0x90000000
	21	+#define VME_A32_MSTR_SIZE 0x01000000
	22	+
	23	+#define VME_A32_SLV_SIZE 0x01000000
	24	+
	25	+#define VME_A32_SLV_BUS 0x90000000
	26	+#define VME_A24_SLV_BUS 0x00000000
	27	+#define VME_A16_SLV_BUS 0x00000000
	28	+
	29	+#define VME_A32_SLV_LOCAL 0x00000000
	30	+#define VME_A24_SLV_LOCAL 0x00000000
	31	+#define VME_A16_SLV_LOCAL 0x00000000
	32	+
	33	+#define A32_SLV_WINDOW
	34	+#undef A24_SLV_WINDOW
	35	+#undef A16_SLV_WINDOW
	36	+#undef REG_SLV_WINDOW
	37	+
	38	+/* PCI Registers */
	39	+
	40	+#define P_IMG_CTRL0 0x100
	41	+#define P_BA0 0x104
	42	+#define P_AM0 0x108
	43	+#define P_TA0 0x10C
	44	+#define P_IMG_CTRL1 0x110
	45	+#define P_BA1 0x114
	46	+#define P_AM1 0x118
	47	+#define P_TA1 0x11C
	48	+#define P_IMG_CTRL2 0x120
	49	+#define P_BA2 0x124
	50	+#define P_AM2 0x128
	51	+#define P_TA2 0x12C
	52	+#define P_IMG_CTRL3 0x130
	53	+#define P_BA3 0x134
	54	+#define P_AM3 0x138
	55	+#define P_TA3 0x13C
	56	+#define P_IMG_CTRL4 0x140
	57	+#define P_BA4 0x144
	58	+#define P_AM4 0x148
	59	+#define P_TA4 0x14C
	60	+#define P_IMG_CTRL5 0x150
	61	+#define P_BA5 0x154
	62	+#define P_AM5 0x158
	63	+#define P_TA5 0x15C
	64	+#define P_ERR_CS 0x160
	65	+#define P_ERR_ADDR 0x164
	66	+#define P_ERR_DATA 0x168
	67	+
	68	+#define WB_CONF_SPC_BAR 0x180
	69	+#define W_IMG_CTRL1 0x184
	70	+#define W_BA1 0x188
	71	+#define W_AM1 0x18C
	72	+#define W_TA1 0x190
	73	+#define W_IMG_CTRL2 0x194
	74	+#define W_BA2 0x198
	75	+#define W_AM2 0x19C
	76	+#define W_TA2 0x1A0
	77	+#define W_IMG_CTRL3 0x1A4
	78	+#define W_BA3 0x1A8
	79	+#define W_AM3 0x1AC
	80	+#define W_TA3 0x1B0
	81	+#define W_IMG_CTRL4 0x1B4
	82	+#define W_BA4 0x1B8
	83	+#define W_AM4 0x1BC
	84	+#define W_TA4 0x1C0
	85	+#define W_IMG_CTRL5 0x1C4
	86	+#define W_BA5 0x1C8
	87	+#define W_AM5 0x1CC
	88	+#define W_TA5 0x1D0
	89	+#define W_ERR_CS 0x1D4
	90	+#define W_ERR_ADDR 0x1D8
	91	+#define W_ERR_DATA 0x1DC
	92	+#define CNF_ADDR 0x1E0
	93	+#define CNF_DATA 0x1E4
	94	+#define INT_ACK 0x1E8
	95	+#define ICR 0x1EC
	96	+#define ISR 0x1F0
	97	+
	98	+/* VME registers */
	99	+
	100	+#define VME_SLAVE32_AM 0x03
	101	+#define VME_SLAVE24_AM 0x02
	102	+#define VME_SLAVE16_AM 0x01
	103	+#define VME_SLAVE_REG_AM 0x00
	104	+#define VME_SLAVE32_A 0x07
	105	+#define VME_SLAVE24_A 0x06
	106	+#define VME_SLAVE16_A 0x05
	107	+#define VME_SLAVE_REG_A 0x04
	108	+#define VME_SLAVE32_MASK 0x0B
	109	+#define VME_SLAVE24_MASK 0x0A
	110	+#define VME_SLAVE16_MASK 0x09
	111	+#define VME_SLAVE_REG_MASK 0x08
	112	+#define VME_SLAVE32_EN 0x0F
	113	+#define VME_SLAVE24_EN 0x0E
	114	+#define VME_SLAVE16_EN 0x0D
	115	+#define VME_SLAVE_REG_EN 0x0C
	116	+#define VME_MASTER32_AM 0x13
	117	+#define VME_MASTER24_AM 0x12
	118	+#define VME_MASTER16_AM 0x11
	119	+#define VME_MASTER_REG_AM 0x10
	120	+#define VME_RMW_ADRS 0x14
	121	+#define VME_MBOX 0x18
	122	+#define VME_STATUS 0x1E
	123	+#define VME_CTRL 0x1C
	124	+#define VME_IRQ 0x20
	125	+#define VME_INT_EN 0x21
	126	+#define VME_INT 0x22
	127	+#define VME_IRQ1_REG 0x24
	128	+#define VME_IRQ2_REG 0x28
	129	+#define VME_IRQ3_REG 0x2C
	130	+#define VME_IRQ4_REG 0x30
	131	+#define VME_IRQ5_REG 0x34
	132	+#define VME_IRQ6_REG 0x38
	133	+#define VME_IRQ7_REG 0x3C
	134	+
	135	+/* VME control register */
	136	+
	137	+#define VME_CTRL_BRDRST 0x01
	138	+#define VME_CTRL_SYSRST 0x02
	139	+#define VME_CTRL_RMW 0x04
	140	+#define VME_CTRL_SHORT_D 0x08
	141	+#define VME_CTRL_SYSFAIL 0x10
	142	+#define VME_CTRL_VOWN 0x20
	143	+#define VME_CTRL_A16_REG_MODE 0x40
	144	+
	145	+/* VME status register */
	146	+
	147	+#define VME_STATUS_SYSCON 0x01
	148	+#define VME_STATUS_SYSFAIL 0x02
	149	+#define VME_STATUS_ACFAIL 0x04
	150	+#define VME_STATUS_SYSRST 0x08
	151	+#define VME_STATUS_VOWN 0x10
	152	+
	153	+/* Interrupt types */
	154	+
	155	+#define LVL1 0x0002
	156	+#define LVL2 0x0004
	157	+#define LVL3 0x0008
	158	+#define LVL4 0x0010
	159	+#define LVL5 0x0020
	160	+#define LVL6 0x0040
	161	+#define LVL7 0x0080
	162	+#define MULTIVERSE_INTI_INT 0x0100
	163	+#define MULTIVERSE_WB_INT 0x0200
	164	+#define MULTIVERSE_PCI_INT 0x0400
	165	+
	166	+/* interrupt acknowledge */
	167	+
	168	+#define VME_IACK1 0x04
	169	+#define VME_IACK2 0x08
	170	+#define VME_IACK3 0x0c
	171	+#define VME_IACK4 0x10
	172	+#define VME_IACK5 0x14
	173	+#define VME_IACK6 0x18
	174	+#define VME_IACK7 0x1c
	175	+
	176	+#endif /* __MULTIVERSE_H__ */