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Commit 544d97e9aa904e489f9e87bae6a6b41cb031cbe9

Authored by Wolfgang Denk
1 parent 6f984adb31
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

PCU_E: remove code for yet another corpse 

The PCU_E board has long reached EOL, and support for it is no longer
relevant in current versions of U-Boot.  Remove it.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 15 changed files with 9 additions and 2163 deletions Side-by-side Diff

... ... @@ -117,7 +117,6 @@
117 117 c2mon MPC855
118 118 hermes MPC860
119 119 lwmon MPC823
120   - pcu_e MPC855
121 120  
122 121 CU824 MPC8240
123 122 Sandpoint8240 MPC8240
... ... @@ -1781,7 +1781,7 @@
1781 1781  
1782 1782 ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
1783 1783 HERMES, IP860, RPXlite, LWMON, LANTEC,
1784   - PCU_E, FLAGADM, TQM8260
  1784 + FLAGADM, TQM8260
1785 1785  
1786 1786 - Error Recovery:
1787 1787 CONFIG_PANIC_HANG
arch/m68k/lib/board.c
Diff comments   View file @ 544d97e
... ... @@ -73,10 +73,6 @@
73 73  
74 74 static char *failed = "*** failed ***\n";
75 75  
76   -#ifdef CONFIG_PCU_E
77   -extern flash_info_t flash_info[];
78   -#endif
79   -
80 76 #include <environment.h>
81 77  
82 78 extern ulong __init_end;
arch/powerpc/cpu/mpc8xx/cpu_init.c
Diff comments   View file @ 544d97e
... ... @@ -156,7 +156,6 @@
156 156 defined(CONFIG_IVMS8) || \
157 157 defined(CONFIG_LWMON) || \
158 158 defined(CONFIG_MHPC) || \
159   - defined(CONFIG_PCU_E) || \
160 159 defined(CONFIG_R360MPI) || \
161 160 defined(CONFIG_RMU) || \
162 161 defined(CONFIG_RPXCLASSIC) || \
arch/powerpc/lib/board.c
Diff comments   View file @ 544d97e
... ... @@ -107,7 +107,7 @@
107 107  
108 108 static char *failed = "*** failed ***\n";
109 109  
110   -#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
  110 +#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
111 111 extern flash_info_t flash_info[];
112 112 #endif
113 113  
... ... @@ -735,7 +735,7 @@
735 735 #endif
736 736  
737 737  
738   -# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
  738 +# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
739 739 /* flash mapped at end of memory map */
740 740 bd->bi_flashoffset = TEXT_BASE + flash_size;
741 741 # elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
board/siemens/pcu_e/Makefile
View file @ 544d97e
1   -#
2   -# (C) Copyright 2001-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).a
27   -
28   -COBJS = $(BOARD).o flash.o
29   -
30   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31   -OBJS := $(addprefix $(obj),$(COBJS))
32   -SOBJS := $(addprefix $(obj),$(SOBJS))
33   -
34   -$(LIB): $(obj).depend $(OBJS)
35   - $(AR) $(ARFLAGS) $@ $(OBJS)
36   -
37   -#########################################################################
38   -
39   -# defines $(obj).depend target
40   -include $(SRCTREE)/rules.mk
41   -
42   -sinclude $(obj).depend
43   -
44   -#########################################################################
board/siemens/pcu_e/config.mk
View file @ 544d97e
1   -#
2   -# (C) Copyright 2001
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -#
25   -# Siemens PCU E Boards
26   -#
27   -
28   -TEXT_BASE = 0xFFF00000
board/siemens/pcu_e/flash.c
View file @ 544d97e
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -#include <mpc8xx.h>
26   -
27   -#if defined(CONFIG_ENV_IS_IN_FLASH)
28   -# ifndef CONFIG_ENV_ADDR
29   -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
30   -# endif
31   -# ifndef CONFIG_ENV_SIZE
32   -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
33   -# endif
34   -# ifndef CONFIG_ENV_SECT_SIZE
35   -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
36   -# endif
37   -#endif
38   -
39   -/*---------------------------------------------------------------------*/
40   -#undef DEBUG_FLASH
41   -
42   -#ifdef DEBUG_FLASH
43   -#define DEBUGF(fmt,args...) printf(fmt ,##args)
44   -#else
45   -#define DEBUGF(fmt,args...)
46   -#endif
47   -/*---------------------------------------------------------------------*/
48   -
49   -
50   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
51   -
52   -/*-----------------------------------------------------------------------
53   - * Functions
54   - */
55   -static ulong flash_get_size (vu_long *addr, flash_info_t *info);
56   -static int write_data (flash_info_t *info, ulong dest, ulong data);
57   -static void flash_get_offsets (ulong base, flash_info_t *info);
58   -
59   -/*-----------------------------------------------------------------------
60   - *
61   - * The PCU E uses an address map where flash banks are aligned top
62   - * down, so that the "first" flash bank ends at top of memory, and
63   - * the monitor entry point is at address (0xFFF00100). The second
64   - * flash bank is mapped immediately below bank 0.
65   - *
66   - * This is NOT in conformance to the "official" memory map!
67   - *
68   - */
69   -
70   -#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \
71   - - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) )
72   -
73   -/*-----------------------------------------------------------------------
74   - */
75   -
76   -unsigned long flash_init (void)
77   -{
78   - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
79   - volatile memctl8xx_t *memctl = &immap->im_memctl;
80   - unsigned long base, size_b0, size_b1;
81   - int i;
82   -
83   - /* Init: no FLASHes known */
84   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
85   - flash_info[i].flash_id = FLASH_UNKNOWN;
86   - }
87   -
88   - /* Static FLASH Bank configuration here - FIXME XXX */
89   -
90   - /*
91   - * Warning:
92   - *
93   - * Since the PCU E memory map assigns flash banks top down,
94   - * we swap the numbering later if both banks are equipped,
95   - * so they look like a contiguous area of memory.
96   - */
97   - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
98   -
99   - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
100   -
101   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
102   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
103   - size_b0, size_b0<<20);
104   - }
105   -
106   - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM);
107   - size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]);
108   -
109   - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1);
110   -
111   - if (size_b1 > size_b0) {
112   - printf ("## ERROR: "
113   - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
114   - size_b1, size_b1<<20,
115   - size_b0, size_b0<<20
116   - );
117   - flash_info[0].flash_id = FLASH_UNKNOWN;
118   - flash_info[1].flash_id = FLASH_UNKNOWN;
119   - flash_info[0].sector_count = -1;
120   - flash_info[1].sector_count = -1;
121   - flash_info[0].size = 0;
122   - flash_info[1].size = 0;
123   - return (0);
124   - }
125   -
126   - DEBUGF ("## Before remap: "
127   - "BR0: 0x%08x OR0: 0x%08x "
128   - "BR6: 0x%08x OR6: 0x%08x\n",
129   - memctl->memc_br0, memctl->memc_or0,
130   - memctl->memc_br6, memctl->memc_or6);
131   -
132   - /* Remap FLASH according to real size */
133   - base = 0 - size_b0;
134   - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
135   - memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
136   -
137   - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
138   - memctl->memc_br0, memctl->memc_or0);
139   -
140   - /* Re-do sizing to get full correct info */
141   - size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
142   - base = 0 - size_b0;
143   -
144   - flash_info[0].size = size_b0;
145   -
146   - flash_get_offsets (base, &flash_info[0]);
147   -
148   - /* monitor protection ON by default */
149   - flash_protect(FLAG_PROTECT_SET,
150   - PCU_MONITOR_BASE,
151   - PCU_MONITOR_BASE+monitor_flash_len-1,
152   - &flash_info[0]);
153   -
154   -#ifdef CONFIG_ENV_IS_IN_FLASH
155   - /* ENV protection ON by default */
156   - flash_protect(FLAG_PROTECT_SET,
157   - CONFIG_ENV_ADDR,
158   - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
159   - &flash_info[0]);
160   -#endif
161   -
162   - if (size_b1) {
163   - flash_info_t tmp_info;
164   -
165   - memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
166   - memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
167   - BR_PS_16 | BR_MS_GPCM | BR_V;
168   -
169   - DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n",
170   - memctl->memc_br6, memctl->memc_or6);
171   -
172   - /* Re-do sizing to get full correct info */
173   - size_b1 = flash_get_size((vu_long *)(base - size_b1),
174   - &flash_info[1]);
175   - base -= size_b1;
176   -
177   - flash_get_offsets (base, &flash_info[1]);
178   -
179   - flash_info[1].size = size_b1;
180   -
181   -#ifdef CONFIG_ENV_IS_IN_FLASH
182   - /* ENV protection ON by default */
183   - flash_protect(FLAG_PROTECT_SET,
184   - CONFIG_ENV_ADDR,
185   - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
186   - &flash_info[1]);
187   -#endif
188   - /*
189   - * Swap bank numbers so that addresses are in ascending order
190   - */
191   - tmp_info = flash_info[0];
192   - flash_info[0] = flash_info[1];
193   - flash_info[1] = tmp_info;
194   - } else {
195   - memctl->memc_br1 = 0; /* invalidate bank */
196   -
197   - flash_info[1].flash_id = FLASH_UNKNOWN;
198   - flash_info[1].sector_count = -1;
199   - }
200   -
201   -
202   - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
203   -
204   - return (size_b0 + size_b1);
205   -}
206   -
207   -/*-----------------------------------------------------------------------
208   - */
209   -static void flash_get_offsets (ulong base, flash_info_t *info)
210   -{
211   - int i;
212   - short n;
213   -
214   - if (info->flash_id == FLASH_UNKNOWN) {
215   - return;
216   - }
217   -
218   - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
219   - return;
220   - }
221   -
222   - switch (info->flash_id & FLASH_TYPEMASK) {
223   - case FLASH_AMDL322T:
224   - case FLASH_AMDL323T:
225   - case FLASH_AMDL324T:
226   - /* set sector offsets for top boot block type */
227   -
228   - base += info->size;
229   - i = info->sector_count;
230   - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
231   - base -= 8 << 10;
232   - --i;
233   - info->start[i] = base;
234   - }
235   - while (i > 0) { /* 64k regular sectors */
236   - base -= 64 << 10;
237   - --i;
238   - info->start[i] = base;
239   - }
240   - return;
241   - case FLASH_AMDL322B:
242   - case FLASH_AMDL323B:
243   - case FLASH_AMDL324B:
244   - /* set sector offsets for bottom boot block type */
245   - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
246   - info->start[i] = base;
247   - base += 8 << 10;
248   - }
249   - while (base < info->size) { /* 64k regular sectors */
250   - info->start[i] = base;
251   - base += 64 << 10;
252   - ++i;
253   - }
254   - return;
255   - case FLASH_AMDL640:
256   - /* set sector offsets for dual boot block type */
257   - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
258   - info->start[i] = base;
259   - base += 8 << 10;
260   - }
261   - n = info->sector_count - 8;
262   - while (i < n) { /* 64k regular sectors */
263   - info->start[i] = base;
264   - base += 64 << 10;
265   - ++i;
266   - }
267   - while (i < info->sector_count) { /* 8 x 8k boot sectors */
268   - info->start[i] = base;
269   - base += 8 << 10;
270   - ++i;
271   - }
272   - return;
273   - default:
274   - return;
275   - }
276   - /* NOTREACHED */
277   -}
278   -
279   -/*-----------------------------------------------------------------------
280   - */
281   -void flash_print_info (flash_info_t *info)
282   -{
283   - int i;
284   -
285   - if (info->flash_id == FLASH_UNKNOWN) {
286   - printf ("missing or unknown FLASH type\n");
287   - return;
288   - }
289   -
290   - switch (info->flash_id & FLASH_VENDMASK) {
291   - case FLASH_MAN_AMD: printf ("AMD "); break;
292   - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
293   - default: printf ("Unknown Vendor "); break;
294   - }
295   -
296   - switch (info->flash_id & FLASH_TYPEMASK) {
297   - case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
298   - break;
299   - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n");
300   - break;
301   - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
302   - break;
303   - case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n");
304   - break;
305   - case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
306   - break;
307   - case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
308   - break;
309   - case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
310   - break;
311   - default: printf ("Unknown Chip Type 0x%lX\n",
312   - info->flash_id);
313   - break;
314   - }
315   -
316   - printf (" Size: %ld MB in %d Sectors\n",
317   - info->size >> 20, info->sector_count);
318   -
319   - printf (" Sector Start Addresses:");
320   - for (i=0; i<info->sector_count; ++i) {
321   - if ((i % 5) == 0)
322   - printf ("\n ");
323   - printf (" %08lX%s",
324   - info->start[i],
325   - info->protect[i] ? " (RO)" : " "
326   - );
327   - }
328   - printf ("\n");
329   - return;
330   -}
331   -
332   -/*-----------------------------------------------------------------------
333   - */
334   -
335   -
336   -/*-----------------------------------------------------------------------
337   - */
338   -
339   -/*
340   - * The following code cannot be run from FLASH!
341   - */
342   -
343   -static ulong flash_get_size (vu_long *addr, flash_info_t *info)
344   -{
345   - short i;
346   - ushort value;
347   - vu_short *saddr = (vu_short *)addr;
348   -
349   - /* Write auto select command: read Manufacturer ID */
350   - saddr[0x0555] = 0x00AA;
351   - saddr[0x02AA] = 0x0055;
352   - saddr[0x0555] = 0x0090;
353   -
354   - value = saddr[0];
355   -
356   - DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value);
357   -
358   - switch (value) {
359   - case (AMD_MANUFACT & 0xFFFF):
360   - info->flash_id = FLASH_MAN_AMD;
361   - break;
362   - case (FUJ_MANUFACT & 0xFFFF):
363   - info->flash_id = FLASH_MAN_FUJ;
364   - break;
365   - default:
366   - DEBUGF("Unknown Manufacturer ID\n");
367   - info->flash_id = FLASH_UNKNOWN;
368   - info->sector_count = 0;
369   - info->size = 0;
370   - return (0); /* no or unknown flash */
371   - }
372   -
373   - value = saddr[1]; /* device ID */
374   -
375   - DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
376   -
377   - switch (value) {
378   -
379   - case (AMD_ID_DL322T & 0xFFFF):
380   - info->flash_id += FLASH_AMDL322T;
381   - info->sector_count = 71;
382   - info->size = 0x00400000;
383   - break; /* => 8 MB */
384   -
385   - case (AMD_ID_DL322B & 0xFFFF):
386   - info->flash_id += FLASH_AMDL322B;
387   - info->sector_count = 71;
388   - info->size = 0x00400000;
389   - break; /* => 8 MB */
390   -
391   - case (AMD_ID_DL323T & 0xFFFF):
392   - info->flash_id += FLASH_AMDL323T;
393   - info->sector_count = 71;
394   - info->size = 0x00400000;
395   - break; /* => 8 MB */
396   -
397   - case (AMD_ID_DL323B & 0xFFFF):
398   - info->flash_id += FLASH_AMDL323B;
399   - info->sector_count = 71;
400   - info->size = 0x00400000;
401   - break; /* => 8 MB */
402   -
403   - case (AMD_ID_DL324T & 0xFFFF):
404   - info->flash_id += FLASH_AMDL324T;
405   - info->sector_count = 71;
406   - info->size = 0x00400000;
407   - break; /* => 8 MB */
408   -
409   - case (AMD_ID_DL324B & 0xFFFF):
410   - info->flash_id += FLASH_AMDL324B;
411   - info->sector_count = 71;
412   - info->size = 0x00400000;
413   - break; /* => 8 MB */
414   - case (AMD_ID_DL640 & 0xFFFF):
415   - info->flash_id += FLASH_AMDL640;
416   - info->sector_count = 142;
417   - info->size = 0x00800000;
418   - break;
419   - default:
420   - DEBUGF("Unknown Device ID\n");
421   - info->flash_id = FLASH_UNKNOWN;
422   - return (0); /* => no or unknown flash */
423   -
424   - }
425   -
426   - flash_get_offsets ((ulong)addr, info);
427   -
428   - /* check for protected sectors */
429   - for (i = 0; i < info->sector_count; i++) {
430   -#if 0
431   - /* read sector protection at sector address, (A7 .. A0) = 0x02 */
432   - /* D0 = 1 if protected */
433   - saddr = (vu_short *)(info->start[i]);
434   - info->protect[i] = saddr[2] & 1;
435   -#else
436   - info->protect[i] =0;
437   -#endif
438   - }
439   -
440   - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
441   - printf ("** ERROR: sector count %d > max (%d) **\n",
442   - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
443   - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
444   - }
445   -
446   - saddr = (vu_short *)info->start[0];
447   - *saddr = 0x00F0; /* restore read mode */
448   -
449   - return (info->size);
450   -}
451   -
452   -
453   -/*-----------------------------------------------------------------------
454   - */
455   -
456   -int flash_erase (flash_info_t *info, int s_first, int s_last)
457   -{
458   - vu_short *addr = (vu_short*)(info->start[0]);
459   - int flag, prot, sect, l_sect;
460   - ulong start, now, last;
461   -
462   - if ((s_first < 0) || (s_first > s_last)) {
463   - if (info->flash_id == FLASH_UNKNOWN) {
464   - printf ("- missing\n");
465   - } else {
466   - printf ("- no sectors to erase\n");
467   - }
468   - return 1;
469   - }
470   -
471   - if ((info->flash_id == FLASH_UNKNOWN) ||
472   - (info->flash_id > FLASH_AMD_COMP)) {
473   - printf ("Can't erase unknown flash type %08lx - aborted\n",
474   - info->flash_id);
475   - return 1;
476   - }
477   -
478   - prot = 0;
479   - for (sect=s_first; sect<=s_last; ++sect) {
480   - if (info->protect[sect]) {
481   - prot++;
482   - }
483   - }
484   -
485   - if (prot) {
486   - printf ("- Warning: %d protected sectors will not be erased!\n",
487   - prot);
488   - } else {
489   - printf ("\n");
490   - }
491   -
492   - l_sect = -1;
493   -
494   - /* Disable interrupts which might cause a timeout here */
495   - flag = disable_interrupts();
496   -
497   - addr[0x0555] = 0x00AA;
498   - addr[0x02AA] = 0x0055;
499   - addr[0x0555] = 0x0080;
500   - addr[0x0555] = 0x00AA;
501   - addr[0x02AA] = 0x0055;
502   -
503   - /* Start erase on unprotected sectors */
504   - for (sect = s_first; sect<=s_last; sect++) {
505   - if (info->protect[sect] == 0) { /* not protected */
506   - addr = (vu_short*)(info->start[sect]);
507   - addr[0] = 0x0030;
508   - l_sect = sect;
509   - }
510   - }
511   -
512   - /* re-enable interrupts if necessary */
513   - if (flag)
514   - enable_interrupts();
515   -
516   - /* wait at least 80us - let's wait 1 ms */
517   - udelay (1000);
518   -
519   - /*
520   - * We wait for the last triggered sector
521   - */
522   - if (l_sect < 0)
523   - goto DONE;
524   -
525   - start = get_timer (0);
526   - last = start;
527   - addr = (vu_short*)(info->start[l_sect]);
528   - while ((addr[0] & 0x0080) != 0x0080) {
529   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
530   - printf ("Timeout\n");
531   - return 1;
532   - }
533   - /* show that we're waiting */
534   - if ((now - last) > 1000) { /* every second */
535   - putc ('.');
536   - last = now;
537   - }
538   - }
539   -
540   -DONE:
541   - /* reset to read mode */
542   - addr = (vu_short *)info->start[0];
543   - addr[0] = 0x00F0; /* reset bank */
544   -
545   - printf (" done\n");
546   - return 0;
547   -}
548   -
549   -/*-----------------------------------------------------------------------
550   - * Copy memory to flash, returns:
551   - * 0 - OK
552   - * 1 - write timeout
553   - * 2 - Flash not erased
554   - */
555   -
556   -#define FLASH_WIDTH 2 /* flash bus width in bytes */
557   -
558   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
559   -{
560   - ulong cp, wp, data;
561   - int i, l, rc;
562   -
563   - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
564   -
565   - /*
566   - * handle unaligned start bytes
567   - */
568   - if ((l = addr - wp) != 0) {
569   - data = 0;
570   - for (i=0, cp=wp; i<l; ++i, ++cp) {
571   - data = (data << 8) | (*(uchar *)cp);
572   - }
573   - for (; i<FLASH_WIDTH && cnt>0; ++i) {
574   - data = (data << 8) | *src++;
575   - --cnt;
576   - ++cp;
577   - }
578   - for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
579   - data = (data << 8) | (*(uchar *)cp);
580   - }
581   -
582   - if ((rc = write_data(info, wp, data)) != 0) {
583   - return (rc);
584   - }
585   - wp += FLASH_WIDTH;
586   - }
587   -
588   - /*
589   - * handle FLASH_WIDTH aligned part
590   - */
591   - while (cnt >= FLASH_WIDTH) {
592   - data = 0;
593   - for (i=0; i<FLASH_WIDTH; ++i) {
594   - data = (data << 8) | *src++;
595   - }
596   - if ((rc = write_data(info, wp, data)) != 0) {
597   - return (rc);
598   - }
599   - wp += FLASH_WIDTH;
600   - cnt -= FLASH_WIDTH;
601   - }
602   -
603   - if (cnt == 0) {
604   - return (0);
605   - }
606   -
607   - /*
608   - * handle unaligned tail bytes
609   - */
610   - data = 0;
611   - for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
612   - data = (data << 8) | *src++;
613   - --cnt;
614   - }
615   - for (; i<FLASH_WIDTH; ++i, ++cp) {
616   - data = (data << 8) | (*(uchar *)cp);
617   - }
618   -
619   - return (write_data(info, wp, data));
620   -}
621   -
622   -/*-----------------------------------------------------------------------
623   - * Write a word to Flash, returns:
624   - * 0 - OK
625   - * 1 - write timeout
626   - * 2 - Flash not erased
627   - */
628   -static int write_data (flash_info_t *info, ulong dest, ulong data)
629   -{
630   - vu_short *addr = (vu_short*)(info->start[0]);
631   - vu_short *sdest = (vu_short *)dest;
632   - ushort sdata = (ushort)data;
633   - ushort sval;
634   - ulong start, passed;
635   - int flag, rc;
636   -
637   - /* Check if Flash is (sufficiently) erased */
638   - if ((*sdest & sdata) != sdata) {
639   - return (2);
640   - }
641   - /* Disable interrupts which might cause a timeout here */
642   - flag = disable_interrupts();
643   -
644   - addr[0x0555] = 0x00AA;
645   - addr[0x02AA] = 0x0055;
646   - addr[0x0555] = 0x00A0;
647   -
648   -#ifdef WORKAROUND_FOR_BROKEN_HARDWARE
649   - /* work around the timeout bugs */
650   - udelay(20);
651   -#endif
652   -
653   - *sdest = sdata;
654   -
655   - /* re-enable interrupts if necessary */
656   - if (flag)
657   - enable_interrupts();
658   -
659   - rc = 0;
660   - /* data polling for D7 */
661   - start = get_timer (0);
662   -
663   - for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) {
664   -
665   - sval = *sdest;
666   -
667   - if ((sval & 0x0080) == (sdata & 0x0080))
668   - break;
669   -
670   - if ((sval & 0x0020) == 0) /* DQ5: Timeout? */
671   - continue;
672   -
673   - sval = *sdest;
674   -
675   - if ((sval & 0x0080) != (sdata & 0x0080))
676   - rc = 1;
677   -
678   - break;
679   - }
680   -
681   - if (rc) {
682   - DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n",
683   - dest, sval, sdata);
684   - }
685   -
686   - if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) {
687   - DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
688   - dest, sval, sdata);
689   - rc = 1;
690   - }
691   -
692   - /* reset to read mode */
693   - addr = (vu_short *)info->start[0];
694   - addr[0] = 0x00F0; /* reset bank */
695   -
696   - return (rc);
697   -}
698   -
699   -/*-----------------------------------------------------------------------
700   - */
board/siemens/pcu_e/pcu_e.c
View file @ 544d97e
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <common.h>
25   -#include <mpc8xx.h>
26   -#include <commproc.h>
27   -#include <i2c.h>
28   -#include <command.h>
29   -
30   -/* ------------------------------------------------------------------------- */
31   -
32   -static long int dram_size (long int, long int *, long int);
33   -static void puma_status (void);
34   -static void puma_set_mode (int mode);
35   -static int puma_init_done (void);
36   -static void puma_load (ulong addr, ulong len);
37   -
38   -/* ------------------------------------------------------------------------- */
39   -
40   -#define _NOT_USED_ 0xFFFFFFFF
41   -
42   -/*
43   - * 50 MHz SDRAM access using UPM A
44   - */
45   -const uint sdram_table[] = {
46   - /*
47   - * Single Read. (Offset 0 in UPM RAM)
48   - */
49   - 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
50   - 0x1ffddc47, /* last */
51   - /*
52   - * SDRAM Initialization (offset 5 in UPM RAM)
53   - *
54   - * This is no UPM entry point. The following definition uses
55   - * the remaining space to establish an initialization
56   - * sequence, which is executed by a RUN command.
57   - *
58   - */
59   - 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
60   - /*
61   - * Burst Read. (Offset 8 in UPM RAM)
62   - */
63   - 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
64   - 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
65   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67   -
68   - /*
69   - * Single Write. (Offset 18 in UPM RAM)
70   - */
71   - 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
72   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73   - /*
74   - * Burst Write. (Offset 20 in UPM RAM)
75   - */
76   - 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
77   - 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
78   - _NOT_USED_,
79   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81   - /*
82   - * Refresh (Offset 30 in UPM RAM)
83   - */
84   - 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
85   - 0xfffffc84, 0xfffffc07, /* last */
86   - _NOT_USED_, _NOT_USED_,
87   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
88   - /*
89   - * Exception. (Offset 3c in UPM RAM)
90   - */
91   - 0x7ffffc07, /* last */
92   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
93   -};
94   -
95   -/* ------------------------------------------------------------------------- */
96   -
97   -/*
98   - * PUMA access using UPM B
99   - */
100   -const uint puma_table[] = {
101   - /*
102   - * Single Read. (Offset 0 in UPM RAM)
103   - */
104   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
105   - _NOT_USED_,
106   - /*
107   - * Precharge and MRS
108   - */
109   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
110   - /*
111   - * Burst Read. (Offset 8 in UPM RAM)
112   - */
113   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
116   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
117   - /*
118   - * Single Write. (Offset 18 in UPM RAM)
119   - */
120   - 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
121   - _NOT_USED_,
122   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
123   - /*
124   - * Burst Write. (Offset 20 in UPM RAM)
125   - */
126   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
127   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
128   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
129   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130   - /*
131   - * Refresh (Offset 30 in UPM RAM)
132   - */
133   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
134   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
135   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
136   - /*
137   - * Exception. (Offset 3c in UPM RAM)
138   - */
139   - 0x7ffffc07, /* last */
140   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
141   -};
142   -
143   -/* ------------------------------------------------------------------------- */
144   -
145   -
146   -/*
147   - * Check Board Identity:
148   - *
149   - */
150   -
151   -int checkboard (void)
152   -{
153   - puts ("Board: Siemens PCU E\n");
154   - return (0);
155   -}
156   -
157   -/* ------------------------------------------------------------------------- */
158   -
159   -phys_size_t initdram (int board_type)
160   -{
161   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
162   - volatile memctl8xx_t *memctl = &immr->im_memctl;
163   - long int size_b0, reg;
164   - int i;
165   -
166   - /*
167   - * Configure UPMA for SDRAM
168   - */
169   - upmconfig (UPMA, (uint *) sdram_table,
170   - sizeof (sdram_table) / sizeof (uint));
171   -
172   - memctl->memc_mptpr = CONFIG_SYS_MPTPR;
173   -
174   - /* burst length=4, burst type=sequential, CAS latency=2 */
175   - memctl->memc_mar = 0x00000088;
176   -
177   - /*
178   - * Map controller bank 2 to the SDRAM bank at preliminary address.
179   - */
180   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
181   - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
182   - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
183   -#else /* XXX */
184   - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
185   - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
186   -#endif /* XXX */
187   -
188   - /* initialize memory address register */
189   - memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */
190   -
191   - /* mode initialization (offset 5) */
192   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
193   - udelay (200); /* 0x8000A105 */
194   - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
195   -#else /* XXX */
196   - udelay (200); /* 0x80004105 */
197   - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
198   -#endif /* XXX */
199   -
200   - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
201   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
202   - udelay (1); /* 0x8000A830 */
203   - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
204   -#else /* XXX */
205   - udelay (1); /* 0x80004830 */
206   - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
207   -#endif /* XXX */
208   -
209   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
210   - udelay (1); /* 0x8000A106 */
211   - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
212   -#else /* XXX */
213   - udelay (1); /* 0x80004106 */
214   - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
215   -#endif /* XXX */
216   -
217   - reg = memctl->memc_mamr;
218   - reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
219   - reg |= MAMR_TLFA_4X; /* ... to 4x */
220   - reg |= MAMR_PTAE; /* enable refresh */
221   - memctl->memc_mamr = reg;
222   -
223   - udelay (200);
224   -
225   - /* Need at least 10 DRAM accesses to stabilize */
226   - for (i = 0; i < 10; ++i) {
227   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
228   - volatile unsigned long *addr =
229   - (volatile unsigned long *) SDRAM_BASE5_PRELIM;
230   -#else /* XXX */
231   - volatile unsigned long *addr =
232   - (volatile unsigned long *) SDRAM_BASE2_PRELIM;
233   -#endif /* XXX */
234   - unsigned long val;
235   -
236   - val = *(addr + i);
237   - *(addr + i) = val;
238   - }
239   -
240   - /*
241   - * Check Bank 0 Memory Size for re-configuration
242   - */
243   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
244   - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
245   -#else /* XXX */
246   - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
247   -#endif /* XXX */
248   -
249   - memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;
250   -
251   - /*
252   - * Final mapping:
253   - */
254   -
255   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
256   - memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
257   - memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
258   -#else /* XXX */
259   - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
260   - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
261   -#endif /* XXX */
262   - udelay (1000);
263   -
264   - /*
265   - * Configure UPMB for PUMA
266   - */
267   - upmconfig (UPMB, (uint *) puma_table,
268   - sizeof (puma_table) / sizeof (uint));
269   -
270   - return (size_b0);
271   -}
272   -
273   -/* ------------------------------------------------------------------------- */
274   -
275   -/*
276   - * Check memory range for valid RAM. A simple memory test determines
277   - * the actually available RAM size between addresses `base' and
278   - * `base + maxsize'. Some (not all) hardware errors are detected:
279   - * - short between address lines
280   - * - short between data lines
281   - */
282   -
283   -static long int dram_size (long int mamr_value, long int *base,
284   - long int maxsize)
285   -{
286   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
287   - volatile memctl8xx_t *memctl = &immr->im_memctl;
288   -
289   - memctl->memc_mamr = mamr_value;
290   -
291   - return (get_ram_size (base, maxsize));
292   -}
293   -
294   -/* ------------------------------------------------------------------------- */
295   -
296   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
297   -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
298   -#else /* XXX */
299   -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
300   - CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
301   -#endif /* XXX */
302   -
303   -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)
304   -
305   -void reset_phy (void)
306   -{
307   - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
308   - ulong value;
309   -
310   - /* Configure all needed port pins for GPIO */
311   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
312   -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
313   - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
314   -# else
315   - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */
316   -# endif
317   - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */
318   - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */
319   - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */
320   -#endif /* XXX */
321   - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
322   - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
323   -
324   - value = immr->im_cpm.cp_pbdat;
325   -
326   - /* Assert Powerdown and Reset signals */
327   - value |= CONFIG_SYS_PB_ETH_POWERDOWN;
328   - value &= ~(CONFIG_SYS_PB_ETH_RESET);
329   -
330   - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
331   -#if !PCU_E_WITH_SWAPPED_CS
332   -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
333   - value |= CONFIG_SYS_PB_ETH_MDDIS;
334   -# else
335   - value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
336   -# endif
337   -#endif
338   -#ifdef CONFIG_SYS_ETH_CFG1_VALUE
339   - value |= CONFIG_SYS_PB_ETH_CFG1;
340   -#else
341   - value &= ~(CONFIG_SYS_PB_ETH_CFG1);
342   -#endif
343   -#ifdef CONFIG_SYS_ETH_CFG2_VALUE
344   - value |= CONFIG_SYS_PB_ETH_CFG2;
345   -#else
346   - value &= ~(CONFIG_SYS_PB_ETH_CFG2);
347   -#endif
348   -#ifdef CONFIG_SYS_ETH_CFG3_VALUE
349   - value |= CONFIG_SYS_PB_ETH_CFG3;
350   -#else
351   - value &= ~(CONFIG_SYS_PB_ETH_CFG3);
352   -#endif
353   -
354   - /* Drive output signals to initial state */
355   - immr->im_cpm.cp_pbdat = value;
356   - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
357   - udelay (10000);
358   -
359   - /* De-assert Ethernet Powerdown */
360   - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
361   - udelay (10000);
362   -
363   - /* de-assert RESET signal of PHY */
364   - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
365   - udelay (1000);
366   -}
367   -
368   -/*-----------------------------------------------------------------------
369   - * Board Special Commands: access functions for "PUMA" FPGA
370   - */
371   -#if defined(CONFIG_CMD_BSP)
372   -
373   -#define PUMA_READ_MODE 0
374   -#define PUMA_LOAD_MODE 1
375   -
376   -int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
377   -{
378   - ulong addr, len;
379   -
380   - switch (argc) {
381   - case 2: /* PUMA reset */
382   - if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
383   - puma_status ();
384   - return 0;
385   - }
386   - break;
387   - case 4: /* PUMA load addr len */
388   - if (strcmp (argv[1], "load") != 0)
389   - break;
390   -
391   - addr = simple_strtoul (argv[2], NULL, 16);
392   - len = simple_strtoul (argv[3], NULL, 16);
393   -
394   - printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
395   - addr, len, len);
396   - puma_load (addr, len);
397   -
398   - return 0;
399   - default:
400   - break;
401   - }
402   - return cmd_usage(cmdtp);
403   -}
404   -
405   -U_BOOT_CMD (puma, 4, 1, do_puma,
406   - "access PUMA FPGA",
407   - "status - print PUMA status\n"
408   - "puma load addr len - load PUMA configuration data"
409   -);
410   -#endif
411   -
412   -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
413   -
414   -static void puma_set_mode (int mode)
415   -{
416   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
417   - volatile memctl8xx_t *memctl = &immr->im_memctl;
418   -
419   - /* disable PUMA in memory controller */
420   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
421   - memctl->memc_br3 = 0;
422   -#else /* XXX */
423   - memctl->memc_br4 = 0;
424   -#endif /* XXX */
425   -
426   - switch (mode) {
427   - case PUMA_READ_MODE:
428   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
429   - memctl->memc_or3 = PUMA_CONF_OR_READ;
430   - memctl->memc_br3 = PUMA_CONF_BR_READ;
431   -#else /* XXX */
432   - memctl->memc_or4 = PUMA_CONF_OR_READ;
433   - memctl->memc_br4 = PUMA_CONF_BR_READ;
434   -#endif /* XXX */
435   - break;
436   - case PUMA_LOAD_MODE:
437   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
438   - memctl->memc_or3 = PUMA_CONF_OR_LOAD;
439   - memctl->memc_br3 = PUMA_CONF_BR_LOAD;
440   -#else /* XXX */
441   - memctl->memc_or4 = PUMA_CONF_OR_READ;
442   - memctl->memc_br4 = PUMA_CONF_BR_READ;
443   -#endif /* XXX */
444   - break;
445   - }
446   -}
447   -
448   -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
449   -
450   -#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
451   -
452   -static void puma_load (ulong addr, ulong len)
453   -{
454   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
455   - volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
456   - uchar *data = (uchar *) addr;
457   - int i;
458   -
459   - /* align length */
460   - if (len & 1)
461   - ++len;
462   -
463   - /* Reset FPGA */
464   - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */
465   - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT);
466   - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
467   -
468   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
469   - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */
470   - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */
471   - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */
472   - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */
473   -#else
474   - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */
475   - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */
476   - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */
477   - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */
478   -#endif /* XXX */
479   - udelay (100);
480   -
481   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
482   - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */
483   -#else
484   - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */
485   -#endif /* XXX */
486   -
487   - /* wait until INIT indicates completion of reset */
488   - for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
489   - udelay (1000);
490   - if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
491   - break;
492   - }
493   - if (i == PUMA_INIT_TIMEOUT) {
494   - printf ("*** PUMA init timeout ***\n");
495   - return;
496   - }
497   -
498   - puma_set_mode (PUMA_LOAD_MODE);
499   -
500   - while (len--)
501   - *fpga_addr = *data++;
502   -
503   - puma_set_mode (PUMA_READ_MODE);
504   -
505   - puma_status ();
506   -}
507   -
508   -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
509   -
510   -static void puma_status (void)
511   -{
512   - /* Check state */
513   - printf ("PUMA initialization is %scomplete\n",
514   - puma_init_done ()? "" : "NOT ");
515   -}
516   -
517   -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
518   -
519   -static int puma_init_done (void)
520   -{
521   - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
522   -
523   - /* make sure pin is GPIO input */
524   - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
525   - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
526   - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
527   -
528   - return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
529   -}
530   -
531   -/* ------------------------------------------------------------------------- */
532   -
533   -int misc_init_r (void)
534   -{
535   - ulong addr = 0;
536   - ulong len = 0;
537   - char *s;
538   -
539   - printf ("PUMA: ");
540   - if (puma_init_done ()) {
541   - printf ("initialized\n");
542   - return 0;
543   - }
544   -
545   - if ((s = getenv ("puma_addr")) != NULL)
546   - addr = simple_strtoul (s, NULL, 16);
547   -
548   - if ((s = getenv ("puma_len")) != NULL)
549   - len = simple_strtoul (s, NULL, 16);
550   -
551   - if ((!addr) || (!len)) {
552   - printf ("net list undefined\n");
553   - return 0;
554   - }
555   -
556   - printf ("loading... ");
557   -
558   - puma_load (addr, len);
559   - return (0);
560   -}
561   -
562   -/* ------------------------------------------------------------------------- */
board/siemens/pcu_e/u-boot.lds
View file @ 544d97e
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -OUTPUT_ARCH(powerpc)
25   -/* Do we need any of these for elf?
26   - __DYNAMIC = 0; */
27   -SECTIONS
28   -{
29   - /* Read-only sections, merged into text segment: */
30   - . = + SIZEOF_HEADERS;
31   - .interp : { *(.interp) }
32   - .hash : { *(.hash) }
33   - .dynsym : { *(.dynsym) }
34   - .dynstr : { *(.dynstr) }
35   - .rel.text : { *(.rel.text) }
36   - .rela.text : { *(.rela.text) }
37   - .rel.data : { *(.rel.data) }
38   - .rela.data : { *(.rela.data) }
39   - .rel.rodata : { *(.rel.rodata) }
40   - .rela.rodata : { *(.rela.rodata) }
41   - .rel.got : { *(.rel.got) }
42   - .rela.got : { *(.rela.got) }
43   - .rel.ctors : { *(.rel.ctors) }
44   - .rela.ctors : { *(.rela.ctors) }
45   - .rel.dtors : { *(.rel.dtors) }
46   - .rela.dtors : { *(.rela.dtors) }
47   - .rel.bss : { *(.rel.bss) }
48   - .rela.bss : { *(.rela.bss) }
49   - .rel.plt : { *(.rel.plt) }
50   - .rela.plt : { *(.rela.plt) }
51   - .init : { *(.init) }
52   - .plt : { *(.plt) }
53   - .text :
54   - {
55   - arch/powerpc/cpu/mpc8xx/start.o (.text)
56   - common/env_embedded.o(.text)
57   - *(.text)
58   - *(.got1)
59   - }
60   - _etext = .;
61   - PROVIDE (etext = .);
62   - .rodata :
63   - {
64   - *(.eh_frame)
65   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
66   - }
67   - .fini : { *(.fini) } =0
68   - .ctors : { *(.ctors) }
69   - .dtors : { *(.dtors) }
70   -
71   - /* Read-write section, merged into data segment: */
72   - . = (. + 0x0FF) & 0xFFFFFF00;
73   - _erotext = .;
74   - PROVIDE (erotext = .);
75   - .reloc :
76   - {
77   - *(.got)
78   - _GOT2_TABLE_ = .;
79   - *(.got2)
80   - _FIXUP_TABLE_ = .;
81   - *(.fixup)
82   - }
83   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
84   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
85   -
86   - .data :
87   - {
88   - *(.data)
89   - *(.data1)
90   - *(.sdata)
91   - *(.sdata2)
92   - *(.dynamic)
93   - CONSTRUCTORS
94   - }
95   - _edata = .;
96   - PROVIDE (edata = .);
97   -
98   - . = .;
99   - __u_boot_cmd_start = .;
100   - .u_boot_cmd : { *(.u_boot_cmd) }
101   - __u_boot_cmd_end = .;
102   -
103   -
104   - . = .;
105   - __start___ex_table = .;
106   - __ex_table : { *(__ex_table) }
107   - __stop___ex_table = .;
108   -
109   - . = ALIGN(256);
110   - __init_begin = .;
111   - .text.init : { *(.text.init) }
112   - .data.init : { *(.data.init) }
113   - . = ALIGN(256);
114   - __init_end = .;
115   -
116   - __bss_start = .;
117   - .bss (NOLOAD) :
118   - {
119   - *(.sbss) *(.scommon)
120   - *(.dynbss)
121   - *(.bss)
122   - *(COMMON)
123   - . = ALIGN(4);
124   - }
125   - _end = . ;
126   - PROVIDE (end = .);
127   -}
board/siemens/pcu_e/u-boot.lds.debug
View file @ 544d97e
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -OUTPUT_ARCH(powerpc)
25   -/* Do we need any of these for elf?
26   - __DYNAMIC = 0; */
27   -SECTIONS
28   -{
29   - /* Read-only sections, merged into text segment: */
30   - . = + SIZEOF_HEADERS;
31   - .interp : { *(.interp) }
32   - .hash : { *(.hash) }
33   - .dynsym : { *(.dynsym) }
34   - .dynstr : { *(.dynstr) }
35   - .rel.text : { *(.rel.text) }
36   - .rela.text : { *(.rela.text) }
37   - .rel.data : { *(.rel.data) }
38   - .rela.data : { *(.rela.data) }
39   - .rel.rodata : { *(.rel.rodata) }
40   - .rela.rodata : { *(.rela.rodata) }
41   - .rel.got : { *(.rel.got) }
42   - .rela.got : { *(.rela.got) }
43   - .rel.ctors : { *(.rel.ctors) }
44   - .rela.ctors : { *(.rela.ctors) }
45   - .rel.dtors : { *(.rel.dtors) }
46   - .rela.dtors : { *(.rela.dtors) }
47   - .rel.bss : { *(.rel.bss) }
48   - .rela.bss : { *(.rela.bss) }
49   - .rel.plt : { *(.rel.plt) }
50   - .rela.plt : { *(.rela.plt) }
51   - .init : { *(.init) }
52   - .plt : { *(.plt) }
53   - .text :
54   - {
55   - /* WARNING - the following is hand-optimized to fit within */
56   - /* the sector layout of our flash chips! XXX FIXME XXX */
57   -
58   - arch/powerpc/cpu/mpc8xx/start.o (.text)
59   - common/dlmalloc.o (.text)
60   - lib/vsprintf.o (.text)
61   - lib/crc32.o (.text)
62   - arch/powerpc/lib/extable.o (.text)
63   -
64   - . = env_offset;
65   - common/env_embedded.o(.text)
66   -
67   - *(.text)
68   - *(.got1)
69   - }
70   - _etext = .;
71   - PROVIDE (etext = .);
72   - .rodata :
73   - {
74   - *(.rodata)
75   - *(.rodata1)
76   - *(.rodata.str1.4)
77   - *(.eh_frame)
78   - }
79   - .fini : { *(.fini) } =0
80   - .ctors : { *(.ctors) }
81   - .dtors : { *(.dtors) }
82   -
83   - /* Read-write section, merged into data segment: */
84   - . = (. + 0x0FFF) & 0xFFFFF000;
85   - _erotext = .;
86   - PROVIDE (erotext = .);
87   - .reloc :
88   - {
89   - *(.got)
90   - _GOT2_TABLE_ = .;
91   - *(.got2)
92   - _FIXUP_TABLE_ = .;
93   - *(.fixup)
94   - }
95   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
96   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
97   -
98   - .data :
99   - {
100   - *(.data)
101   - *(.data1)
102   - *(.sdata)
103   - *(.sdata2)
104   - *(.dynamic)
105   - CONSTRUCTORS
106   - }
107   - _edata = .;
108   - PROVIDE (edata = .);
109   -
110   - __u_boot_cmd_start = .;
111   - .u_boot_cmd : { *(.u_boot_cmd) }
112   - __u_boot_cmd_end = .;
113   -
114   -
115   - __start___ex_table = .;
116   - __ex_table : { *(__ex_table) }
117   - __stop___ex_table = .;
118   -
119   - . = ALIGN(4096);
120   - __init_begin = .;
121   - .text.init : { *(.text.init) }
122   - .data.init : { *(.data.init) }
123   - . = ALIGN(4096);
124   - __init_end = .;
125   -
126   - __bss_start = .;
127   - .bss :
128   - {
129   - *(.sbss) *(.scommon)
130   - *(.dynbss)
131   - *(.bss)
132   - *(COMMON)
133   - }
134   - _end = . ;
135   - PROVIDE (end = .);
136   -}
... ... @@ -163,7 +163,6 @@
163 163 ELPT860 powerpc mpc8xx elpt860 LEOX
164 164 CCM powerpc mpc8xx - siemens
165 165 IAD210 powerpc mpc8xx - siemens
166   -pcu_e powerpc mpc8xx - siemens
167 166 QS823 powerpc mpc8xx qs850 snmc
168 167 QS850 powerpc mpc8xx qs850 snmc
169 168 QS860T powerpc mpc8xx qs860t snmc
... ... @@ -580,11 +580,11 @@
580 580 /*********************************************************************/
581 581  
582 582  
583   -/*** CCM and PCU E ***********************************************/
  583 +/*** CCM ***********************************************************/
584 584  
585   -/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
  585 +/* The CCM uses the FEC on a MPC860T for Ethernet */
586 586  
587   -#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
  587 +#if defined(CONFIG_CCM)
588 588  
589 589 #define FEC_ENET /* use FEC for EThernet */
590 590 #undef SCC_ENET
... ... @@ -605,7 +605,7 @@
605 605  
606 606 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
607 607  
608   -#endif /* CONFIG_PCU_E, CONFIG_CCM */
  608 +#endif /* CONFIG_CCM */
609 609  
610 610 /*** ELPT860 *********************************************************/
611 611  
include/configs/pcu_e.h
View file @ 544d97e
1   -/*
2   - * (C) Copyright 2001-2005
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -/*
25   - * board/config.h - configuration options, board specific
26   - */
27   -
28   -#ifndef __CONFIG_H
29   -#define __CONFIG_H
30   -
31   -/*
32   - * Workaround for layout bug on prototype board
33   - */
34   -#define PCU_E_WITH_SWAPPED_CS 1
35   -
36   -/*
37   - * High Level Configuration Options
38   - * (easy to change)
39   - */
40   -
41   -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
42   -#define CONFIG_MPC860T 1
43   -#define CONFIG_PCU_E 1 /* ...on a PCU E board */
44   -
45   -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
46   -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
47   -
48   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
49   -
50   -#define CONFIG_BAUDRATE 9600
51   -#if 0
52   -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
53   -#else
54   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
55   -#endif
56   -
57   -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
58   -
59   -#undef CONFIG_BOOTARGS
60   -#define CONFIG_BOOTCOMMAND \
61   - "bootp;" \
62   - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
63   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
64   - "bootm"
65   -
66   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
67   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
68   -
69   -#undef CONFIG_WATCHDOG /* watchdog disabled */
70   -
71   -#define CONFIG_STATUS_LED 1 /* Status LED enabled */
72   -
73   -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
74   -
75   -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
76   -
77   -#define CONFIG_SPI /* enable SPI driver */
78   -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
79   -
80   -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
81   -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
82   -#define CONFIG_SYS_I2C_SLAVE 0x7F
83   -
84   -
85   -/* ----------------------------------------------------------------
86   - * Offset to initial SPI buffers in DPRAM (used if the environment
87   - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
88   - * use at an early stage. It is used between the two initialization
89   - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
90   - * far enough from the start of the data area (as well as from the
91   - * stack pointer).
92   - * ---------------------------------------------------------------- */
93   -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
94   -
95   -
96   -/*
97   - * Command line configuration.
98   - */
99   -#include <config_cmd_default.h>
100   -#define CONFIG_CMD_BSP
101   -#define CONFIG_CMD_DATE
102   -#define CONFIG_CMD_DHCP
103   -#define CONFIG_CMD_EEPROM
104   -#define CONFIG_CMD_NFS
105   -#define CONFIG_CMD_SNTP
106   -
107   -
108   -/*
109   - * BOOTP options
110   - */
111   -#define CONFIG_BOOTP_SUBNETMASK
112   -#define CONFIG_BOOTP_HOSTNAME
113   -#define CONFIG_BOOTP_BOOTPATH
114   -#define CONFIG_BOOTP_BOOTFILESIZE
115   -
116   -
117   -/*
118   - * Miscellaneous configurable options
119   - */
120   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
121   -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
122   -#if defined(CONFIG_CMD_KGDB)
123   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
124   -#else
125   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126   -#endif
127   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
130   -
131   -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
132   -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
133   -
134   -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
135   -
136   -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
137   -
138   -/* Ethernet hardware configuration done using port pins */
139   -#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */
140   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
141   -#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
142   -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
143   -#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
144   -#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
145   -#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
146   -#else /* XXX */
147   -#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */
148   -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
149   -#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */
150   -#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */
151   -#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */
152   -#endif /* XXX */
153   -
154   -/* Ethernet settings:
155   - * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
156   - */
157   -#define CONFIG_SYS_ETH_MDDIS_VALUE 0
158   -#define CONFIG_SYS_ETH_CFG1_VALUE 1
159   -#define CONFIG_SYS_ETH_CFG2_VALUE 1
160   -#define CONFIG_SYS_ETH_CFG3_VALUE 1
161   -
162   -/* PUMA configuration */
163   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
164   -#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */
165   -#else /* XXX */
166   -#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */
167   -#endif /* XXX */
168   -#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
169   -#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
170   -
171   -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
172   -
173   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
174   -
175   -/*
176   - * Low Level Configuration Settings
177   - * (address mappings, register initial values, etc.)
178   - * You should know what you are doing if you make changes here.
179   - */
180   -/*-----------------------------------------------------------------------
181   - * Internal Memory Mapped Register
182   - */
183   -#define CONFIG_SYS_IMMR 0xFE000000
184   -
185   -/*-----------------------------------------------------------------------
186   - * Definitions for initial stack pointer and data area (in DPRAM)
187   - */
188   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
189   -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
190   -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
191   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
192   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193   -
194   -/*-----------------------------------------------------------------------
195   - * Address accessed to reset the board - must not be mapped/assigned
196   - */
197   -#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
198   -
199   -/*-----------------------------------------------------------------------
200   - * Start addresses for the final memory configuration
201   - * (Set up by the startup code)
202   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
203   - */
204   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
205   -/* this is an ugly hack needed because of the silly non-constant address map */
206   -#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
207   -
208   -#if defined(DEBUG)
209   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
210   -#else
211   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
212   -#endif
213   -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
214   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
215   -
216   -/*
217   - * For booting Linux, the board info and command line data
218   - * have to be in the first 8 MB of memory, since this is
219   - * the maximum mapped by the Linux kernel during initialization.
220   - */
221   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
222   -/*-----------------------------------------------------------------------
223   - * FLASH organization
224   - */
225   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
226   -#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
227   -
228   -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
229   -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
230   -
231   -#if 0
232   -/* Start port with environment in flash; switch to SPI EEPROM later */
233   -#define CONFIG_ENV_IS_IN_FLASH 1
234   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
235   -#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
236   -#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
237   -#else
238   -/* Final version: environment in EEPROM */
239   -#define CONFIG_ENV_IS_IN_EEPROM 1
240   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0
241   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
242   -#define CONFIG_ENV_OFFSET 1024
243   -#define CONFIG_ENV_SIZE 1024
244   -#endif
245   -
246   -/*-----------------------------------------------------------------------
247   - * Cache Configuration
248   - */
249   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
250   -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
251   -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
252   - * running in RAM.
253   - */
254   -
255   -/*-----------------------------------------------------------------------
256   - * SYPCR - System Protection Control 11-9
257   - * SYPCR can only be written once after reset!
258   - *-----------------------------------------------------------------------
259   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
260   - */
261   -#if defined(CONFIG_WATCHDOG)
262   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
263   - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
264   -#else
265   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
266   -#endif
267   -
268   -/*-----------------------------------------------------------------------
269   - * SIUMCR - SIU Module Configuration 11-6
270   - *-----------------------------------------------------------------------
271   - * External Arbitration max. priority (7),
272   - * Debug pins configuration '11',
273   - * Asynchronous external master enable.
274   - */
275   -/* => 0x70600200 */
276   -#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
277   -
278   -/*-----------------------------------------------------------------------
279   - * TBSCR - Time Base Status and Control 11-26
280   - *-----------------------------------------------------------------------
281   - * Clear Reference Interrupt Status, Timebase freezing enabled
282   - */
283   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
284   -
285   -/*-----------------------------------------------------------------------
286   - * PISCR - Periodic Interrupt Status and Control 11-31
287   - *-----------------------------------------------------------------------
288   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289   - */
290   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
291   -
292   -/*-----------------------------------------------------------------------
293   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
294   - *-----------------------------------------------------------------------
295   - * Reset PLL lock status sticky bit, timer expired status bit and timer
296   - * interrupt status bit, set PLL multiplication factor !
297   - */
298   -/* 0x00004080 */
299   -#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
300   -#define CONFIG_SYS_PLPRCR \
301   - ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
302   - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
303   - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
304   - PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
305   - )
306   -
307   -#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000)
308   -
309   -/*-----------------------------------------------------------------------
310   - * SCCR - System Clock and reset Control Register 15-27
311   - *-----------------------------------------------------------------------
312   - * Set clock output, timebase and RTC source and divider,
313   - * power management and some other internal clocks
314   - *
315   - * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
316   - */
317   -#define SCCR_MASK SCCR_EBDF11
318   -/* 0x01800000 */
319   -#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
320   - SCCR_RTDIV | SCCR_RTSEL | \
321   - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
322   - SCCR_EBDF00 | SCCR_DFSYNC00 | \
323   - SCCR_DFBRG00 | SCCR_DFNL000 | \
324   - SCCR_DFNH000 | SCCR_DFLCD100 | \
325   - SCCR_DFALCD01)
326   -
327   -/*-----------------------------------------------------------------------
328   - * RTCSC - Real-Time Clock Status and Control Register 11-27
329   - *-----------------------------------------------------------------------
330   - *
331   - * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
332   - *
333   - * Don't expect the "date" command to work without a 32kHz clock input!
334   - */
335   -/* 0x00C3 => 0x0003 */
336   -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
337   -
338   -
339   -/*-----------------------------------------------------------------------
340   - * RCCR - RISC Controller Configuration Register 19-4
341   - *-----------------------------------------------------------------------
342   - */
343   -#define CONFIG_SYS_RCCR 0x0000
344   -
345   -/*-----------------------------------------------------------------------
346   - * RMDS - RISC Microcode Development Support Control Register
347   - *-----------------------------------------------------------------------
348   - */
349   -#define CONFIG_SYS_RMDS 0
350   -
351   -/*-----------------------------------------------------------------------
352   - *
353   - * Interrupt Levels
354   - *-----------------------------------------------------------------------
355   - */
356   -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
357   -
358   -/*-----------------------------------------------------------------------
359   - *
360   - *-----------------------------------------------------------------------
361   - *
362   - */
363   -#define CONFIG_SYS_DER 0
364   -
365   -/*
366   - * Init Memory Controller:
367   - *
368   - * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
369   - */
370   -
371   -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
372   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
373   -#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
374   -#else /* XXX */
375   -#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
376   -#endif /* XXX */
377   -
378   -/*
379   - * used to re-map FLASH: restrict access enough but not too much to
380   - * meddle with FLASH accesses
381   - */
382   -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
383   -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
384   -
385   -/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
386   -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
387   -
388   -#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
389   - CONFIG_SYS_OR_TIMING_FLASH)
390   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
391   - CONFIG_SYS_OR_TIMING_FLASH)
392   -/* 16 bit, bank valid */
393   -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
394   -
395   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
396   -#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP
397   -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM
398   -#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
399   -#else /* XXX */
400   -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
401   -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
402   -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
403   -#endif /* XXX */
404   -
405   -/*
406   - * BR2/OR2: SDRAM
407   - *
408   - * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
409   - */
410   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
411   -#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
412   -#else /* XXX */
413   -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
414   -#endif /* XXX */
415   -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
416   -#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
417   -
418   -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
419   -
420   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
421   -#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
422   -#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
423   -#else /* XXX */
424   -#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
425   -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
426   -#endif /* XXX */
427   -
428   -/*
429   - * BR3/OR3: CAN Controller
430   - * BR3: 0x10000401 OR3: 0xffff818a
431   - */
432   -#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
433   -#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
434   -#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
435   -
436   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
437   -#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
438   -#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
439   -#else /* XXX */
440   -#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
441   -#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
442   -#endif /* XXX */
443   -
444   -/*
445   - * BR4/OR4: PUMA Config
446   - *
447   - * Memory controller will be used in 2 modes:
448   - *
449   - * - "read" mode:
450   - * BR4: 0x10100801 OR4: 0xffff8530
451   - * - "load" mode (chip select on UPM B):
452   - * BR4: 0x101008c1 OR4: 0xffff8630
453   - *
454   - * Default initialization is in "read" mode
455   - */
456   -#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
457   -#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
458   -#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
459   -#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
460   -
461   -#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
462   - BR_PS_16 | BR_MS_UPMB | BR_V)
463   -#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
464   -
465   -#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
466   -#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
467   -
468   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
469   -#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ
470   -#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ
471   -#else /* XXX */
472   -#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
473   -#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
474   -#endif /* XXX */
475   -
476   -/*
477   - * BR5/OR5: PUMA: SMA Bus 8 Bit
478   - * BR5: 0x10200401 OR5: 0xffe0010a
479   - */
480   -#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
481   -#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
482   -#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
483   -
484   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
485   -#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
486   -#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
487   -#else /* XXX */
488   -#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
489   -#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
490   -#endif /* XXX */
491   -
492   -/*
493   - * BR6/OR6: PUMA: SMA Bus 16 Bit
494   - * BR6: 0x10600801 OR6: 0xffe0010a
495   - */
496   -#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
497   -#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
498   -#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
499   -
500   -#if PCU_E_WITH_SWAPPED_CS /* XXX */
501   -#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
502   -#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
503   -#else /* XXX */
504   -#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
505   -#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
506   -#endif /* XXX */
507   -
508   -/*
509   - * BR7/OR7: PUMA: external Flash
510   - * BR7: 0x10a00801 OR7: 0xfe00010a
511   - */
512   -#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
513   -#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
514   -#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
515   -
516   -#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
517   -#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
518   -
519   -/*
520   - * Memory Periodic Timer Prescaler
521   - */
522   -
523   -/* periodic timer for refresh */
524   -#define CONFIG_SYS_MPTPR 0x0200
525   -
526   -/*
527   - * MAMR settings for SDRAM
528   - * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
529   - * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
530   - * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
531   - */
532   -/* periodic timer for refresh */
533   -#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */
534   -
535   -#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
536   - MAMR_AMA_TYPE_1 | \
537   - MAMR_G0CLA_A10 | \
538   - MAMR_RLFA_1X | \
539   - MAMR_WLFA_1X | \
540   - MAMR_TLFA_8X )
541   -
542   -/*
543   - * Internal Definitions
544   - *
545   - * Boot Flags
546   - */
547   -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
548   -#define BOOTFLAG_WARM 0x02 /* Software reboot */
549   -
550   -#endif /* __CONFIG_H */
include/status_led.h
Diff comments   View file @ 544d97e
... ... @@ -190,8 +190,8 @@
190 190  
191 191 # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
192 192  
193   -/***** PCU E and CCM ************************************************/
194   -#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
  193 +/***** CCM ************************************************************/
  194 +#elif defined(CONFIG_CCM)
195 195  
196 196 # define STATUS_LED_PAR im_cpm.cp_pbpar
197 197 # define STATUS_LED_DIR im_cpm.cp_pbdir