Eric Lee / smarc-uboot

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Commit 5495dae7aa9d5cd161e07174d38acac86515c58a

Authored by Tom Rini
2 parents c0d297946f 27019e4a94
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-arm

Showing 61 changed files Side-by-side Diff

arch/arm/cpu/arm720t/tegra-common/cpu.c
Diff comments   View file @ 5495dae
... ... @@ -378,9 +378,8 @@
378 378 void halt_avp(void)
379 379 {
380 380 for (;;) {
381   - writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
382   - | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
383   - FLOW_CTLR_HALT_COP_EVENTS);
  381 + writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
  382 + FLOW_CTLR_HALT_COP_EVENTS);
384 383 }
385 384 }
arch/arm/cpu/arm720t/tegra124/cpu.c
Diff comments   View file @ 5495dae
... ... @@ -252,8 +252,8 @@
252 252 tegra124_init_clocks();
253 253  
254 254 /* Set power-gating timer multiplier */
255   - clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
256   - setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
  255 + writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
  256 + &pmc->pmc_pwrgate_timer_mult);
257 257  
258 258 enable_cpu_power_rail();
259 259 enable_cpu_clocks();
arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
Diff comments   View file @ 5495dae
... ... @@ -143,6 +143,31 @@
143 143 }
144 144 #endif
145 145  
  146 +#if defined(CONFIG_GENERIC_ATMEL_MCI)
  147 +void at91_mci_hw_init(void)
  148 +{
  149 + /* Enable mci clock */
  150 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  151 + writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
  152 +
  153 + at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
  154 +
  155 +#if defined(CONFIG_ATMEL_MCI_PORTB)
  156 + at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
  157 + at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
  158 + at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
  159 + at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
  160 + at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
  161 +#else
  162 + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
  163 + at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
  164 + at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
  165 + at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
  166 + at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
  167 +#endif
  168 +}
  169 +#endif
  170 +
146 171 #ifdef CONFIG_MACB
147 172 void at91_macb_hw_init(void)
148 173 {
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
Diff comments   View file @ 5495dae
... ... @@ -97,6 +97,7 @@
97 97 &cmper->gpio4clkctrl,
98 98 &cmper->gpio5clkctrl,
99 99 &cmper->i2c1clkctrl,
  100 + &cmper->cpgmac0clkctrl,
100 101 &cmper->emiffwclkctrl,
101 102 &cmper->emifclkctrl,
102 103 &cmper->otfaemifclkctrl,
arch/arm/cpu/armv7/am33xx/ddr.c
Diff comments   View file @ 5495dae
... ... @@ -80,8 +80,8 @@
80 80 */
81 81 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
82 82 {
83   - writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
84   - writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  83 + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  84 + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
85 85 writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
86 86 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
87 87  
... ... @@ -96,6 +96,7 @@
96 96  
97 97 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
98 98 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  99 + writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
99 100  
100 101 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
101 102 configure_mr(nr, 0);
arch/arm/cpu/armv7/am33xx/emif4.c
Diff comments   View file @ 5495dae
... ... @@ -113,7 +113,7 @@
113 113 writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
114 114 while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
115 115 ;
116   - writel(0x0, &ddrctrl->ddrioctrl);
  116 + writel(0x80000000, &ddrctrl->ddrioctrl);
117 117  
118 118 config_io_ctrl(ioregs);
119 119  
arch/arm/cpu/at91-common/spl.c
Diff comments   View file @ 5495dae
... ... @@ -52,6 +52,10 @@
52 52 {
53 53 #ifdef CONFIG_SYS_USE_MMC
54 54 return BOOT_DEVICE_MMC1;
  55 +#elif CONFIG_SYS_USE_NANDFLASH
  56 + return BOOT_DEVICE_NAND;
  57 +#elif CONFIG_SYS_USE_SERIALFLASH
  58 + return BOOT_DEVICE_SPI;
55 59 #endif
56 60 return BOOT_DEVICE_NONE;
57 61 }
arch/arm/include/asm/arch-at91/gpio.h
Diff comments   View file @ 5495dae
... ... @@ -214,7 +214,7 @@
214 214  
215 215 /* The following macros are need for backward compatibility */
216 216 #define at91_set_GPIO_periph(x, y) \
217   - at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
  217 + at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
218 218 #define at91_set_A_periph(x, y) \
219 219 at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
220 220 #define at91_set_B_periph(x, y) \
arch/arm/include/asm/arch-at91/spl.h
Diff comments   View file @ 5495dae
... ... @@ -14,6 +14,10 @@
14 14 BOOT_DEVICE_MMC1,
15 15 BOOT_DEVICE_MMC2,
16 16 BOOT_DEVICE_MMC2_2,
  17 +#elif CONFIG_SYS_USE_NANDFLASH
  18 + BOOT_DEVICE_NAND,
  19 +#elif CONFIG_SYS_USE_SERIALFLASH
  20 + BOOT_DEVICE_SPI,
17 21 #endif
18 22 };
19 23  
arch/arm/include/asm/arch-tegra/pmc.h
Diff comments   View file @ 5495dae
... ... @@ -298,14 +298,25 @@
298 298 #define PMC_XOFS_SHIFT 1
299 299 #define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
300 300  
  301 +#if defined(CONFIG_TEGRA114)
301 302 #define TIMER_MULT_SHIFT 0
302 303 #define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
303 304 #define TIMER_MULT_CPU_SHIFT 2
304 305 #define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
  306 +#elif defined(CONFIG_TEGRA124)
  307 +#define TIMER_MULT_SHIFT 0
  308 +#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
  309 +#define TIMER_MULT_CPU_SHIFT 3
  310 +#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
  311 +#endif
  312 +
305 313 #define MULT_1 0
306 314 #define MULT_2 1
307 315 #define MULT_4 2
308 316 #define MULT_8 3
  317 +#if defined(CONFIG_TEGRA124)
  318 +#define MULT_16 4
  319 +#endif
309 320  
310 321 #define AMAP_WRITE_SHIFT 20
311 322 #define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
arch/arm/include/asm/arch-tegra/tegra.h
Diff comments   View file @ 5495dae
... ... @@ -34,7 +34,12 @@
34 34 #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
35 35 #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
36 36 #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
  37 +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
  38 + defined(CONFIG_TEGRA114)
37 39 #define NV_PA_CSITE_BASE 0x70040000
  40 +#else
  41 +#define NV_PA_CSITE_BASE 0x70800000
  42 +#endif
38 43 #define TEGRA_USB_ADDR_MASK 0xFFFFC000
39 44  
40 45 #define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
arch/arm/include/asm/arch-tegra114/tegra.h
Diff comments   View file @ 5495dae
... ... @@ -17,6 +17,8 @@
17 17 #ifndef _TEGRA114_H_
18 18 #define _TEGRA114_H_
19 19  
  20 +#define CONFIG_TEGRA114
  21 +
20 22 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
21 23 #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
22 24  
arch/arm/include/asm/arch-tegra124/tegra.h
Diff comments   View file @ 5495dae
... ... @@ -8,6 +8,8 @@
8 8 #ifndef _TEGRA124_H_
9 9 #define _TEGRA124_H_
10 10  
  11 +#define CONFIG_TEGRA124
  12 +
11 13 #define NV_PA_SDRAM_BASE 0x80000000
12 14 #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
13 15 #define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
arch/arm/include/asm/arch-tegra20/tegra.h
Diff comments   View file @ 5495dae
... ... @@ -8,6 +8,8 @@
8 8 #ifndef _TEGRA20_H_
9 9 #define _TEGRA20_H_
10 10  
  11 +#define CONFIG_TEGRA20
  12 +
11 13 #define NV_PA_SDRAM_BASE 0x00000000
12 14  
13 15 #include <asm/arch-tegra/tegra.h>
arch/arm/include/asm/arch-tegra30/tegra.h
Diff comments   View file @ 5495dae
... ... @@ -17,6 +17,8 @@
17 17 #ifndef _TEGRA30_H_
18 18 #define _TEGRA30_H_
19 19  
  20 +#define CONFIG_TEGRA30
  21 +
20 22 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
21 23  
22 24 #include <asm/arch-tegra/tegra.h>
board/BuR/common/common.c
Diff comments   View file @ 5495dae
... ... @@ -141,12 +141,12 @@
141 141 {
142 142 .slave_reg_ofs = 0x208,
143 143 .sliver_reg_ofs = 0xd80,
144   - .phy_id = 0,
  144 + .phy_addr = 1,
145 145 },
146 146 {
147 147 .slave_reg_ofs = 0x308,
148 148 .sliver_reg_ofs = 0xdc0,
149   - .phy_id = 1,
  149 + .phy_addr = 2,
150 150 },
151 151 };
152 152  
board/atmel/at91sam9263ek/at91sam9263ek.c
Diff comments   View file @ 5495dae
... ... @@ -24,6 +24,7 @@
24 24 #include <net.h>
25 25 #endif
26 26 #include <netdev.h>
  27 +#include <atmel_mci.h>
27 28  
28 29 DECLARE_GLOBAL_DATA_PTR;
29 30  
... ... @@ -212,6 +213,15 @@
212 213 lcd_puts ("\n");
213 214 }
214 215 #endif /* CONFIG_LCD_INFO */
  216 +#endif
  217 +
  218 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  219 +int board_mmc_init(bd_t *bd)
  220 +{
  221 + at91_mci_hw_init();
  222 +
  223 + return atmel_mci_init((void *)ATMEL_BASE_MCI1);
  224 +}
215 225 #endif
216 226  
217 227 int board_early_init_f(void)
board/atmel/sama5d3_xplained/Makefile
Diff comments   View file @ 5495dae
  1 +#
  2 +# (C) Copyright 2003-2008
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2008
  6 +# Stelian Pop <stelian@popies.net>
  7 +# Lead Tech Design <www.leadtechdesign.com>
  8 +#
  9 +# (C) Copyright 2014
  10 +# Bo Shen <voice.shen@atmel.com>
  11 +#
  12 +# SPDX-License-Identifier: GPL-2.0+
  13 +#
  14 +
  15 +obj-y += sama5d3_xplained.o
board/atmel/sama5d3_xplained/sama5d3_xplained.c
Diff comments   View file @ 5495dae
  1 +/*
  2 + * Copyright (C) 2014 Atmel Corporation
  3 + * Bo Shen <voice.shen@atmel.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <mmc.h>
  10 +#include <asm/io.h>
  11 +#include <asm/arch/sama5d3_smc.h>
  12 +#include <asm/arch/at91_common.h>
  13 +#include <asm/arch/at91_pmc.h>
  14 +#include <asm/arch/at91_rstc.h>
  15 +#include <asm/arch/gpio.h>
  16 +#include <asm/arch/clk.h>
  17 +#include <atmel_mci.h>
  18 +#include <net.h>
  19 +#include <netdev.h>
  20 +
  21 +DECLARE_GLOBAL_DATA_PTR;
  22 +
  23 +#ifdef CONFIG_NAND_ATMEL
  24 +void sama5d3_xplained_nand_hw_init(void)
  25 +{
  26 + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  27 +
  28 + at91_periph_clk_enable(ATMEL_ID_SMC);
  29 +
  30 + /* Configure SMC CS3 for NAND/SmartMedia */
  31 + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  32 + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  33 + &smc->cs[3].setup);
  34 + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  35 + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  36 + &smc->cs[3].pulse);
  37 + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  38 + &smc->cs[3].cycle);
  39 + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  40 + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
  41 + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
  42 + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  43 + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  44 + AT91_SMC_MODE_EXNW_DISABLE |
  45 +#ifdef CONFIG_SYS_NAND_DBW_16
  46 + AT91_SMC_MODE_DBW_16 |
  47 +#else /* CONFIG_SYS_NAND_DBW_8 */
  48 + AT91_SMC_MODE_DBW_8 |
  49 +#endif
  50 + AT91_SMC_MODE_TDF_CYCLE(3),
  51 + &smc->cs[3].mode);
  52 +}
  53 +#endif
  54 +
  55 +#ifdef CONFIG_CMD_USB
  56 +static void sama5d3_xplained_usb_hw_init(void)
  57 +{
  58 + at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
  59 + at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
  60 +}
  61 +#endif
  62 +
  63 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  64 +static void sama5d3_xplained_mci0_hw_init(void)
  65 +{
  66 + at91_mci_hw_init();
  67 +
  68 + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
  69 +}
  70 +#endif
  71 +
  72 +int board_early_init_f(void)
  73 +{
  74 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  75 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  76 + at91_periph_clk_enable(ATMEL_ID_PIOC);
  77 + at91_periph_clk_enable(ATMEL_ID_PIOD);
  78 + at91_periph_clk_enable(ATMEL_ID_PIOE);
  79 +
  80 + at91_seriald_hw_init();
  81 +
  82 + return 0;
  83 +}
  84 +
  85 +int board_init(void)
  86 +{
  87 + /* adress of boot parameters */
  88 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  89 +
  90 +#ifdef CONFIG_NAND_ATMEL
  91 + sama5d3_xplained_nand_hw_init();
  92 +#endif
  93 +#ifdef CONFIG_CMD_USB
  94 + sama5d3_xplained_usb_hw_init();
  95 +#endif
  96 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  97 + sama5d3_xplained_mci0_hw_init();
  98 +#endif
  99 +#ifdef CONFIG_MACB
  100 + at91_gmac_hw_init();
  101 + at91_macb_hw_init();
  102 +#endif
  103 + return 0;
  104 +}
  105 +
  106 +int dram_init(void)
  107 +{
  108 + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  109 + CONFIG_SYS_SDRAM_SIZE);
  110 +
  111 + return 0;
  112 +}
  113 +
  114 +int board_eth_init(bd_t *bis)
  115 +{
  116 +#ifdef CONFIG_MACB
  117 + macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
  118 + macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  119 +#endif
  120 + return 0;
  121 +}
  122 +
  123 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  124 +int board_mmc_init(bd_t *bis)
  125 +{
  126 + atmel_mci_init((void *)ATMEL_BASE_MCI0);
  127 +
  128 + return 0;
  129 +}
  130 +#endif
board/atmel/sama5d3xek/sama5d3xek.c
Diff comments   View file @ 5495dae
... ... @@ -307,6 +307,10 @@
307 307 {
308 308 #ifdef CONFIG_SYS_USE_MMC
309 309 sama5d3xek_mci_hw_init();
  310 +#elif CONFIG_SYS_USE_NANDFLASH
  311 + sama5d3xek_nand_hw_init();
  312 +#elif CONFIG_SYS_USE_SERIALFLASH
  313 + at91_spi0_hw_init(1 << 0);
310 314 #endif
311 315 }
312 316  
board/compulab/cm_t335/cm_t335.c
Diff comments   View file @ 5495dae
... ... @@ -47,7 +47,7 @@
47 47 static struct cpsw_slave_data cpsw_slave = {
48 48 .slave_reg_ofs = 0x208,
49 49 .sliver_reg_ofs = 0xd80,
50   - .phy_id = 0,
  50 + .phy_addr = 0,
51 51 .phy_if = PHY_INTERFACE_MODE_RGMII,
52 52 };
53 53  
board/isee/igep0033/board.c
Diff comments   View file @ 5495dae
... ... @@ -116,7 +116,7 @@
116 116 {
117 117 .slave_reg_ofs = 0x208,
118 118 .sliver_reg_ofs = 0xd80,
119   - .phy_id = 0,
  119 + .phy_addr = 0,
120 120 .phy_if = PHY_INTERFACE_MODE_RMII,
121 121 },
122 122 };
board/phytec/pcm051/board.c
Diff comments   View file @ 5495dae
... ... @@ -176,13 +176,13 @@
176 176 {
177 177 .slave_reg_ofs = 0x208,
178 178 .sliver_reg_ofs = 0xd80,
179   - .phy_id = 0,
  179 + .phy_addr = 0,
180 180 .phy_if = PHY_INTERFACE_MODE_RGMII,
181 181 },
182 182 {
183 183 .slave_reg_ofs = 0x308,
184 184 .sliver_reg_ofs = 0xdc0,
185   - .phy_id = 1,
  185 + .phy_addr = 1,
186 186 .phy_if = PHY_INTERFACE_MODE_RGMII,
187 187 },
188 188 };
board/siemens/dxr2/board.c
Diff comments   View file @ 5495dae
... ... @@ -198,7 +198,7 @@
198 198 {
199 199 .slave_reg_ofs = 0x208,
200 200 .sliver_reg_ofs = 0xd80,
201   - .phy_id = 0,
  201 + .phy_addr = 0,
202 202 .phy_if = PHY_INTERFACE_MODE_MII,
203 203 },
204 204 };
... ... @@ -231,6 +231,13 @@
231 231 int rv;
232 232  
233 233 factoryset_setenv();
  234 +
  235 + /* Reset SMSC LAN9303 switch for default configuration */
  236 + gpio_request(GPIO_LAN9303_NRST, "nRST");
  237 + gpio_direction_output(GPIO_LAN9303_NRST, 0);
  238 + /* assert active low reset for 200us */
  239 + udelay(200);
  240 + gpio_set_value(GPIO_LAN9303_NRST, 1);
234 241  
235 242 /* Set rgmii mode and enable rmii clock to be sourced from chip */
236 243 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
board/siemens/dxr2/mux.c
Diff comments   View file @ 5495dae
... ... @@ -221,6 +221,8 @@
221 221 {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
222 222 {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
223 223 {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
  224 + /* nRST for SMSC LAN9303 switch - GPIO2_24 */
  225 + {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */
224 226 {-1},
225 227 };
226 228  
board/siemens/pxm2/board.c
Diff comments   View file @ 5495dae
... ... @@ -181,13 +181,13 @@
181 181 {
182 182 .slave_reg_ofs = 0x208,
183 183 .sliver_reg_ofs = 0xd80,
184   - .phy_id = 0,
  184 + .phy_addr = 0,
185 185 .phy_if = PHY_INTERFACE_MODE_RMII,
186 186 },
187 187 {
188 188 .slave_reg_ofs = 0x308,
189 189 .sliver_reg_ofs = 0xdc0,
190   - .phy_id = 1,
  190 + .phy_addr = 1,
191 191 .phy_if = PHY_INTERFACE_MODE_RMII,
192 192 },
193 193 };
board/siemens/rut/board.c
Diff comments   View file @ 5495dae
... ... @@ -143,13 +143,13 @@
143 143 {
144 144 .slave_reg_ofs = 0x208,
145 145 .sliver_reg_ofs = 0xd80,
146   - .phy_id = 1,
  146 + .phy_addr = 1,
147 147 .phy_if = PHY_INTERFACE_MODE_RMII,
148 148 },
149 149 {
150 150 .slave_reg_ofs = 0x308,
151 151 .sliver_reg_ofs = 0xdc0,
152   - .phy_id = 0,
  152 + .phy_addr = 0,
153 153 .phy_if = PHY_INTERFACE_MODE_RMII,
154 154 },
155 155 };
board/silica/pengwyn/board.c
Diff comments   View file @ 5495dae
... ... @@ -141,13 +141,13 @@
141 141 {
142 142 .slave_reg_ofs = 0x208,
143 143 .sliver_reg_ofs = 0xd80,
144   - .phy_id = 0,
  144 + .phy_addr = 0,
145 145 .phy_if = PHY_INTERFACE_MODE_MII,
146 146 },
147 147 {
148 148 .slave_reg_ofs = 0x308,
149 149 .sliver_reg_ofs = 0xdc0,
150   - .phy_id = 1,
  150 + .phy_addr = 1,
151 151 .phy_if = PHY_INTERFACE_MODE_MII,
152 152 },
153 153 };
board/ti/am335x/board.c
Diff comments   View file @ 5495dae
... ... @@ -544,12 +544,12 @@
544 544 {
545 545 .slave_reg_ofs = 0x208,
546 546 .sliver_reg_ofs = 0xd80,
547   - .phy_id = 0,
  547 + .phy_addr = 0,
548 548 },
549 549 {
550 550 .slave_reg_ofs = 0x308,
551 551 .sliver_reg_ofs = 0xdc0,
552   - .phy_id = 1,
  552 + .phy_addr = 1,
553 553 },
554 554 };
555 555  
... ... @@ -602,6 +602,21 @@
602 602 }
603 603  
604 604 #ifdef CONFIG_DRIVER_TI_CPSW
  605 +
  606 + mac_lo = readl(&cdev->macid1l);
  607 + mac_hi = readl(&cdev->macid1h);
  608 + mac_addr[0] = mac_hi & 0xFF;
  609 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  610 + mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  611 + mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  612 + mac_addr[4] = mac_lo & 0xFF;
  613 + mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  614 +
  615 + if (!getenv("eth1addr")) {
  616 + if (is_valid_ether_addr(mac_addr))
  617 + eth_setenv_enetaddr("eth1addr", mac_addr);
  618 + }
  619 +
605 620 if (read_eeprom(&header) < 0)
606 621 puts("Could not get board ID.\n");
607 622  
board/ti/am43xx/board.c
Diff comments   View file @ 5495dae
... ... @@ -19,9 +19,13 @@
19 19 #include <asm/arch/gpio.h>
20 20 #include <asm/emif.h>
21 21 #include "board.h"
  22 +#include <miiphy.h>
  23 +#include <cpsw.h>
22 24  
23 25 DECLARE_GLOBAL_DATA_PTR;
24 26  
  27 +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  28 +
25 29 /*
26 30 * Read header information from EEPROM into global structure.
27 31 */
... ... @@ -200,7 +204,7 @@
200 204 .read_idle_ctrl = 0x00050000,
201 205 .zq_config = 0x50074BE4,
202 206 .temp_alert_config = 0x0,
203   - .emif_ddr_phy_ctlr_1 = 0x0E084008,
  207 + .emif_ddr_phy_ctlr_1 = 0x0E004008,
204 208 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
205 209 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
206 210 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
... ... @@ -400,6 +404,100 @@
400 404 setenv("board_rev", safe_string);
401 405 #endif
402 406 return 0;
  407 +}
  408 +#endif
  409 +
  410 +#ifdef CONFIG_DRIVER_TI_CPSW
  411 +
  412 +static void cpsw_control(int enabled)
  413 +{
  414 + /* Additional controls can be added here */
  415 + return;
  416 +}
  417 +
  418 +static struct cpsw_slave_data cpsw_slaves[] = {
  419 + {
  420 + .slave_reg_ofs = 0x208,
  421 + .sliver_reg_ofs = 0xd80,
  422 + .phy_addr = 16,
  423 + },
  424 + {
  425 + .slave_reg_ofs = 0x308,
  426 + .sliver_reg_ofs = 0xdc0,
  427 + .phy_addr = 1,
  428 + },
  429 +};
  430 +
  431 +static struct cpsw_platform_data cpsw_data = {
  432 + .mdio_base = CPSW_MDIO_BASE,
  433 + .cpsw_base = CPSW_BASE,
  434 + .mdio_div = 0xff,
  435 + .channels = 8,
  436 + .cpdma_reg_ofs = 0x800,
  437 + .slaves = 1,
  438 + .slave_data = cpsw_slaves,
  439 + .ale_reg_ofs = 0xd00,
  440 + .ale_entries = 1024,
  441 + .host_port_reg_ofs = 0x108,
  442 + .hw_stats_reg_ofs = 0x900,
  443 + .bd_ram_ofs = 0x2000,
  444 + .mac_control = (1 << 5),
  445 + .control = cpsw_control,
  446 + .host_port_num = 0,
  447 + .version = CPSW_CTRL_VERSION_2,
  448 +};
  449 +
  450 +int board_eth_init(bd_t *bis)
  451 +{
  452 + int rv;
  453 + uint8_t mac_addr[6];
  454 + uint32_t mac_hi, mac_lo;
  455 +
  456 + /* try reading mac address from efuse */
  457 + mac_lo = readl(&cdev->macid0l);
  458 + mac_hi = readl(&cdev->macid0h);
  459 + mac_addr[0] = mac_hi & 0xFF;
  460 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  461 + mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  462 + mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  463 + mac_addr[4] = mac_lo & 0xFF;
  464 + mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  465 +
  466 + if (!getenv("ethaddr")) {
  467 + puts("<ethaddr> not set. Validating first E-fuse MAC\n");
  468 + if (is_valid_ether_addr(mac_addr))
  469 + eth_setenv_enetaddr("ethaddr", mac_addr);
  470 + }
  471 +
  472 + mac_lo = readl(&cdev->macid1l);
  473 + mac_hi = readl(&cdev->macid1h);
  474 + mac_addr[0] = mac_hi & 0xFF;
  475 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  476 + mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  477 + mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  478 + mac_addr[4] = mac_lo & 0xFF;
  479 + mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  480 +
  481 + if (!getenv("eth1addr")) {
  482 + if (is_valid_ether_addr(mac_addr))
  483 + eth_setenv_enetaddr("eth1addr", mac_addr);
  484 + }
  485 +
  486 + if (board_is_eposevm()) {
  487 + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
  488 + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
  489 + cpsw_slaves[0].phy_addr = 16;
  490 + } else {
  491 + writel(RGMII_MODE_ENABLE, &cdev->miisel);
  492 + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
  493 + cpsw_slaves[0].phy_addr = 0;
  494 + }
  495 +
  496 + rv = cpsw_register(&cpsw_data);
  497 + if (rv < 0)
  498 + printf("Error %d registering CPSW switch\n", rv);
  499 +
  500 + return rv;
403 501 }
404 502 #endif
board/ti/am43xx/mux.c
Diff comments   View file @ 5495dae
... ... @@ -11,6 +11,41 @@
11 11 #include <asm/arch/mux.h>
12 12 #include "board.h"
13 13  
  14 +static struct module_pin_mux rmii1_pin_mux[] = {
  15 + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
  16 + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
  17 + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
  18 + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
  19 + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
  20 + {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
  21 + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
  22 + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
  23 + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
  24 + {-1},
  25 +};
  26 +
  27 +static struct module_pin_mux rgmii1_pin_mux[] = {
  28 + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
  29 + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  30 + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
  31 + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
  32 + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
  33 + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
  34 + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
  35 + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  36 + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  37 + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  38 + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  39 + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  40 + {-1},
  41 +};
  42 +
  43 +static struct module_pin_mux mdio_pin_mux[] = {
  44 + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  45 + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  46 + {-1},
  47 +};
  48 +
14 49 static struct module_pin_mux uart0_pin_mux[] = {
15 50 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
16 51 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
17 52  
18 53  
... ... @@ -57,10 +92,15 @@
57 92 {
58 93 configure_module_pin_mux(mmc0_pin_mux);
59 94 configure_module_pin_mux(i2c0_pin_mux);
  95 + configure_module_pin_mux(mdio_pin_mux);
60 96  
61   - if (board_is_gpevm())
  97 + if (board_is_gpevm()) {
62 98 configure_module_pin_mux(gpio5_7_pin_mux);
63   - configure_module_pin_mux(qspi_pin_mux);
  99 + configure_module_pin_mux(rgmii1_pin_mux);
  100 + } else if (board_is_eposevm()) {
  101 + configure_module_pin_mux(rmii1_pin_mux);
  102 + configure_module_pin_mux(qspi_pin_mux);
  103 + }
64 104 }
65 105  
66 106 void enable_i2c0_pin_mux(void)
board/ti/dra7xx/evm.c
Diff comments   View file @ 5495dae
... ... @@ -149,12 +149,12 @@
149 149 {
150 150 .slave_reg_ofs = 0x208,
151 151 .sliver_reg_ofs = 0xd80,
152   - .phy_id = 0,
  152 + .phy_addr = 2,
153 153 },
154 154 {
155 155 .slave_reg_ofs = 0x308,
156 156 .sliver_reg_ofs = 0xdc0,
157   - .phy_id = 1,
  157 + .phy_addr = 3,
158 158 },
159 159 };
160 160  
... ... @@ -216,6 +216,21 @@
216 216 if (is_valid_ether_addr(mac_addr))
217 217 eth_setenv_enetaddr("ethaddr", mac_addr);
218 218 }
  219 +
  220 + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  221 + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  222 + mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  223 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  224 + mac_addr[2] = mac_hi & 0xFF;
  225 + mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  226 + mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  227 + mac_addr[5] = mac_lo & 0xFF;
  228 +
  229 + if (!getenv("eth1addr")) {
  230 + if (is_valid_ether_addr(mac_addr))
  231 + eth_setenv_enetaddr("eth1addr", mac_addr);
  232 + }
  233 +
219 234 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
220 235 ctrl_val |= 0x22;
221 236 writel(ctrl_val, (*ctrl)->control_core_control_io1);
board/ti/ti814x/evm.c
Diff comments   View file @ 5495dae
... ... @@ -132,12 +132,12 @@
132 132 {
133 133 .slave_reg_ofs = 0x50,
134 134 .sliver_reg_ofs = 0x700,
135   - .phy_id = 1,
  135 + .phy_addr = 1,
136 136 },
137 137 {
138 138 .slave_reg_ofs = 0x90,
139 139 .sliver_reg_ofs = 0x740,
140   - .phy_id = 0,
  140 + .phy_addr = 0,
141 141 },
142 142 };
143 143  
... ... @@ -278,6 +278,8 @@
278 278 Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
279 279 Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
280 280 Active arm armv7 am33xx ti ti816x ti816x_evm - -
  281 +Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
  282 +Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_nandflash sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
281 283 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
282 284 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
283 285 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
drivers/mtd/nand/atmel_nand.c
Diff comments   View file @ 5495dae
... ... @@ -31,6 +31,10 @@
31 31  
32 32 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
33 33  
  34 +#ifdef CONFIG_SPL_BUILD
  35 +#undef CONFIG_SYS_NAND_ONFI_DETECTION
  36 +#endif
  37 +
34 38 struct atmel_nand_host {
35 39 struct pmecc_regs __iomem *pmecc;
36 40 struct pmecc_errloc_regs __iomem *pmerrloc;
... ... @@ -1169,6 +1173,209 @@
1169 1173 }
1170 1174 #endif
1171 1175  
  1176 +#ifdef CONFIG_SPL_BUILD
  1177 +/* The following code is for SPL */
  1178 +static nand_info_t mtd;
  1179 +static struct nand_chip nand_chip;
  1180 +
  1181 +static int nand_command(int block, int page, uint32_t offs, u8 cmd)
  1182 +{
  1183 + struct nand_chip *this = mtd.priv;
  1184 + int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1185 + void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1186 + unsigned int ctrl) = this->cmd_ctrl;
  1187 +
  1188 + while (this->dev_ready(&mtd))
  1189 + ;
  1190 +
  1191 + if (cmd == NAND_CMD_READOOB) {
  1192 + offs += CONFIG_SYS_NAND_PAGE_SIZE;
  1193 + cmd = NAND_CMD_READ0;
  1194 + }
  1195 +
  1196 + hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1197 +
  1198 + if (this->options & NAND_BUSWIDTH_16)
  1199 + offs >>= 1;
  1200 +
  1201 + hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1202 + hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
  1203 + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
  1204 + hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
  1205 +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1206 + hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
  1207 +#endif
  1208 + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1209 +
  1210 + hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1211 + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1212 +
  1213 + while (this->dev_ready(&mtd))
  1214 + ;
  1215 +
  1216 + return 0;
  1217 +}
  1218 +
  1219 +static int nand_is_bad_block(int block)
  1220 +{
  1221 + struct nand_chip *this = mtd.priv;
  1222 +
  1223 + nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
  1224 +
  1225 + if (this->options & NAND_BUSWIDTH_16) {
  1226 + if (readw(this->IO_ADDR_R) != 0xffff)
  1227 + return 1;
  1228 + } else {
  1229 + if (readb(this->IO_ADDR_R) != 0xff)
  1230 + return 1;
  1231 + }
  1232 +
  1233 + return 0;
  1234 +}
  1235 +
  1236 +#ifdef CONFIG_SPL_NAND_ECC
  1237 +static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  1238 +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  1239 + CONFIG_SYS_NAND_ECCSIZE)
  1240 +#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  1241 +
  1242 +static int nand_read_page(int block, int page, void *dst)
  1243 +{
  1244 + struct nand_chip *this = mtd.priv;
  1245 + u_char ecc_calc[ECCTOTAL];
  1246 + u_char ecc_code[ECCTOTAL];
  1247 + u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  1248 + int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  1249 + int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  1250 + int eccsteps = ECCSTEPS;
  1251 + int i;
  1252 + uint8_t *p = dst;
  1253 + nand_command(block, page, 0, NAND_CMD_READ0);
  1254 +
  1255 + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1256 + if (this->ecc.mode != NAND_ECC_SOFT)
  1257 + this->ecc.hwctl(&mtd, NAND_ECC_READ);
  1258 + this->read_buf(&mtd, p, eccsize);
  1259 + this->ecc.calculate(&mtd, p, &ecc_calc[i]);
  1260 + }
  1261 + this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  1262 +
  1263 + for (i = 0; i < ECCTOTAL; i++)
  1264 + ecc_code[i] = oob_data[nand_ecc_pos[i]];
  1265 +
  1266 + eccsteps = ECCSTEPS;
  1267 + p = dst;
  1268 +
  1269 + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1270 + this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
  1271 +
  1272 + return 0;
  1273 +}
  1274 +#else
  1275 +static int nand_read_page(int block, int page, void *dst)
  1276 +{
  1277 + struct nand_chip *this = mtd.priv;
  1278 +
  1279 + nand_command(block, page, 0, NAND_CMD_READ0);
  1280 + atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
  1281 +
  1282 + return 0;
  1283 +}
  1284 +#endif /* CONFIG_SPL_NAND_ECC */
  1285 +
  1286 +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
  1287 +{
  1288 + unsigned int block, lastblock;
  1289 + unsigned int page;
  1290 +
  1291 + block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
  1292 + lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
  1293 + page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
  1294 +
  1295 + while (block <= lastblock) {
  1296 + if (!nand_is_bad_block(block)) {
  1297 + while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
  1298 + nand_read_page(block, page, dst);
  1299 + dst += CONFIG_SYS_NAND_PAGE_SIZE;
  1300 + page++;
  1301 + }
  1302 +
  1303 + page = 0;
  1304 + } else {
  1305 + lastblock++;
  1306 + }
  1307 +
  1308 + block++;
  1309 + }
  1310 +
  1311 + return 0;
  1312 +}
  1313 +
  1314 +int at91_nand_wait_ready(struct mtd_info *mtd)
  1315 +{
  1316 + struct nand_chip *this = mtd->priv;
  1317 +
  1318 + udelay(this->chip_delay);
  1319 +
  1320 + return 0;
  1321 +}
  1322 +
  1323 +int board_nand_init(struct nand_chip *nand)
  1324 +{
  1325 + int ret = 0;
  1326 +
  1327 + nand->ecc.mode = NAND_ECC_SOFT;
  1328 +#ifdef CONFIG_SYS_NAND_DBW_16
  1329 + nand->options = NAND_BUSWIDTH_16;
  1330 + nand->read_buf = nand_read_buf16;
  1331 +#else
  1332 + nand->read_buf = nand_read_buf;
  1333 +#endif
  1334 + nand->cmd_ctrl = at91_nand_hwcontrol;
  1335 +#ifdef CONFIG_SYS_NAND_READY_PIN
  1336 + nand->dev_ready = at91_nand_ready;
  1337 +#else
  1338 + nand->dev_ready = at91_nand_wait_ready;
  1339 +#endif
  1340 + nand->chip_delay = 20;
  1341 +
  1342 +#ifdef CONFIG_ATMEL_NAND_HWECC
  1343 +#ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1344 + ret = atmel_pmecc_nand_init_params(nand, &mtd);
  1345 +#endif
  1346 +#endif
  1347 +
  1348 + return ret;
  1349 +}
  1350 +
  1351 +void nand_init(void)
  1352 +{
  1353 + mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
  1354 + mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
  1355 + mtd.priv = &nand_chip;
  1356 + nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1357 + nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1358 + board_nand_init(&nand_chip);
  1359 +
  1360 +#ifdef CONFIG_SPL_NAND_ECC
  1361 + if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
  1362 + nand_chip.ecc.calculate = nand_calculate_ecc;
  1363 + nand_chip.ecc.correct = nand_correct_data;
  1364 + }
  1365 +#endif
  1366 +
  1367 + if (nand_chip.select_chip)
  1368 + nand_chip.select_chip(&mtd, 0);
  1369 +}
  1370 +
  1371 +void nand_deselect(void)
  1372 +{
  1373 + if (nand_chip.select_chip)
  1374 + nand_chip.select_chip(&mtd, -1);
  1375 +}
  1376 +
  1377 +#else
  1378 +
1172 1379 #ifndef CONFIG_SYS_NAND_BASE_LIST
1173 1380 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1174 1381 #endif
... ... @@ -1227,4 +1434,5 @@
1227 1434 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1228 1435 i);
1229 1436 }
  1437 +#endif /* CONFIG_SPL_BUILD */
... ... @@ -656,7 +656,7 @@
656 656  
657 657 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
658 658  
659   - priv->phy_mask |= 1 << slave->data->phy_id;
  659 + priv->phy_mask |= 1 << slave->data->phy_addr;
660 660 }
661 661  
662 662 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
... ... @@ -948,7 +948,7 @@
948 948 SUPPORTED_1000baseT_Full);
949 949  
950 950 phydev = phy_connect(priv->bus,
951   - CONFIG_PHY_ADDR,
  951 + slave->data->phy_addr,
952 952 dev,
953 953 slave->data->phy_if);
954 954  
include/configs/am335x_evm.h
Diff comments   View file @ 5495dae
... ... @@ -398,7 +398,6 @@
398 398 /* Network. */
399 399 #define CONFIG_PHY_GIGE
400 400 #define CONFIG_PHYLIB
401   -#define CONFIG_PHY_ADDR 0
402 401 #define CONFIG_PHY_SMSC
403 402  
404 403 /* NAND support */
include/configs/am335x_igep0033.h
Diff comments   View file @ 5495dae
... ... @@ -181,7 +181,6 @@
181 181 #define CONFIG_NET_RETRY_COUNT 10
182 182 #define CONFIG_NET_MULTI
183 183 #define CONFIG_PHYLIB
184   -#define CONFIG_PHY_ADDR 0
185 184 #define CONFIG_PHY_SMSC
186 185  
187 186 /* NAND support */
include/configs/am43xx_evm.h
Diff comments   View file @ 5495dae
... ... @@ -205,5 +205,31 @@
205 205 "run usbboot;"
206 206  
207 207 #endif
  208 +
  209 +/* CPSW Ethernet */
  210 +#define CONFIG_CMD_NET
  211 +#define CONFIG_CMD_DHCP
  212 +#define CONFIG_CMD_PING
  213 +#define CONFIG_CMD_MII
  214 +#define CONFIG_DRIVER_TI_CPSW
  215 +#define CONFIG_MII
  216 +#define CONFIG_BOOTP_DEFAULT
  217 +#define CONFIG_BOOTP_DNS
  218 +#define CONFIG_BOOTP_DNS2
  219 +#define CONFIG_BOOTP_SEND_HOSTNAME
  220 +#define CONFIG_BOOTP_GATEWAY
  221 +#define CONFIG_BOOTP_SUBNETMASK
  222 +#define CONFIG_NET_RETRY_COUNT 10
  223 +#define CONFIG_NET_MULTI
  224 +#define CONFIG_PHY_GIGE
  225 +#define CONFIG_PHYLIB
  226 +
  227 +#define CONFIG_SPL_ENV_SUPPORT
  228 +#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
  229 +
  230 +#define CONFIG_SPL_ETH_SUPPORT
  231 +#define CONFIG_SPL_NET_SUPPORT
  232 +#define CONFIG_SYS_RX_ETH_BUFFER 64
  233 +
208 234 #endif /* __CONFIG_AM43XX_EVM_H */
include/configs/at91sam9263ek.h
Diff comments   View file @ 5495dae
... ... @@ -103,6 +103,7 @@
103 103 #define CONFIG_CMD_PING 1
104 104 #define CONFIG_CMD_DHCP 1
105 105 #define CONFIG_CMD_NAND 1
  106 +#define CONFIG_CMD_MMC
106 107 #define CONFIG_CMD_USB 1
107 108  
108 109 /* SDRAM */
... ... @@ -122,6 +123,18 @@
122 123 #define AT91_SPI_CLK 15000000
123 124 #define DATAFLASH_TCSS (0x1a << 16)
124 125 #define DATAFLASH_TCHS (0x1 << 24)
  126 +
  127 +/* MMC */
  128 +#ifdef CONFIG_CMD_MMC
  129 +#define CONFIG_MMC
  130 +#define CONFIG_GENERIC_MMC
  131 +#define CONFIG_GENERIC_ATMEL_MCI
  132 +#endif
  133 +
  134 +/* FAT */
  135 +#ifdef CONFIG_CMD_FAT
  136 +#define CONFIG_DOS_PARTITION
  137 +#endif
125 138  
126 139 /* NOR flash, if populated */
127 140 #ifdef CONFIG_SYS_USE_NORFLASH
include/configs/bur_am335x_common.h
Diff comments   View file @ 5495dae
... ... @@ -51,7 +51,6 @@
51 51 #define CONFIG_MII /* Required in net/eth.c */
52 52 #define CONFIG_SPL_ETH_SUPPORT
53 53 #define CONFIG_PHYLIB
54   -#define CONFIG_PHY_ADDR 1
55 54 #define CONFIG_PHY_NATSEMI
56 55 #define CONFIG_SPL_NET_SUPPORT
57 56 #define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
include/configs/cm_t335.h
Diff comments   View file @ 5495dae
... ... @@ -114,7 +114,6 @@
114 114 /* Network. */
115 115 #define CONFIG_PHY_GIGE
116 116 #define CONFIG_PHYLIB
117   -#define CONFIG_PHY_ADDR 0
118 117 #define CONFIG_PHY_ATHEROS
119 118  
120 119 /* NAND support */
include/configs/dra7xx_evm.h
Diff comments   View file @ 5495dae
... ... @@ -62,7 +62,6 @@
62 62 #define CONFIG_MII /* Required in net/eth.c */
63 63 #define CONFIG_PHY_GIGE /* per-board part of CPSW */
64 64 #define CONFIG_PHYLIB
65   -#define CONFIG_PHY_ADDR 2
66 65  
67 66 /* SPI */
68 67 #undef CONFIG_OMAP3_SPI
include/configs/dxr2.h
Diff comments   View file @ 5495dae
... ... @@ -26,6 +26,7 @@
26 26  
27 27 #define BOARD_DFU_BUTTON_GPIO 27
28 28 #define BOARD_DFU_BUTTON_LED 64
  29 +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
29 30  
30 31 #undef CONFIG_DOS_PARTITION
31 32 #undef CONFIG_CMD_FAT
... ... @@ -49,7 +50,6 @@
49 50  
50 51 #undef CONFIG_MII
51 52 #undef CONFIG_PHY_GIGE
52   -#define CONFIG_PHY_ADDR 0
53 53 #define CONFIG_PHY_SMSC
54 54  
55 55 #define CONFIG_FACTORYSET
include/configs/omap3_igep00x0.h
Diff comments   View file @ 5495dae
... ... @@ -37,6 +37,11 @@
37 37 #define CONFIG_SHOW_BOOT_PROGRESS
38 38 #endif
39 39  
  40 +/* GPIO banks */
  41 +#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
  42 +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
  43 +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
  44 +
40 45 /* USB */
41 46 #define CONFIG_MUSB_UDC 1
42 47 #define CONFIG_USB_OMAP3 1
include/configs/pcm051.h
Diff comments   View file @ 5495dae
... ... @@ -297,7 +297,6 @@
297 297 #define CONFIG_NET_MULTI
298 298 #define CONFIG_PHY_GIGE
299 299 #define CONFIG_PHYLIB
300   -#define CONFIG_PHY_ADDR 0
301 300 #define CONFIG_PHY_SMSC
302 301  
303 302 #endif /* ! __CONFIG_PCM051_H */
include/configs/pengwyn.h
Diff comments   View file @ 5495dae
... ... @@ -196,7 +196,6 @@
196 196 /* Network */
197 197 #define CONFIG_CMD_MII
198 198 #define CONFIG_PHYLIB
199   -#define CONFIG_PHY_ADDR 1
200 199 #define CONFIG_PHY_RESET 1
201 200 #define CONFIG_PHY_NATSEMI
202 201  
include/configs/pxm2.h
Diff comments   View file @ 5495dae
... ... @@ -44,7 +44,6 @@
44 44 #undef CONFIG_SPL_NET_VCI_STRING
45 45 #undef CONFIG_SPL_ETH_SUPPORT
46 46  
47   -#define CONFIG_PHY_ADDR 0
48 47 #define CONFIG_PHY_ATHEROS
49 48  
50 49 #define CONFIG_FACTORYSET
include/configs/rut.h
Diff comments   View file @ 5495dae
... ... @@ -41,7 +41,6 @@
41 41 #undef CONFIG_SPL_NET_VCI_STRING
42 42 #undef CONFIG_SPL_ETH_SUPPORT
43 43  
44   -#define CONFIG_PHY_ADDR 1
45 44 #define CONFIG_PHY_NATSEMI
46 45  
47 46 #define CONFIG_FACTORYSET
include/configs/sama5d3_xplained.h
Diff comments   View file @ 5495dae
  1 +/*
  2 + * Configuration settings for the SAMA5D3 Xplained board.
  3 + *
  4 + * Copyright (C) 2014 Atmel Corporation
  5 + * Bo Shen <voice.shen@atmel.com>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#ifndef __CONFIG_H
  11 +#define __CONFIG_H
  12 +
  13 +#include <asm/hardware.h>
  14 +
  15 +#define CONFIG_SYS_TEXT_BASE 0x26f00000
  16 +
  17 +/* ARM asynchronous clock */
  18 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  19 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
  20 +#define CONFIG_SYS_HZ 1000
  21 +
  22 +#define CONFIG_AT91FAMILY
  23 +#define CONFIG_ARCH_CPU_INIT
  24 +#define CONFIG_SKIP_LOWLEVEL_INIT
  25 +#define CONFIG_BOARD_EARLY_INIT_F
  26 +#define CONFIG_DISPLAY_CPUINFO
  27 +
  28 +#define CONFIG_CMD_BOOTZ
  29 +#define CONFIG_OF_LIBFDT /* Device Tree support */
  30 +
  31 +/* general purpose I/O */
  32 +#define CONFIG_AT91_GPIO
  33 +
  34 +/* serial console */
  35 +#define CONFIG_ATMEL_USART
  36 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU
  37 +#define CONFIG_USART_ID ATMEL_ID_DBGU
  38 +
  39 +/*
  40 + * This needs to be defined for the OHCI code to work but it is defined as
  41 + * ATMEL_ID_UHPHS in the CPU specific header files.
  42 + */
  43 +#define ATMEL_ID_UHP ATMEL_ID_UHPHS
  44 +
  45 +/*
  46 + * Specify the clock enable bit in the PMC_SCER register.
  47 + */
  48 +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
  49 +
  50 +#define CONFIG_BOOTDELAY 3
  51 +
  52 +/*
  53 + * BOOTP options
  54 + */
  55 +#define CONFIG_BOOTP_BOOTFILESIZE
  56 +#define CONFIG_BOOTP_BOOTPATH
  57 +#define CONFIG_BOOTP_GATEWAY
  58 +#define CONFIG_BOOTP_HOSTNAME
  59 +
  60 +/* No NOR flash */
  61 +#define CONFIG_SYS_NO_FLASH
  62 +
  63 +/*
  64 + * Command line configuration.
  65 + */
  66 +#include <config_cmd_default.h>
  67 +#undef CONFIG_CMD_FPGA
  68 +#undef CONFIG_CMD_IMI
  69 +#undef CONFIG_CMD_LOADS
  70 +#define CONFIG_CMD_PING
  71 +#define CONFIG_CMD_DHCP
  72 +
  73 +/* SDRAM */
  74 +#define CONFIG_NR_DRAM_BANKS 1
  75 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
  76 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000
  77 +
  78 +#define CONFIG_SYS_INIT_SP_ADDR \
  79 + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
  80 +
  81 +/* NAND flash */
  82 +#define CONFIG_CMD_NAND
  83 +
  84 +#ifdef CONFIG_CMD_NAND
  85 +#define CONFIG_NAND_ATMEL
  86 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  87 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  88 +/* our ALE is AD21 */
  89 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  90 +/* our CLE is AD22 */
  91 +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  92 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  93 +/* PMECC & PMERRLOC */
  94 +#define CONFIG_ATMEL_NAND_HWECC
  95 +#define CONFIG_ATMEL_NAND_HW_PMECC
  96 +#define CONFIG_PMECC_CAP 4
  97 +#define CONFIG_PMECC_SECTOR_SIZE 512
  98 +#define CONFIG_CMD_NAND_TRIMFFS
  99 +#define CONFIG_CMD_MTDPARTS
  100 +
  101 +#define CONFIG_MTD_DEVICE
  102 +#define CONFIG_MTD_PARTITIONS
  103 +#define CONFIG_RBTREE
  104 +#define CONFIG_LZO
  105 +#define CONFIG_CMD_UBI
  106 +#define CONFIG_CMD_UBIFS
  107 +#endif
  108 +
  109 +/* Ethernet Hardware */
  110 +#define CONFIG_MACB
  111 +#define CONFIG_RMII
  112 +#define CONFIG_NET_MULTI
  113 +#define CONFIG_NET_RETRY_COUNT 20
  114 +#define CONFIG_MACB_SEARCH_PHY
  115 +#define CONFIG_RGMII
  116 +#define CONFIG_CMD_MII
  117 +#define CONFIG_PHYLIB
  118 +
  119 +/* MMC */
  120 +#define CONFIG_CMD_MMC
  121 +
  122 +#ifdef CONFIG_CMD_MMC
  123 +#define CONFIG_MMC
  124 +#define CONFIG_GENERIC_MMC
  125 +#define CONFIG_GENERIC_ATMEL_MCI
  126 +#define CONFIG_ATMEL_MCI_8BIT
  127 +#endif
  128 +
  129 +/* USB */
  130 +#define CONFIG_CMD_USB
  131 +
  132 +#ifdef CONFIG_CMD_USB
  133 +#define CONFIG_USB_ATMEL
  134 +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  135 +#define CONFIG_USB_OHCI_NEW
  136 +#define CONFIG_SYS_USB_OHCI_CPU_INIT
  137 +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
  138 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
  139 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  140 +#define CONFIG_DOS_PARTITION
  141 +#define CONFIG_USB_STORAGE
  142 +#endif
  143 +
  144 +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
  145 +#define CONFIG_CMD_FAT
  146 +#define CONFIG_FAT_WRITE
  147 +#define CONFIG_CMD_EXT4
  148 +#define CONFIG_CMD_EXT4_WRITE
  149 +#endif
  150 +
  151 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  152 +
  153 +#if CONFIG_SYS_USE_NANDFLASH
  154 +/* bootstrap + u-boot + env in nandflash */
  155 +#define CONFIG_ENV_IS_IN_NAND
  156 +#define CONFIG_ENV_OFFSET 0xc0000
  157 +#define CONFIG_ENV_OFFSET_REDUND 0x100000
  158 +#define CONFIG_ENV_SIZE 0x20000
  159 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
  160 + "nand read 0x22000000 0x200000 0x600000;" \
  161 + "bootz 0x22000000 - 0x21000000"
  162 +#elif CONFIG_SYS_USE_MMC
  163 +/* bootstrap + u-boot + env in sd card */
  164 +#define CONFIG_ENV_IS_IN_MMC
  165 +#define CONFIG_ENV_OFFSET 0x2000
  166 +#define CONFIG_ENV_SIZE 0x1000
  167 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
  168 + "fatload mmc 0:1 0x22000000 zImage; " \
  169 + "bootz 0x22000000 - 0x21000000"
  170 +#define CONFIG_SYS_MMC_ENV_DEV 0
  171 +#else
  172 +#define CONFIG_ENV_IS_NOWHERE
  173 +#endif
  174 +
  175 +#ifdef CONFIG_SYS_USE_MMC
  176 +#define CONFIG_BOOTARGS \
  177 + "console=ttyS0,115200 earlyprintk " \
  178 + "root=/dev/mmcblk0p2 rw rootwait"
  179 +#else
  180 +#define CONFIG_BOOTARGS \
  181 + "console=ttyS0,115200 earlyprintk " \
  182 + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
  183 + "256K(env),256k(evn_redundent),256k(spare)," \
  184 + "512k(dtb),6M(kernel)ro,-(rootfs) " \
  185 + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
  186 +#endif
  187 +
  188 +#define CONFIG_BAUDRATE 115200
  189 +
  190 +#define CONFIG_SYS_PROMPT "U-Boot> "
  191 +#define CONFIG_SYS_CBSIZE 256
  192 +#define CONFIG_SYS_MAXARGS 16
  193 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  194 + sizeof(CONFIG_SYS_PROMPT) + 16)
  195 +#define CONFIG_SYS_LONGHELP
  196 +#define CONFIG_CMDLINE_EDITING
  197 +#define CONFIG_AUTO_COMPLETE
  198 +#define CONFIG_SYS_HUSH_PARSER
  199 +
  200 +/* Size of malloc() pool */
  201 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  202 +
  203 +#endif
include/configs/sama5d3xek.h
Diff comments   View file @ 5495dae
... ... @@ -258,6 +258,8 @@
258 258 #define CONFIG_SPL_SERIAL_SUPPORT
259 259  
260 260 #define CONFIG_SPL_BOARD_INIT
  261 +#define CONFIG_SYS_MONITOR_LEN (512 << 10)
  262 +
261 263 #ifdef CONFIG_SYS_USE_MMC
262 264 #define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
263 265 #define CONFIG_SPL_MMC_SUPPORT
... ... @@ -267,6 +269,27 @@
267 269 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
268 270 #define CONFIG_SPL_FAT_SUPPORT
269 271 #define CONFIG_SPL_LIBDISK_SUPPORT
  272 +
  273 +#elif CONFIG_SYS_USE_NANDFLASH
  274 +#define CONFIG_SPL_NAND_SUPPORT
  275 +#define CONFIG_SPL_NAND_DRIVERS
  276 +#define CONFIG_SPL_NAND_BASE
  277 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  278 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  279 +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  280 +#define CONFIG_SYS_NAND_PAGE_COUNT 64
  281 +#define CONFIG_SYS_NAND_OOBSIZE 64
  282 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  283 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  284 +
  285 +#elif CONFIG_SYS_USE_SERIALFLASH
  286 +#define CONFIG_SPL_SPI_SUPPORT
  287 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
  288 +#define CONFIG_SPL_SPI_LOAD
  289 +#define CONFIG_SPL_SPI_BUS 0
  290 +#define CONFIG_SPL_SPI_CS 0
  291 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
  292 +
270 293 #endif
271 294  
272 295 #endif
include/configs/tegra-common-post.h
Diff comments   View file @ 5495dae
... ... @@ -66,27 +66,63 @@
66 66 #define BOOT_TARGETS_DHCP ""
67 67 #endif
68 68  
  69 +#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
  70 +#define BOOTCMDS_PXE \
  71 + "bootcmd_pxe=" \
  72 + BOOTCMD_INIT_USB \
  73 + "dhcp; " \
  74 + "if pxe get; then " \
  75 + "pxe boot; " \
  76 + "fi\0"
  77 +#define BOOT_TARGETS_PXE "pxe"
  78 +#else
  79 +#define BOOTCMDS_PXE ""
  80 +#define BOOT_TARGETS_PXE ""
  81 +#endif
  82 +
69 83 #define BOOTCMDS_COMMON \
70 84 "rootpart=1\0" \
71 85 \
  86 + "do_script_boot=" \
  87 + "load ${devtype} ${devnum}:${rootpart} " \
  88 + "${scriptaddr} ${prefix}${script}; " \
  89 + "source ${scriptaddr}\0" \
  90 + \
72 91 "script_boot=" \
73   - "if load ${devtype} ${devnum}:${rootpart} " \
74   - "${scriptaddr} ${prefix}${script}; then " \
75   - "echo ${script} found! Executing ...;" \
76   - "source ${scriptaddr};" \
77   - "fi;\0" \
  92 + "for script in ${boot_scripts}; do " \
  93 + "if test -e ${devtype} ${devnum}:${rootpart} " \
  94 + "${prefix}${script}; then " \
  95 + "echo Found U-Boot script " \
  96 + "${prefix}${script}; " \
  97 + "run do_script_boot; " \
  98 + "echo SCRIPT FAILED: continuing...; " \
  99 + "fi; " \
  100 + "done\0" \
78 101 \
  102 + "do_sysboot_boot=" \
  103 + "sysboot ${devtype} ${devnum}:${rootpart} any " \
  104 + "${scriptaddr} ${prefix}extlinux.conf\0" \
  105 + \
  106 + "sysboot_boot=" \
  107 + "if test -e ${devtype} ${devnum}:${rootpart} " \
  108 + "${prefix}extlinux.conf; then " \
  109 + "echo Found extlinux config " \
  110 + "${prefix}extlinux.conf; " \
  111 + "run do_sysboot_boot; " \
  112 + "echo SCRIPT FAILED: continuing...; " \
  113 + "fi\0" \
  114 + \
79 115 "scan_boot=" \
80 116 "echo Scanning ${devtype} ${devnum}...; " \
81 117 "for prefix in ${boot_prefixes}; do " \
82   - "for script in ${boot_scripts}; do " \
83   - "run script_boot; " \
84   - "done; " \
85   - "done;\0" \
  118 + "run sysboot_boot; " \
  119 + "run script_boot; " \
  120 + "done\0" \
86 121 \
87 122 "boot_targets=" \
88 123 BOOT_TARGETS_MMC " " \
89 124 BOOT_TARGETS_USB " " \
  125 + BOOT_TARGETS_PXE " " \
90 126 BOOT_TARGETS_DHCP " " \
91 127 "\0" \
92 128 \
... ... @@ -96,7 +132,8 @@
96 132 \
97 133 BOOTCMDS_MMC \
98 134 BOOTCMDS_USB \
99   - BOOTCMDS_DHCP
  135 + BOOTCMDS_DHCP \
  136 + BOOTCMDS_PXE
100 137  
101 138 #define CONFIG_BOOTCOMMAND \
102 139 "set usb_need_init; " \
include/configs/tegra-common.h
Diff comments   View file @ 5495dae
... ... @@ -29,7 +29,6 @@
29 29 #define CONFIG_DISPLAY_BOARDINFO
30 30  
31 31 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
32   -#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
33 32  
34 33 /* Environment */
35 34 #define CONFIG_ENV_VARS_UBOOT_CONFIG
36 35  
37 36  
38 37  
39 38  
40 39  
... ... @@ -69,33 +68,20 @@
69 68 #undef CONFIG_CMD_NET /* network support */
70 69  
71 70 /* turn on command-line edit/hist/auto */
72   -#define CONFIG_CMDLINE_EDITING
73 71 #define CONFIG_COMMAND_HISTORY
74   -#define CONFIG_AUTO_COMPLETE
75 72  
76 73 /* turn on commonly used storage-related commands */
77   -
78   -#define CONFIG_DOS_PARTITION
79   -#define CONFIG_EFI_PARTITION
80 74 #define CONFIG_PARTITION_UUIDS
81   -#define CONFIG_FS_EXT4
82   -#define CONFIG_FS_FAT
83   -#define CONFIG_CMD_EXT2
84   -#define CONFIG_CMD_FAT
85   -#define CONFIG_CMD_FS_GENERIC
86 75 #define CONFIG_CMD_PART
87 76  
88 77 #define CONFIG_SYS_NO_FLASH
89 78  
90 79 #define CONFIG_CONSOLE_MUX
91 80 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
92   -#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
93 81  
94 82 /*
95 83 * Miscellaneous configurable options
96 84 */
97   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
98   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
99 85 #define CONFIG_SYS_PROMPT V_PROMPT
100 86 /*
101 87 * Increasing the size of the IO buffer as default nfsargs size is more
... ... @@ -133,8 +119,6 @@
133 119 #define CONFIG_TEGRA_GPIO
134 120 #define CONFIG_CMD_GPIO
135 121 #define CONFIG_CMD_ENTERRCM
136   -#define CONFIG_CMD_BOOTZ
137   -#define CONFIG_SUPPORT_RAW_INITRD
138 122  
139 123 /* Defines for SPL */
140 124 #define CONFIG_SPL
... ... @@ -160,6 +144,10 @@
160 144 /* Misc utility code */
161 145 #define CONFIG_BOUNCE_BUFFER
162 146 #define CONFIG_CRC32_VERIFY
  147 +
  148 +#ifndef CONFIG_SPL_BUILD
  149 +#include <config_distro_defaults.h>
  150 +#endif
163 151  
164 152 #endif /* _TEGRA_COMMON_H_ */
include/configs/tegra114-common.h
Diff comments   View file @ 5495dae
... ... @@ -26,11 +26,6 @@
26 26 */
27 27 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
28 28  
29   -/*
30   - * High Level Configuration Options
31   - */
32   -#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
33   -
34 29 /* Environment information, boards can override if required */
35 30 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
36 31  
... ... @@ -51,6 +46,9 @@
51 46 * scriptaddr can be pretty much anywhere that doesn't conflict with something
52 47 * else. Put it above BOOTMAPSZ to eliminate conflicts.
53 48 *
  49 + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  50 + * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  51 + *
54 52 * kernel_addr_r must be within the first 128M of RAM in order for the
55 53 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
56 54 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
... ... @@ -68,6 +66,7 @@
68 66 */
69 67 #define MEM_LAYOUT_ENV_SETTINGS \
70 68 "scriptaddr=0x90000000\0" \
  69 + "pxefile_addr_r=0x90100000\0" \
71 70 "kernel_addr_r=0x81000000\0" \
72 71 "fdt_addr_r=0x82000000\0" \
73 72 "ramdisk_addr_r=0x82100000\0"
... ... @@ -83,6 +82,7 @@
83 82 /* For USB EHCI controller */
84 83 #define CONFIG_EHCI_IS_TDI
85 84 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
  85 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
86 86  
87 87 #endif /* _TEGRA114_COMMON_H_ */
include/configs/tegra124-common.h
Diff comments   View file @ 5495dae
... ... @@ -18,11 +18,6 @@
18 18 */
19 19 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
20 20  
21   -/*
22   - * High Level Configuration Options
23   - */
24   -#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
25   -
26 21 /* Environment information, boards can override if required */
27 22 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
28 23  
... ... @@ -79,6 +74,7 @@
79 74 /* For USB EHCI controller */
80 75 #define CONFIG_EHCI_IS_TDI
81 76 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
  77 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
82 78  
83 79 #endif /* _TEGRA124_COMMON_H_ */
include/configs/tegra20-common.h
Diff comments   View file @ 5495dae
... ... @@ -24,11 +24,6 @@
24 24 */
25 25 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
26 26  
27   -/*
28   - * High Level Configuration Options
29   - */
30   -#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
31   -
32 27 /* Environment information, boards can override if required */
33 28 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
34 29  
... ... @@ -49,6 +44,9 @@
49 44 * scriptaddr can be pretty much anywhere that doesn't conflict with something
50 45 * else. Put it above BOOTMAPSZ to eliminate conflicts.
51 46 *
  47 + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  48 + * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  49 + *
52 50 * kernel_addr_r must be within the first 128M of RAM in order for the
53 51 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
54 52 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
... ... @@ -66,6 +64,7 @@
66 64 */
67 65 #define MEM_LAYOUT_ENV_SETTINGS \
68 66 "scriptaddr=0x10000000\0" \
  67 + "pxefile_addr_r=0x10100000\0" \
69 68 "kernel_addr_r=0x01000000\0" \
70 69 "fdt_addr_r=0x02000000\0" \
71 70 "ramdisk_addr_r=0x02100000\0"
... ... @@ -96,6 +95,7 @@
96 95 */
97 96 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
98 97 #define CONFIG_EHCI_IS_TDI
  98 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
99 99  
100 100 /* Total I2C ports on Tegra20 */
101 101 #define TEGRA_I2C_NUM_CONTROLLERS 4
include/configs/tegra30-common.h
Diff comments   View file @ 5495dae
... ... @@ -23,11 +23,6 @@
23 23 */
24 24 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
25 25  
26   -/*
27   - * High Level Configuration Options
28   - */
29   -#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
30   -
31 26 /* Environment information, boards can override if required */
32 27 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
33 28  
... ... @@ -48,6 +43,9 @@
48 43 * scriptaddr can be pretty much anywhere that doesn't conflict with something
49 44 * else. Put it above BOOTMAPSZ to eliminate conflicts.
50 45 *
  46 + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  47 + * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  48 + *
51 49 * kernel_addr_r must be within the first 128M of RAM in order for the
52 50 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
53 51 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
... ... @@ -65,6 +63,7 @@
65 63 */
66 64 #define MEM_LAYOUT_ENV_SETTINGS \
67 65 "scriptaddr=0x90000000\0" \
  66 + "pxefile_addr_r=0x90100000\0" \
68 67 "kernel_addr_r=0x81000000\0" \
69 68 "fdt_addr_r=0x82000000\0" \
70 69 "ramdisk_addr_r=0x82100000\0"
... ... @@ -80,6 +79,7 @@
80 79 /* For USB EHCI controller */
81 80 #define CONFIG_EHCI_IS_TDI
82 81 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
  82 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
83 83  
84 84 #endif /* _TEGRA30_COMMON_H_ */
include/configs/ti814x_evm.h
Diff comments   View file @ 5495dae
... ... @@ -233,7 +233,6 @@
233 233 #define CONFIG_NET_MULTI
234 234 #define CONFIG_PHY_GIGE
235 235 #define CONFIG_PHYLIB
236   -#define CONFIG_PHY_ADDR 1
237 236 #define CONFIG_PHY_ET1011C
238 237 #define CONFIG_PHY_ET1011C_TX_CLK_FIX
239 238  
include/configs/ti_am335x_common.h
Diff comments   View file @ 5495dae
... ... @@ -30,6 +30,7 @@
30 30 /* Network defines. */
31 31 #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
32 32 #define CONFIG_CMD_DHCP
  33 +#define CONFIG_CMD_MII
33 34 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
34 35 #define CONFIG_BOOTP_DNS2
35 36 #define CONFIG_BOOTP_SEND_HOSTNAME
... ... @@ -19,7 +19,7 @@
19 19 struct cpsw_slave_data {
20 20 u32 slave_reg_ofs;
21 21 u32 sliver_reg_ofs;
22   - int phy_id;
  22 + int phy_addr;
23 23 int phy_if;
24 24 };
25 25  
... ... @@ -21,9 +21,15 @@
21 21 * at the same time, so do it here. When all drivers are
22 22 * converted, this will go away.
23 23 */
  24 +#ifdef CONFIG_SPL_BUILD
  25 +#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
  26 +#define CONFIG_SYS_NAND_SELF_INIT
  27 +#endif
  28 +#else
24 29 #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
25 30 || defined(CONFIG_NAND_FSL_IFC)
26 31 #define CONFIG_SYS_NAND_SELF_INIT
  32 +#endif
27 33 #endif
28 34  
29 35 extern void nand_init(void);