Eric Lee / smarc-uboot

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Commit 54eac8b3a3cc4c05d981ecefc8bcd5151f0d928c

Authored by Marek Vasut
Committed by Marek Vasut
1 parent 58300f399f
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

sh: rsk7269: Remove the board 

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Showing 8 changed files with 0 additions and 337 deletions Side-by-side Diff

... ... @@ -31,10 +31,6 @@
31 31 prompt "Target select"
32 32 optional
33 33  
34   -config TARGET_RSK7269
35   - bool "RSK2+SH7269"
36   - select CPU_SH2A
37   -
38 34 config TARGET_MPR2
39 35 bool "Magic Panel Release 2 board"
40 36 select CPU_SH3
... ... @@ -122,7 +118,6 @@
122 118 source "board/renesas/r0p7734/Kconfig"
123 119 source "board/renesas/r2dplus/Kconfig"
124 120 source "board/renesas/r7780mp/Kconfig"
125   -source "board/renesas/rsk7269/Kconfig"
126 121 source "board/renesas/sh7752evb/Kconfig"
127 122 source "board/renesas/sh7753evb/Kconfig"
128 123 source "board/renesas/sh7757lcr/Kconfig"
board/renesas/rsk7269/Kconfig
View file @ 54eac8b
1   -if TARGET_RSK7269
2   -
3   -config SYS_BOARD
4   - default "rsk7269"
5   -
6   -config SYS_VENDOR
7   - default "renesas"
8   -
9   -config SYS_CONFIG_NAME
10   - default "rsk7269"
11   -
12   -endif
board/renesas/rsk7269/MAINTAINERS
View file @ 54eac8b
1   -RSK7269 BOARD
2   -#M: -
3   -S: Maintained
4   -F: board/renesas/rsk7269/
5   -F: include/configs/rsk7269.h
6   -F: configs/rsk7269_defconfig
board/renesas/rsk7269/Makefile
View file @ 54eac8b
1   -# SPDX-License-Identifier: GPL-2.0+
2   -#
3   -# Copyright (C) 2012 Renesas Electronics Europe Ltd.
4   -# Copyright (C) 2012 Phil Edworthy
5   -#
6   -
7   -obj-y := rsk7269.o
8   -extra-y += lowlevel_init.o
board/renesas/rsk7269/lowlevel_init.S
View file @ 54eac8b
1   -/* SPDX-License-Identifier: GPL-2.0+ */
2   -/*
3   - * Copyright (C) 2012 Renesas Electronics Europe Ltd.
4   - * Copyright (C) 2012 Phil Edworthy
5   - * Copyright (C) 2008 Renesas Solutions Corp.
6   - * Copyright (C) 2008 Nobuhiro Iwamatsu
7   - *
8   - * Based on board/renesas/rsk7264/lowlevel_init.S
9   - */
10   -#include <config.h>
11   -
12   -#include <asm/processor.h>
13   -#include <asm/macro.h>
14   -
15   - .global lowlevel_init
16   -
17   - .text
18   - .align 2
19   -
20   -lowlevel_init:
21   - /* Flush and enable caches (data cache in write-through mode) */
22   - write32 CCR1_A ,CCR1_D
23   -
24   - /* Disable WDT */
25   - write16 WTCSR_A, WTCSR_D
26   - write16 WTCNT_A, WTCNT_D
27   -
28   - /* Disable Register Bank interrupts */
29   - write16 IBNR_A, IBNR_D
30   -
31   - /* Set clocks based on 13.225MHz xtal */
32   - write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
33   -
34   - /* Enable all peripherals */
35   - write8 STBCR3_A, STBCR3_D
36   - write8 STBCR4_A, STBCR4_D
37   - write8 STBCR5_A, STBCR5_D
38   - write8 STBCR6_A, STBCR6_D
39   - write8 STBCR7_A, STBCR7_D
40   - write8 STBCR8_A, STBCR8_D
41   - write8 STBCR9_A, STBCR9_D
42   - write8 STBCR10_A, STBCR10_D
43   -
44   - /* SCIF7 and IIC2 */
45   - write16 PJCR3_A, PJCR3_D /* TXD7 */
46   - write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
47   -
48   - /* Configure bus (CS0) */
49   - write16 PFCR3_A, PFCR3_D /* A24 */
50   - write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
51   - write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
52   - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
53   - write32 CS0WCR_A, CS0WCR_D
54   - write32 CS0BCR_A, CS0BCR_D
55   -
56   - /* Configure SDRAM (CS3) */
57   - write16 PCCR2_A, PCCR2_D /* CS3# */
58   - write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
59   - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
60   - write32 CS3BCR_A, CS3BCR_D
61   - write32 CS3WCR_A, CS3WCR_D
62   - write32 SDCR_A, SDCR_D
63   - write32 RTCOR_A, RTCOR_D
64   - write32 RTCSR_A, RTCSR_D
65   -
66   - /* Configure ethernet (CS1) */
67   - write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
68   - write16 PHCR0_A, PHCR0_D
69   - write16 PFCR2_A, PFCR2_D /* CS1# */
70   - write32 CS1BCR_A, CS1BCR_D /* Big endian */
71   - write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
72   - write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
73   - write16 PJIOR1_A, PJIOR1_D
74   -
75   - /* wait 200us */
76   - mov.l REPEAT_D, r3
77   - mov #0, r2
78   -repeat0:
79   - add #1, r2
80   - cmp/hs r3, r2
81   - bf repeat0
82   - nop
83   -
84   - mov.l SDRAM_MODE, r1
85   - mov #0, r0
86   - mov.l r0, @r1
87   -
88   - nop
89   - rts
90   -
91   - .align 4
92   -
93   -CCR1_A: .long CCR1
94   -CCR1_D: .long 0x0000090B
95   -
96   -STBCR3_A: .long 0xFFFE0408
97   -STBCR4_A: .long 0xFFFE040C
98   -STBCR5_A: .long 0xFFFE0410
99   -STBCR6_A: .long 0xFFFE0414
100   -STBCR7_A: .long 0xFFFE0418
101   -STBCR8_A: .long 0xFFFE041C
102   -STBCR9_A: .long 0xFFFE0440
103   -STBCR10_A: .long 0xFFFE0444
104   -STBCR3_D: .long 0x0000001A
105   -STBCR4_D: .long 0x00000000
106   -STBCR5_D: .long 0x00000000
107   -STBCR6_D: .long 0x00000000
108   -STBCR7_D: .long 0x00000012
109   -STBCR8_D: .long 0x00000009
110   -STBCR9_D: .long 0x00000000
111   -STBCR10_D: .long 0x00000010
112   -
113   -WTCSR_A: .long 0xFFFE0000
114   -WTCNT_A: .long 0xFFFE0002
115   -WTCSR_D: .word 0xA518
116   -WTCNT_D: .word 0x5A00
117   -
118   -IBNR_A: .long 0xFFFE080E
119   -IBNR_D: .word 0x0000
120   -.align 2
121   -FRQCR_A: .long 0xFFFE0010
122   -FRQCR_D: .word 0x0015
123   -.align 2
124   -
125   -PJCR3_A: .long 0xFFFE3908
126   -PJCR3_D: .word 0x5000
127   -.align 2
128   -PECR1_A: .long 0xFFFE388C
129   -PECR1_D: .word 0x2011
130   -.align 2
131   -
132   -PFCR3_A: .long 0xFFFE38A8
133   -PFCR2_A: .long 0xFFFE38AA
134   -PBCR5_A: .long 0xFFFE3824
135   -PFCR3_D: .word 0x0010
136   -PFCR2_D: .word 0x0101
137   -PBCR5_D: .word 0x0111
138   -.align 2
139   -CS0WCR_A: .long 0xFFFC0028
140   -CS0WCR_D: .long 0x00000341
141   -CS0BCR_A: .long 0xFFFC0004
142   -CS0BCR_D: .long 0x00000400
143   -
144   -PCCR2_A: .long 0xFFFE384A
145   -PCCR1_A: .long 0xFFFE384C
146   -PCCR0_A: .long 0xFFFE384E
147   -PCCR2_D: .word 0x0001
148   -PCCR1_D: .word 0x1111
149   -PCCR0_D: .word 0x1111
150   -.align 2
151   -CS3BCR_A: .long 0xFFFC0010
152   -CS3BCR_D: .long 0x00004400
153   -CS3WCR_A: .long 0xFFFC0034
154   -CS3WCR_D: .long 0x00004912
155   -SDCR_A: .long 0xFFFC004C
156   -SDCR_D: .long 0x00000811
157   -RTCOR_A: .long 0xFFFC0058
158   -RTCOR_D: .long 0xA55A0035
159   -RTCSR_A: .long 0xFFFC0050
160   -RTCSR_D: .long 0xA55A0010
161   -.align 2
162   -SDRAM_MODE: .long 0xFFFC5460
163   -REPEAT_D: .long 0x000033F1
164   -
165   -PHCR1_A: .long 0xFFFE38EC
166   -PHCR0_A: .long 0xFFFE38EE
167   -PHCR1_D: .word 0x2222
168   -PHCR0_D: .word 0x2222
169   -.align 2
170   -CS1BCR_A: .long 0xFFFC0008
171   -CS1BCR_D: .long 0x00000400
172   -CS1WCR_A: .long 0xFFFC002C
173   -CS1WCR_D: .long 0x00000080
174   -PJDR1_A: .long 0xFFFE3914
175   -PJDR1_D: .word 0x0000
176   -.align 2
177   -PJIOR1_A: .long 0xFFFE3910
178   -PJIOR1_D: .word 0x8000
179   -.align 2
board/renesas/rsk7269/rsk7269.c
View file @ 54eac8b
1   -// SPDX-License-Identifier: GPL-2.0+
2   -/*
3   - * Copyright (C) 2012 Renesas Electronics Europe Ltd.
4   - * Copyright (C) 2012 Phil Edworthy
5   - * Copyright (C) 2008 Renesas Solutions Corp.
6   - * Copyright (C) 2008 Nobuhiro Iwamatsu
7   - *
8   - * Based on u-boot/board/rsk7264/rsk7264.c
9   - */
10   -
11   -#include <common.h>
12   -#include <net.h>
13   -#include <netdev.h>
14   -#include <asm/io.h>
15   -#include <asm/processor.h>
16   -
17   -int checkboard(void)
18   -{
19   - puts("BOARD: Renesas RSK7269\n");
20   - return 0;
21   -}
22   -
23   -int board_init(void)
24   -{
25   - return 0;
26   -}
27   -
28   -void led_set_state(unsigned short value)
29   -{
30   -}
31   -
32   -/*
33   - * The RSK board has the SMSC89218 wired up 'incorrectly'.
34   - * Byte-swapping is necessary, and so poor performance is inevitable.
35   - * This problem cannot evade by the swap function of CHIP, this can
36   - * evade by software Byte-swapping.
37   - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
38   - * functions necessary to solve this problem.
39   - */
40   -u32 pkt_data_pull(struct eth_device *dev, u32 addr)
41   -{
42   - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
43   - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
44   - | swab16(*(addr_16 + 1));
45   -}
46   -
47   -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
48   -{
49   - addr += dev->iobase;
50   - *(volatile u16 *)(addr + 2) = swab16((u16)val);
51   - *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
52   -}
53   -
54   -int board_eth_init(bd_t *bis)
55   -{
56   - int rc = 0;
57   -#ifdef CONFIG_SMC911X
58   - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
59   -#endif
60   - return rc;
61   -}
configs/rsk7269_defconfig
View file @ 54eac8b
1   -CONFIG_SH=y
2   -CONFIG_SYS_TEXT_BASE=0xDFC0000
3   -CONFIG_TARGET_RSK7269=y
4   -CONFIG_BOOTDELAY=3
5   -CONFIG_USE_BOOTARGS=y
6   -CONFIG_BOOTARGS="console=ttySC7,115200"
7   -# CONFIG_CMDLINE_EDITING is not set
8   -# CONFIG_AUTO_COMPLETE is not set
9   -CONFIG_CMD_IMLS=y
10   -# CONFIG_CMD_SETEXPR is not set
11   -CONFIG_MTD_NOR_FLASH=y
12   -CONFIG_FLASH_CFI_DRIVER=y
13   -CONFIG_SYS_FLASH_CFI=y
14   -CONFIG_SCIF_CONSOLE=y
15   -CONFIG_USE_PRIVATE_LIBGCC=y
include/configs/rsk7269.h
View file @ 54eac8b
1   -/* SPDX-License-Identifier: GPL-2.0+ */
2   -/*
3   - * Configuation settings for the Renesas RSK2+SH7269 board
4   - *
5   - * Copyright (C) 2012 Renesas Electronics Europe Ltd.
6   - * Copyright (C) 2012 Phil Edworthy
7   - */
8   -
9   -#ifndef __RSK7269_H
10   -#define __RSK7269_H
11   -
12   -#define CONFIG_CPU_SH7269 1
13   -
14   -#define CONFIG_DISPLAY_BOARDINFO
15   -
16   -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
17   -
18   -#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
19   -
20   -/* Serial */
21   -#define CONFIG_CONS_SCIF7
22   -
23   -/* Memory */
24   -/* u-boot relocated to top 256KB of ram */
25   -#define CONFIG_SYS_SDRAM_BASE 0x0C000000
26   -#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
27   -
28   -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
29   -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
30   -#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
31   -#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
32   -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
33   -
34   -/* NOR Flash */
35   -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
36   -#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
37   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
38   -#define CONFIG_SYS_MAX_FLASH_SECT 512
39   -
40   -#define CONFIG_ENV_OFFSET (128 * 1024)
41   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
42   -#define CONFIG_ENV_SECT_SIZE (64 * 1024)
43   -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
44   -
45   -/* Board Clock */
46   -#define CONFIG_SYS_CLK_FREQ 66125000
47   -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
48   -#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
49   -#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
50   -
51   -#endif /* __RSK7269_H */