LCD: add data structure for EXYNOS display driver

Add vidinfo data structure for EXYNOS display driver Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Anatolij Gustschin <agust@denx.de>

LCD: add data structure for EXYNOS display driver
Add vidinfo data structure for EXYNOS display driver Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Anatolij Gustschin <agust@denx.de>
Donghwa Lee · Albert ARIBAUD
1 parent 37835d4ba8
Showing 1 changed file with 64 additions and 0 deletions Side-by-side Diff
include/lcd.h
@@ -183,6 +183,70 @@
 	u_long	mmio;		/* Memory mapped registers */
 } vidinfo_t;
  
+#elif defined(CONFIG_EXYNOS_FB)
+
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	void (*cfg_gpio)(void);
+	void (*backlight_on)(unsigned int onoff);
+	void (*reset_lcd)(void);
+	void (*lcd_power_on)(void);
+	void (*cfg_ldo)(void);
+	void (*enable_ldo)(unsigned int onoff);
+	void (*mipi_power)(void);
+	void (*backlight_reset)(void);
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+
+} vidinfo_t;
+
+void init_panel_info(vidinfo_t *vid);
+
 #else
  
 typedef struct vidinfo {
...	...	@@ -183,6 +183,70 @@
183	183	u_long mmio; /* Memory mapped registers */
184	184	} vidinfo_t;
185	185
	186	+#elif defined(CONFIG_EXYNOS_FB)
	187	+
	188	+enum {
	189	+ FIMD_RGB_INTERFACE = 1,
	190	+ FIMD_CPU_INTERFACE = 2,
	191	+};
	192	+
	193	+typedef struct vidinfo {
	194	+ ushort vl_col; /* Number of columns (i.e. 640) */
	195	+ ushort vl_row; /* Number of rows (i.e. 480) */
	196	+ ushort vl_width; /* Width of display area in millimeters */
	197	+ ushort vl_height; /* Height of display area in millimeters */
	198	+
	199	+ /* LCD configuration register */
	200	+ u_char vl_freq; /* Frequency */
	201	+ u_char vl_clkp; /* Clock polarity */
	202	+ u_char vl_oep; /* Output Enable polarity */
	203	+ u_char vl_hsp; /* Horizontal Sync polarity */
	204	+ u_char vl_vsp; /* Vertical Sync polarity */
	205	+ u_char vl_dp; /* Data polarity */
	206	+ u_char vl_bpix; /* Bits per pixel */
	207	+
	208	+ /* Horizontal control register. Timing from data sheet */
	209	+ u_char vl_hspw; /* Horz sync pulse width */
	210	+ u_char vl_hfpd; /* Wait before of line */
	211	+ u_char vl_hbpd; /* Wait end of line */
	212	+
	213	+ /* Vertical control register. */
	214	+ u_char vl_vspw; /* Vertical sync pulse width */
	215	+ u_char vl_vfpd; /* Wait before of frame */
	216	+ u_char vl_vbpd; /* Wait end of frame */
	217	+ u_char vl_cmd_allow_len; /* Wait end of frame */
	218	+
	219	+ void (*cfg_gpio)(void);
	220	+ void (*backlight_on)(unsigned int onoff);
	221	+ void (*reset_lcd)(void);
	222	+ void (*lcd_power_on)(void);
	223	+ void (*cfg_ldo)(void);
	224	+ void (*enable_ldo)(unsigned int onoff);
	225	+ void (*mipi_power)(void);
	226	+ void (*backlight_reset)(void);
	227	+
	228	+ unsigned int win_id;
	229	+ unsigned int init_delay;
	230	+ unsigned int power_on_delay;
	231	+ unsigned int reset_delay;
	232	+ unsigned int interface_mode;
	233	+ unsigned int mipi_enabled;
	234	+ unsigned int cs_setup;
	235	+ unsigned int wr_setup;
	236	+ unsigned int wr_act;
	237	+ unsigned int wr_hold;
	238	+
	239	+ /* parent clock name(MPLL, EPLL or VPLL) */
	240	+ unsigned int pclk_name;
	241	+ /* ratio value for source clock from parent clock. */
	242	+ unsigned int sclk_div;
	243	+
	244	+ unsigned int dual_lcd_enabled;
	245	+
	246	+} vidinfo_t;
	247	+
	248	+void init_panel_info(vidinfo_t *vid);
	249	+
186	250	#else
187	251
188	252	typedef struct vidinfo {