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Commit 564964bd8527667bf88a47890d73cac5eec16c55

Authored by Marek Vasut
Committed by Wolfgang Denk
1 parent be547c6db3
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

GCC4.6: Squash warnings in ipu_disp.c 

ipu_disp.c: In function ‘ipu_disp_set_global_alpha’:
ipu_disp.c:1237:11: warning: variable ‘flow’ set but not used
[-Wunused-but-set-variable]
ipu_disp.c: In function ‘ipu_disp_set_color_key’:
ipu_disp.c:1302:16: warning: variable ‘flow’ set but not used
[-Wunused-but-set-variable]

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

Showing 2 changed files with 48 additions and 57 deletions Side-by-side Diff

drivers/video/ipu_disp.c
Diff comments   View file @ 564964b
... ... @@ -399,29 +399,29 @@
399 399 const int (*coeff)[5][3];
400 400  
401 401 if (dp_csc_param.mode >= 0) {
402   - reg = __raw_readl(DP_COM_CONF(dp));
  402 + reg = __raw_readl(DP_COM_CONF());
403 403 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
404 404 reg |= dp_csc_param.mode;
405   - __raw_writel(reg, DP_COM_CONF(dp));
  405 + __raw_writel(reg, DP_COM_CONF());
406 406 }
407 407  
408 408 coeff = dp_csc_param.coeff;
409 409  
410 410 if (coeff) {
411 411 __raw_writel(mask_a((*coeff)[0][0]) |
412   - (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
  412 + (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
413 413 __raw_writel(mask_a((*coeff)[0][2]) |
414   - (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
  414 + (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
415 415 __raw_writel(mask_a((*coeff)[1][1]) |
416   - (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
  416 + (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
417 417 __raw_writel(mask_a((*coeff)[2][0]) |
418   - (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
  418 + (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
419 419 __raw_writel(mask_a((*coeff)[2][2]) |
420 420 (mask_b((*coeff)[3][0]) << 16) |
421   - ((*coeff)[4][0] << 30), DP_CSC_0(dp));
  421 + ((*coeff)[4][0] << 30), DP_CSC_0());
422 422 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
423 423 (mask_b((*coeff)[3][2]) << 16) |
424   - ((*coeff)[4][2] << 30), DP_CSC_1(dp));
  424 + ((*coeff)[4][2] << 30), DP_CSC_1());
425 425 }
426 426  
427 427 if (srm_mode_update) {
... ... @@ -481,7 +481,7 @@
481 481 }
482 482  
483 483 /* Transform color key from rgb to yuv if CSC is enabled */
484   - reg = __raw_readl(DP_COM_CONF(dp));
  484 + reg = __raw_readl(DP_COM_CONF());
485 485 if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
486 486 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
487 487 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
... ... @@ -489,7 +489,7 @@
489 489 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
490 490 int red, green, blue;
491 491 int y, u, v;
492   - uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) &
  492 + uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
493 493 0xFFFFFFL;
494 494  
495 495 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
... ... @@ -504,8 +504,8 @@
504 504 v = rgb_to_yuv(2, red, green, blue);
505 505 color_key = (y << 16) | (u << 8) | v;
506 506  
507   - reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
508   - __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp));
  507 + reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
  508 + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
509 509 color_key_4rgb = 0;
510 510  
511 511 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
... ... @@ -648,8 +648,8 @@
648 648  
649 649 if (channel == MEM_FG_SYNC) {
650 650 /* Enable FG channel */
651   - reg = __raw_readl(DP_COM_CONF(DP_SYNC));
652   - __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
  651 + reg = __raw_readl(DP_COM_CONF());
  652 + __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
653 653  
654 654 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
655 655 __raw_writel(reg, IPU_SRM_PRI2);
656 656  
... ... @@ -692,13 +692,13 @@
692 692 /* Disable FG channel */
693 693 dc_chan = 5;
694 694  
695   - reg = __raw_readl(DP_COM_CONF(DP_SYNC));
  695 + reg = __raw_readl(DP_COM_CONF());
696 696 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
697 697 if (csc == DP_COM_CONF_CSC_DEF_FG)
698 698 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
699 699  
700 700 reg &= ~DP_COM_CONF_FG_EN;
701   - __raw_writel(reg, DP_COM_CONF(DP_SYNC));
  701 + __raw_writel(reg, DP_COM_CONF());
702 702  
703 703 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
704 704 __raw_writel(reg, IPU_SRM_PRI2);
705 705  
... ... @@ -1234,17 +1234,12 @@
1234 1234 uint8_t alpha)
1235 1235 {
1236 1236 uint32_t reg;
1237   - uint32_t flow;
1238 1237  
1239 1238 unsigned char bg_chan;
1240 1239  
1241   - if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1242   - flow = DP_SYNC;
1243   - else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1244   - flow = DP_ASYNC0;
1245   - else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1246   - flow = DP_ASYNC1;
1247   - else
  1240 + if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
  1241 + (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
  1242 + (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1248 1243 return -EINVAL;
1249 1244  
1250 1245 if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1251 1246  
1252 1247  
1253 1248  
1254 1249  
1255 1250  
... ... @@ -1257,23 +1252,23 @@
1257 1252 clk_enable(g_ipu_clk);
1258 1253  
1259 1254 if (bg_chan) {
1260   - reg = __raw_readl(DP_COM_CONF(flow));
1261   - __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
  1255 + reg = __raw_readl(DP_COM_CONF());
  1256 + __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1262 1257 } else {
1263   - reg = __raw_readl(DP_COM_CONF(flow));
1264   - __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
  1258 + reg = __raw_readl(DP_COM_CONF());
  1259 + __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1265 1260 }
1266 1261  
1267 1262 if (enable) {
1268   - reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
  1263 + reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1269 1264 __raw_writel(reg | ((uint32_t) alpha << 24),
1270   - DP_GRAPH_WIND_CTRL(flow));
  1265 + DP_GRAPH_WIND_CTRL());
1271 1266  
1272   - reg = __raw_readl(DP_COM_CONF(flow));
1273   - __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
  1267 + reg = __raw_readl(DP_COM_CONF());
  1268 + __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1274 1269 } else {
1275   - reg = __raw_readl(DP_COM_CONF(flow));
1276   - __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
  1270 + reg = __raw_readl(DP_COM_CONF());
  1271 + __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1277 1272 }
1278 1273  
1279 1274 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1280 1275  
... ... @@ -1299,17 +1294,13 @@
1299 1294 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1300 1295 uint32_t color_key)
1301 1296 {
1302   - uint32_t reg, flow;
  1297 + uint32_t reg;
1303 1298 int y, u, v;
1304 1299 int red, green, blue;
1305 1300  
1306   - if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1307   - flow = DP_SYNC;
1308   - else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1309   - flow = DP_ASYNC0;
1310   - else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1311   - flow = DP_ASYNC1;
1312   - else
  1301 + if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
  1302 + (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
  1303 + (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1313 1304 return -EINVAL;
1314 1305  
1315 1306 if (!g_ipu_clk_enabled)
1316 1307  
1317 1308  
... ... @@ -1339,14 +1330,14 @@
1339 1330 }
1340 1331  
1341 1332 if (enable) {
1342   - reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
1343   - __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow));
  1333 + reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
  1334 + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1344 1335  
1345   - reg = __raw_readl(DP_COM_CONF(flow));
1346   - __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
  1336 + reg = __raw_readl(DP_COM_CONF());
  1337 + __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1347 1338 } else {
1348   - reg = __raw_readl(DP_COM_CONF(flow));
1349   - __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
  1339 + reg = __raw_readl(DP_COM_CONF());
  1340 + __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1350 1341 }
1351 1342  
1352 1343 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
drivers/video/ipu_regs.h
Diff comments   View file @ 564964b
... ... @@ -402,15 +402,15 @@
402 402  
403 403 #define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
404 404 IPU_DP_REG_BASE))
405   -#define DP_COM_CONF(flow) (&DP_REG->com_conf_sync)
406   -#define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync)
407   -#define DP_CSC_A_0(flow) (&DP_REG->csca_sync[0])
408   -#define DP_CSC_A_1(flow) (&DP_REG->csca_sync[1])
409   -#define DP_CSC_A_2(flow) (&DP_REG->csca_sync[2])
410   -#define DP_CSC_A_3(flow) (&DP_REG->csca_sync[3])
  405 +#define DP_COM_CONF() (&DP_REG->com_conf_sync)
  406 +#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
  407 +#define DP_CSC_A_0() (&DP_REG->csca_sync[0])
  408 +#define DP_CSC_A_1() (&DP_REG->csca_sync[1])
  409 +#define DP_CSC_A_2() (&DP_REG->csca_sync[2])
  410 +#define DP_CSC_A_3() (&DP_REG->csca_sync[3])
411 411  
412   -#define DP_CSC_0(flow) (&DP_REG->csc_sync[0])
413   -#define DP_CSC_1(flow) (&DP_REG->csc_sync[1])
  412 +#define DP_CSC_0() (&DP_REG->csc_sync[0])
  413 +#define DP_CSC_1() (&DP_REG->csc_sync[1])
414 414  
415 415 /* DC template opcodes */
416 416 #define WROD(lf) (0x18 | (lf << 1))