Eric Lee / smarc-uboot

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Commit 56848428a88f89420ae7acc04bb5805e70c430a3

Authored by York Sun
1 parent 14d5547cf1
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

drivers/ddr/fsl: Adjust bstopre value 

By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.

Signed-off-by: York Sun <yorksun@freescale.com>

Showing 3 changed files with 8 additions and 6 deletions Side-by-side Diff

drivers/ddr/fsl/main.c
Diff comments   View file @ 5684842
... ... @@ -535,7 +535,7 @@
535 535 * which is currently STEP_ASSIGN_ADDRESSES.
536 536 */
537 537 populate_memctl_options(
538   - timing_params[i].all_dimms_registered,
  538 + &timing_params[i],
539 539 &pinfo->memctl_opts[i],
540 540 pinfo->dimm_params[i], i);
541 541 /*
drivers/ddr/fsl/options.c
Diff comments   View file @ 5684842
... ... @@ -499,7 +499,7 @@
499 499 return 0;
500 500 }
501 501  
502   -unsigned int populate_memctl_options(int all_dimms_registered,
  502 +unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
503 503 memctl_options_t *popts,
504 504 dimm_params_t *pdimm,
505 505 unsigned int ctrl_num)
... ... @@ -640,7 +640,7 @@
640 640 popts->ba_intlv_ctl = 0;
641 641  
642 642 /* Memory Organization Parameters */
643   - popts->registered_dimm_en = all_dimms_registered;
  643 + popts->registered_dimm_en = common_dimm->all_dimms_registered;
644 644  
645 645 /* Operational Mode Paramters */
646 646  
647 647  
... ... @@ -778,9 +778,11 @@
778 778 * Set this to 0 for global auto precharge
779 779 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
780 780 * It is not wrong. Any value should be OK. The performance depends on
781   - * applications. There is no one good value for all.
  781 + * applications. There is no one good value for all. One way to set
  782 + * is to use 1/4 of refint value.
782 783 */
783   - popts->bstopre = 0x100;
  784 + popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
  785 + >> 2;
784 786  
785 787 /*
786 788 * Window for four activates -- tFAW
... ... @@ -103,7 +103,7 @@
103 103 const dimm_params_t *dimm_params,
104 104 common_timing_params_t *outpdimm,
105 105 unsigned int number_of_dimms);
106   -unsigned int populate_memctl_options(int all_dimms_registered,
  106 +unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
107 107 memctl_options_t *popts,
108 108 dimm_params_t *pdimm,
109 109 unsigned int ctrl_num);