Commit 568c6c4a6ca21a08faec1e7c02a573edad555617
1 parent
dd8aa7b4cb
Exists in
smarc_8mq-imx_v2020.04_5.4.24_2.1.0
and in
3 other branches
MLK-23241 imx8dx_mek: Add iMX8DX MEK board support
iMX8DX MEK board has similar design with 8QXP MEK. The major changes are 1. DDR changed to 16bits 1GB DDR part 2. USB3.0 is removed and only support OTG on typec port. (No SW change needed) This patch adds new defconfigs and DTS file for this new board. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 8185fa9fa8e48d64d4abf8066bf080f02343d484)
Showing 9 changed files with 383 additions and 1 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi
arch/arm/dts/fsl-imx8dx-mek.dts
arch/arm/mach-imx/imx8/Kconfig
... | ... | @@ -106,6 +106,12 @@ |
106 | 106 | select BOARD_LATE_INIT |
107 | 107 | select IMX8QXP |
108 | 108 | |
109 | +config TARGET_IMX8DX_MEK | |
110 | + bool "Support i.MX8DX MEK board" | |
111 | + select BOARD_LATE_INIT | |
112 | + select SUPPORT_SPL | |
113 | + select IMX8QXP | |
114 | + | |
109 | 115 | endchoice |
110 | 116 | |
111 | 117 | source "board/freescale/imx8qm_mek/Kconfig" |
board/freescale/imx8qxp_mek/Kconfig
board/freescale/imx8qxp_mek/imx8qxp_mek.c
... | ... | @@ -211,7 +211,11 @@ |
211 | 211 | |
212 | 212 | int checkboard(void) |
213 | 213 | { |
214 | +#ifdef CONFIG_TARGET_IMX8DX_MEK | |
215 | + puts("Board: iMX8DX MEK\n"); | |
216 | +#else | |
214 | 217 | puts("Board: iMX8QXP MEK\n"); |
218 | +#endif | |
215 | 219 | |
216 | 220 | build_info(); |
217 | 221 | print_bootinfo(); |
218 | 222 | |
... | ... | @@ -375,8 +379,12 @@ |
375 | 379 | |
376 | 380 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
377 | 381 | env_set("board_name", "MEK"); |
382 | +#ifdef CONFIG_TARGET_IMX8DX_MEK | |
383 | + env_set("board_rev", "iMX8DX"); | |
384 | +#else | |
378 | 385 | env_set("board_rev", "iMX8QXP"); |
379 | 386 | #endif |
387 | +#endif | |
380 | 388 | |
381 | 389 | env_set("sec_boot", "no"); |
382 | 390 | #ifdef CONFIG_AHAB_BOOT |
383 | 391 | |
384 | 392 | |
... | ... | @@ -387,10 +395,17 @@ |
387 | 395 | m4_boot = check_m4_parts_boot(); |
388 | 396 | |
389 | 397 | if (fdt_file && !strcmp(fdt_file, "undefined")) { |
398 | +#ifdef CONFIG_TARGET_IMX8DX_MEK | |
390 | 399 | if (m4_boot) |
400 | + env_set("fdt_file", "fsl-imx8dx-mek-rpmsg.dtb"); | |
401 | + else | |
402 | + env_set("fdt_file", "fsl-imx8dx-mek.dtb"); | |
403 | +#else | |
404 | + if (m4_boot) | |
391 | 405 | env_set("fdt_file", "fsl-imx8qxp-mek-rpmsg.dtb"); |
392 | 406 | else |
393 | 407 | env_set("fdt_file", "fsl-imx8qxp-mek.dtb"); |
408 | +#endif | |
394 | 409 | } |
395 | 410 | |
396 | 411 | #ifdef CONFIG_ENV_IS_IN_MMC |
configs/imx8dx_mek_defconfig
1 | +CONFIG_ARM=y | |
2 | +CONFIG_SPL_SYS_ICACHE_OFF=y | |
3 | +CONFIG_SPL_SYS_DCACHE_OFF=y | |
4 | +CONFIG_ARCH_IMX8=y | |
5 | +CONFIG_SYS_TEXT_BASE=0x80020000 | |
6 | +CONFIG_SPL_GPIO_SUPPORT=y | |
7 | +CONFIG_SPL_LIBCOMMON_SUPPORT=y | |
8 | +CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
9 | +CONFIG_SYS_MALLOC_F_LEN=0x8000 | |
10 | +CONFIG_ENV_SIZE=0x2000 | |
11 | +CONFIG_ENV_OFFSET=0x400000 | |
12 | +CONFIG_DM_GPIO=y | |
13 | +CONFIG_SPL_LOAD_IMX_CONTAINER=y | |
14 | +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" | |
15 | +CONFIG_TARGET_IMX8DX_MEK=y | |
16 | +CONFIG_SPL_MMC_SUPPORT=y | |
17 | +CONFIG_SPL_EFI_PARTITION=n | |
18 | +CONFIG_SPL_DOS_PARTITION=n | |
19 | +CONFIG_SPL_DM_SEQ_ALIAS=y | |
20 | +CONFIG_SPL_SERIAL_SUPPORT=y | |
21 | +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | |
22 | +CONFIG_USE_TINY_PRINTF=y | |
23 | +CONFIG_NR_DRAM_BANKS=4 | |
24 | +CONFIG_SPL=y | |
25 | +CONFIG_PANIC_HANG=y | |
26 | +CONFIG_SPL_TEXT_BASE=0x100000 | |
27 | +CONFIG_OF_SYSTEM_SETUP=y | |
28 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" | |
29 | +CONFIG_BOOTDELAY=3 | |
30 | +CONFIG_LOG=y | |
31 | +CONFIG_SPL_BOARD_INIT=y | |
32 | +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set | |
33 | +CONFIG_SPL_SEPARATE_BSS=y | |
34 | +CONFIG_SPL_POWER_SUPPORT=y | |
35 | +CONFIG_SPL_POWER_DOMAIN=y | |
36 | +CONFIG_SPL_WATCHDOG_SUPPORT=y | |
37 | +CONFIG_HUSH_PARSER=y | |
38 | +CONFIG_CMD_CPU=y | |
39 | +# CONFIG_BOOTM_NETBSD is not set | |
40 | +# CONFIG_CMD_IMPORTENV is not set | |
41 | +CONFIG_CMD_CLK=y | |
42 | +CONFIG_CMD_DM=y | |
43 | +CONFIG_CMD_GPIO=y | |
44 | +CONFIG_CMD_I2C=y | |
45 | +CONFIG_CMD_MMC=y | |
46 | +CONFIG_CMD_DHCP=y | |
47 | +CONFIG_CMD_MII=y | |
48 | +CONFIG_CMD_PING=y | |
49 | +CONFIG_CMD_CACHE=y | |
50 | +CONFIG_CMD_FAT=y | |
51 | +CONFIG_SPL_OF_CONTROL=y | |
52 | +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek" | |
53 | +CONFIG_ENV_IS_IN_MMC=y | |
54 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
55 | +CONFIG_NET_RANDOM_ETHADDR=y | |
56 | +CONFIG_SPL_DM=y | |
57 | +CONFIG_SPL_CLK=y | |
58 | +CONFIG_CLK_IMX8=y | |
59 | +CONFIG_CPU=y | |
60 | +CONFIG_MXC_GPIO=y | |
61 | +CONFIG_DM_PCA953X=y | |
62 | +CONFIG_DM_I2C=y | |
63 | +CONFIG_SYS_I2C_IMX_LPI2C=y | |
64 | +CONFIG_I2C_MUX=y | |
65 | +CONFIG_I2C_MUX_PCA954x=y | |
66 | +CONFIG_MISC=y | |
67 | +CONFIG_DM_MMC=y | |
68 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
69 | +CONFIG_FSL_USDHC=y | |
70 | +CONFIG_MMC_IO_VOLTAGE=y | |
71 | +CONFIG_MMC_UHS_SUPPORT=y | |
72 | +CONFIG_MMC_HS400_SUPPORT=y | |
73 | +CONFIG_EFI_PARTITION=y | |
74 | +CONFIG_PHYLIB=y | |
75 | +CONFIG_PHY_ADDR_ENABLE=y | |
76 | +CONFIG_PHY_ATHEROS=y | |
77 | +CONFIG_DM_ETH=y | |
78 | +CONFIG_PHY_GIGE=y | |
79 | +CONFIG_FEC_MXC_SHARE_MDIO=y | |
80 | +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 | |
81 | +CONFIG_FEC_MXC=y | |
82 | +CONFIG_MII=y | |
83 | +CONFIG_PINCTRL=y | |
84 | +CONFIG_SPL_PINCTRL=y | |
85 | +CONFIG_PINCTRL_IMX8=y | |
86 | +CONFIG_POWER_DOMAIN=y | |
87 | +CONFIG_IMX8_POWER_DOMAIN=y | |
88 | +CONFIG_DM_REGULATOR=y | |
89 | +CONFIG_SPL_DM_REGULATOR=y | |
90 | +CONFIG_DM_REGULATOR_FIXED=y | |
91 | +CONFIG_DM_REGULATOR_GPIO=y | |
92 | +CONFIG_SPL_DM_REGULATOR_FIXED=y | |
93 | +CONFIG_DM_SERIAL=y | |
94 | +CONFIG_FSL_LPUART=y | |
95 | +CONFIG_SPL_TINY_MEMSET=y | |
96 | +# CONFIG_EFI_LOADER is not set | |
97 | + | |
98 | +CONFIG_CMD_FUSE=y | |
99 | +CONFIG_SMC_FUSE=y | |
100 | +CONFIG_CMD_MEMTEST=y | |
101 | + | |
102 | +CONFIG_IMX_BOOTAUX=y | |
103 | + | |
104 | +CONFIG_DM_THERMAL=y | |
105 | +CONFIG_IMX_SCU_THERMAL=y | |
106 | + | |
107 | +CONFIG_SPI=y | |
108 | +CONFIG_FSL_FSPI=y | |
109 | +CONFIG_DM_SPI=y | |
110 | +CONFIG_DM_SPI_FLASH=y | |
111 | +CONFIG_SPI_FLASH=y | |
112 | +CONFIG_SPI_FLASH_STMICRO=y | |
113 | +CONFIG_CMD_SF=y | |
114 | +CONFIG_SF_DEFAULT_BUS=0 | |
115 | +CONFIG_SF_DEFAULT_CS=0 | |
116 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
117 | +CONFIG_SF_DEFAULT_MODE=0 | |
118 | + | |
119 | +CONFIG_USB_XHCI_HCD=y | |
120 | +CONFIG_USB_XHCI_IMX8=y | |
121 | +CONFIG_DM_USB=y | |
122 | +CONFIG_DM_USB_GADGET=y | |
123 | +CONFIG_SPL_DM_USB_GADGET=y | |
124 | +CONFIG_USB=y | |
125 | +CONFIG_USB_TCPC=y | |
126 | +CONFIG_USB_GADGET=y | |
127 | +CONFIG_CI_UDC=y | |
128 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
129 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
130 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
131 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
132 | +CONFIG_USB_CDNS3=y | |
133 | +CONFIG_USB_CDNS3_GADGET=y | |
134 | +CONFIG_USB_GADGET_DUALSPEED=y | |
135 | +CONFIG_CDNS3_USB_PHY=y | |
136 | +CONFIG_PHY=y | |
137 | +CONFIG_SPL_PHY=y | |
138 | + | |
139 | +CONFIG_SPL_USB_GADGET=y | |
140 | +CONFIG_SPL_USB_SDP_SUPPORT=y | |
141 | +CONFIG_SPL_SDP_USB_DEV=1 | |
142 | +CONFIG_SDP_LOADADDR=0x80400000 | |
143 | + | |
144 | +CONFIG_FASTBOOT=y | |
145 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
146 | +CONFIG_CMD_FASTBOOT=y | |
147 | +CONFIG_ANDROID_BOOT_IMAGE=y | |
148 | +CONFIG_FASTBOOT_UUU_SUPPORT=y | |
149 | +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 | |
150 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
151 | +CONFIG_FASTBOOT_FLASH=y | |
152 | +CONFIG_FASTBOOT_USB_DEV=1 | |
153 | + | |
154 | +CONFIG_SYS_I2C_IMX_VIRT_I2C=y | |
155 | +CONFIG_I2C_MUX_IMX_VIRT=y | |
156 | +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 | |
157 | + | |
158 | +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 | |
159 | +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 | |
160 | + | |
161 | +CONFIG_REGMAP=y | |
162 | +CONFIG_SYSCON=y | |
163 | +CONFIG_PCI=y | |
164 | +CONFIG_DM_PCI=y | |
165 | + | |
166 | +CONFIG_USB_PORT_AUTO=y | |
167 | + | |
168 | +CONFIG_SNVS_SEC_SC=y |
configs/imx8dx_mek_fspi_defconfig
1 | +CONFIG_ARM=y | |
2 | +CONFIG_SPL_SYS_ICACHE_OFF=y | |
3 | +CONFIG_SPL_SYS_DCACHE_OFF=y | |
4 | +CONFIG_ARCH_IMX8=y | |
5 | +CONFIG_SYS_TEXT_BASE=0x80020000 | |
6 | +CONFIG_SPL_LIBCOMMON_SUPPORT=y | |
7 | +CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
8 | +CONFIG_SYS_MALLOC_F_LEN=0x8000 | |
9 | +CONFIG_ENV_SIZE=0x2000 | |
10 | +CONFIG_ENV_OFFSET=0x400000 | |
11 | +CONFIG_DM_GPIO=y | |
12 | +CONFIG_SPL_LOAD_IMX_CONTAINER=y | |
13 | +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" | |
14 | +CONFIG_TARGET_IMX8DX_MEK=y | |
15 | +CONFIG_SPL_SPI_FLASH_SUPPORT=y | |
16 | +CONFIG_SPL_SPI_SUPPORT=y | |
17 | +CONFIG_SPL_SPI_LOAD=y | |
18 | +CONFIG_SPL_SPI_FLASH_TINY=y | |
19 | +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 | |
20 | +CONFIG_SPL_NOR_SUPPORT=y | |
21 | +CONFIG_SPL_EFI_PARTITION=n | |
22 | +CONFIG_SPL_DOS_PARTITION=n | |
23 | +CONFIG_SPL_DM_SEQ_ALIAS=y | |
24 | +CONFIG_SPL_SERIAL_SUPPORT=y | |
25 | +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | |
26 | +CONFIG_USE_TINY_PRINTF=y | |
27 | +CONFIG_NR_DRAM_BANKS=4 | |
28 | +CONFIG_SPL=y | |
29 | +CONFIG_PANIC_HANG=y | |
30 | +CONFIG_SPL_TEXT_BASE=0x100000 | |
31 | +CONFIG_OF_SYSTEM_SETUP=y | |
32 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" | |
33 | +CONFIG_BOOTDELAY=3 | |
34 | +CONFIG_LOG=y | |
35 | +CONFIG_SPL_BOARD_INIT=y | |
36 | +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set | |
37 | +CONFIG_SPL_SEPARATE_BSS=y | |
38 | +CONFIG_SPL_POWER_SUPPORT=y | |
39 | +CONFIG_SPL_POWER_DOMAIN=y | |
40 | +CONFIG_SPL_WATCHDOG_SUPPORT=y | |
41 | +CONFIG_HUSH_PARSER=y | |
42 | +CONFIG_CMD_CPU=y | |
43 | +# CONFIG_BOOTM_NETBSD is not set | |
44 | +# CONFIG_CMD_IMPORTENV is not set | |
45 | +CONFIG_CMD_CLK=y | |
46 | +CONFIG_CMD_DM=y | |
47 | +CONFIG_CMD_GPIO=y | |
48 | +CONFIG_CMD_I2C=y | |
49 | +CONFIG_CMD_MMC=y | |
50 | +CONFIG_CMD_DHCP=y | |
51 | +CONFIG_CMD_MII=y | |
52 | +CONFIG_CMD_PING=y | |
53 | +CONFIG_CMD_CACHE=y | |
54 | +CONFIG_CMD_FAT=y | |
55 | +CONFIG_SPL_OF_CONTROL=y | |
56 | +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek" | |
57 | +CONFIG_ENV_IS_IN_MMC=y | |
58 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
59 | +CONFIG_NET_RANDOM_ETHADDR=y | |
60 | +CONFIG_SPL_DM=y | |
61 | +CONFIG_SPL_CLK=y | |
62 | +CONFIG_CLK_IMX8=y | |
63 | +CONFIG_CPU=y | |
64 | +CONFIG_MXC_GPIO=y | |
65 | +CONFIG_DM_PCA953X=y | |
66 | +CONFIG_DM_I2C=y | |
67 | +CONFIG_SYS_I2C_IMX_LPI2C=y | |
68 | +CONFIG_I2C_MUX=y | |
69 | +CONFIG_I2C_MUX_PCA954x=y | |
70 | +CONFIG_MISC=y | |
71 | +CONFIG_DM_MMC=y | |
72 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
73 | +CONFIG_FSL_USDHC=y | |
74 | +CONFIG_MMC_IO_VOLTAGE=y | |
75 | +CONFIG_MMC_UHS_SUPPORT=y | |
76 | +CONFIG_MMC_HS400_SUPPORT=y | |
77 | +CONFIG_EFI_PARTITION=y | |
78 | +CONFIG_PHYLIB=y | |
79 | +CONFIG_PHY_ADDR_ENABLE=y | |
80 | +CONFIG_PHY_ATHEROS=y | |
81 | +CONFIG_DM_ETH=y | |
82 | +CONFIG_PHY_GIGE=y | |
83 | +CONFIG_FEC_MXC_SHARE_MDIO=y | |
84 | +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 | |
85 | +CONFIG_FEC_MXC=y | |
86 | +CONFIG_MII=y | |
87 | +CONFIG_PINCTRL=y | |
88 | +CONFIG_SPL_PINCTRL=y | |
89 | +CONFIG_PINCTRL_IMX8=y | |
90 | +CONFIG_POWER_DOMAIN=y | |
91 | +CONFIG_IMX8_POWER_DOMAIN=y | |
92 | +CONFIG_DM_REGULATOR=y | |
93 | +CONFIG_DM_REGULATOR_FIXED=y | |
94 | +CONFIG_DM_REGULATOR_GPIO=y | |
95 | +CONFIG_DM_SERIAL=y | |
96 | +CONFIG_FSL_LPUART=y | |
97 | +CONFIG_SPL_TINY_MEMSET=y | |
98 | +# CONFIG_EFI_LOADER is not set | |
99 | + | |
100 | +CONFIG_CMD_FUSE=y | |
101 | +CONFIG_SMC_FUSE=y | |
102 | +CONFIG_CMD_MEMTEST=y | |
103 | + | |
104 | +CONFIG_IMX_BOOTAUX=y | |
105 | + | |
106 | +CONFIG_DM_THERMAL=y | |
107 | +CONFIG_IMX_SCU_THERMAL=y | |
108 | + | |
109 | +CONFIG_SPI=y | |
110 | +CONFIG_FSL_FSPI=y | |
111 | +CONFIG_DM_SPI=y | |
112 | +CONFIG_DM_SPI_FLASH=y | |
113 | +CONFIG_SPI_FLASH=y | |
114 | +CONFIG_SPI_FLASH_STMICRO=y | |
115 | +CONFIG_CMD_SF=y | |
116 | +CONFIG_SF_DEFAULT_BUS=0 | |
117 | +CONFIG_SF_DEFAULT_CS=0 | |
118 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
119 | +CONFIG_SF_DEFAULT_MODE=0 | |
120 | + | |
121 | +CONFIG_USB_XHCI_HCD=y | |
122 | +CONFIG_USB_XHCI_IMX8=y | |
123 | +CONFIG_DM_USB=y | |
124 | +CONFIG_DM_USB_GADGET=y | |
125 | +CONFIG_SPL_DM_USB_GADGET=y | |
126 | +CONFIG_USB=y | |
127 | +CONFIG_USB_TCPC=y | |
128 | +CONFIG_USB_GADGET=y | |
129 | +CONFIG_CI_UDC=y | |
130 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
131 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
132 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
133 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
134 | +CONFIG_USB_CDNS3=y | |
135 | +CONFIG_USB_CDNS3_GADGET=y | |
136 | +CONFIG_USB_GADGET_DUALSPEED=y | |
137 | +CONFIG_CDNS3_USB_PHY=y | |
138 | +CONFIG_PHY=y | |
139 | +CONFIG_SPL_PHY=y | |
140 | + | |
141 | +CONFIG_SPL_USB_GADGET=y | |
142 | +CONFIG_SPL_USB_SDP_SUPPORT=y | |
143 | +CONFIG_SPL_SDP_USB_DEV=1 | |
144 | +CONFIG_SDP_LOADADDR=0x80400000 | |
145 | + | |
146 | +CONFIG_FASTBOOT=y | |
147 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
148 | +CONFIG_CMD_FASTBOOT=y | |
149 | +CONFIG_ANDROID_BOOT_IMAGE=y | |
150 | +CONFIG_FASTBOOT_UUU_SUPPORT=y | |
151 | +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 | |
152 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
153 | +CONFIG_FASTBOOT_FLASH=y | |
154 | +CONFIG_FASTBOOT_USB_DEV=1 | |
155 | + | |
156 | +CONFIG_SYS_I2C_IMX_VIRT_I2C=y | |
157 | +CONFIG_I2C_MUX_IMX_VIRT=y | |
158 | +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90000000 | |
159 | + | |
160 | +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 | |
161 | +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 | |
162 | + | |
163 | +CONFIG_REGMAP=y | |
164 | +CONFIG_SYSCON=y | |
165 | +CONFIG_PCI=y | |
166 | +CONFIG_DM_PCI=y | |
167 | + | |
168 | +CONFIG_USB_PORT_AUTO=y | |
169 | + | |
170 | +CONFIG_SNVS_SEC_SC=y |
include/configs/imx8qxp_mek.h
... | ... | @@ -254,9 +254,15 @@ |
254 | 254 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
255 | 255 | #define PHYS_SDRAM_1 0x80000000 |
256 | 256 | #define PHYS_SDRAM_2 0x880000000 |
257 | + | |
258 | +#ifdef CONFIG_TARGET_IMX8DX_MEK | |
259 | +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ | |
260 | +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ | |
261 | +#else | |
257 | 262 | #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ |
258 | 263 | /* LPDDR4 board total DDR is 3GB */ |
259 | 264 | #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ |
265 | +#endif | |
260 | 266 | |
261 | 267 | #define CONFIG_SYS_MEMTEST_START 0xA0000000 |
262 | 268 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) |