Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 56cb080858fde222522d41d4ffdf9afc0696d963

Authored by Ye Li
1 parent 747e9c9980
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12988 imx: mx6ull Add board support for i.MX6ULL EVK 

Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar
board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok
to work.

The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when
it is needed.

The DDR3 script is using version 1.2:

   File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc

   Test: 3 boards passed memtester.

Build target:

   mx6ull_14x14_evk_defconfig

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 11 changed files with 2088 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/Kconfig
Diff comments   View file @ 56cb080
... ... @@ -176,6 +176,18 @@
176 176 select DM
177 177 select DM_THERMAL
178 178  
  179 +config TARGET_MX6ULL_14X14_EVK
  180 + bool "Support mx6ull_14x14_evk"
  181 + select MX6ULL
  182 + select DM
  183 + select DM_THERMAL
  184 +
  185 +config TARGET_MX6ULL_9X9_EVK
  186 + bool "Support mx6ull_9x9_evk"
  187 + select MX6ULL
  188 + select DM
  189 + select DM_THERMAL
  190 +
179 191 config TARGET_SECOMX6
180 192 bool "secomx6 boards"
181 193  
... ... @@ -224,6 +236,7 @@
224 236 source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
225 237 source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
226 238 source "board/freescale/mx6ull_ddr3_arm2/Kconfig"
  239 +source "board/freescale/mx6ullevk/Kconfig"
227 240 source "board/gateworks/gw_ventana/Kconfig"
228 241 source "board/kosagi/novena/Kconfig"
229 242 source "board/seco/Kconfig"
board/freescale/mx6ullevk/Kconfig
Diff comments   View file @ 56cb080
  1 +if TARGET_MX6ULL_14X14_EVK || TARGET_MX6ULL_9X9_EVK
  2 +
  3 +config SYS_BOARD
  4 + default "mx6ullevk"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx6ullevk"
  11 +
  12 +endif
board/freescale/mx6ullevk/MAINTAINERS
Diff comments   View file @ 56cb080
  1 +MX6ULLEVK BOARD
  2 +M: Peng Fan <peng.fan@nxp.com>
  3 +S: Maintained
  4 +F: board/freescale/mx6ullevk/
  5 +F: include/configs/mx6ullevk.h
  6 +F: configs/mx6ull_14x14_evk_defconfig
  7 +F: configs/mx6ull_9x9_evk_defconfig
board/freescale/mx6ullevk/Makefile
Diff comments   View file @ 56cb080
  1 +# (C) Copyright 2015 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx6ullevk.o
  7 +
  8 +extra-$(CONFIG_USE_PLUGIN) := plugin.bin
  9 +$(obj)/plugin.bin: $(obj)/plugin.o
  10 + $(OBJCOPY) -O binary --gap-fill 0xff $< $@
board/freescale/mx6ullevk/README
Diff comments   View file @ 56cb080
  1 +How to use U-Boot on Freescale MX6ULL 14x14 EVK
  2 +-----------------------------------------------
  3 +
  4 +- Build U-Boot for MX6ULL 14x14 EVK:
  5 +
  6 +$ make mrproper
  7 +$ make mx6ull_14x14_evk_defconfig
  8 +$ make
  9 +
  10 +This will generate the u-boot image u-boot.imx.
  11 +
  12 +- Flash the u-boot image into the micro SD card:
  13 +
  14 +sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync
  15 +
  16 +- Jumper settings:
  17 +
  18 +SW601: 0 0 1 0
  19 +Sw602: 1 0
  20 +
  21 +where 0 means bottom position and 1 means top position (from the
  22 +switch label numbers reference).
  23 +
  24 +- Connect the USB cable between the EVK and the PC for the console.
  25 +(The USB console connector is the one close the push buttons)
  26 +
  27 +- Insert the micro SD card in the board, power it up and U-Boot messages should
  28 +come up.
board/freescale/mx6ullevk/imximage.cfg
Diff comments   View file @ 56cb080
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +/* Enable all clocks */
  54 +DATA 4 0x020c4068 0xffffffff
  55 +DATA 4 0x020c406c 0xffffffff
  56 +DATA 4 0x020c4070 0xffffffff
  57 +DATA 4 0x020c4074 0xffffffff
  58 +DATA 4 0x020c4078 0xffffffff
  59 +DATA 4 0x020c407c 0xffffffff
  60 +DATA 4 0x020c4080 0xffffffff
  61 +
  62 +DATA 4 0x020E04B4 0x000C0000
  63 +DATA 4 0x020E04AC 0x00000000
  64 +DATA 4 0x020E027C 0x00000030
  65 +DATA 4 0x020E0250 0x00000030
  66 +DATA 4 0x020E024C 0x00000030
  67 +DATA 4 0x020E0490 0x00000030
  68 +DATA 4 0x020E0288 0x000C0030
  69 +DATA 4 0x020E0270 0x00000000
  70 +DATA 4 0x020E0260 0x00000030
  71 +DATA 4 0x020E0264 0x00000030
  72 +DATA 4 0x020E04A0 0x00000030
  73 +DATA 4 0x020E0494 0x00020000
  74 +DATA 4 0x020E0280 0x00000030
  75 +DATA 4 0x020E0284 0x00000030
  76 +DATA 4 0x020E04B0 0x00020000
  77 +DATA 4 0x020E0498 0x00000030
  78 +DATA 4 0x020E04A4 0x00000030
  79 +DATA 4 0x020E0244 0x00000030
  80 +DATA 4 0x020E0248 0x00000030
  81 +DATA 4 0x021B001C 0x00008000
  82 +DATA 4 0x021B0800 0xA1390003
  83 +DATA 4 0x021B080C 0x00000004
  84 +DATA 4 0x021B083C 0x41640158
  85 +DATA 4 0x021B0848 0x40403237
  86 +DATA 4 0x021B0850 0x40403C33
  87 +DATA 4 0x021B081C 0x33333333
  88 +DATA 4 0x021B0820 0x33333333
  89 +DATA 4 0x021B082C 0xf3333333
  90 +DATA 4 0x021B0830 0xf3333333
  91 +DATA 4 0x021B08C0 0x00944009
  92 +DATA 4 0x021B08b8 0x00000800
  93 +DATA 4 0x021B0004 0x0002002D
  94 +DATA 4 0x021B0008 0x1B333030
  95 +DATA 4 0x021B000C 0x676B52F3
  96 +DATA 4 0x021B0010 0xB66D0B63
  97 +DATA 4 0x021B0014 0x01FF00DB
  98 +DATA 4 0x021B0018 0x00201740
  99 +DATA 4 0x021B001C 0x00008000
  100 +DATA 4 0x021B002C 0x000026D2
  101 +DATA 4 0x021B0030 0x006B1023
  102 +DATA 4 0x021B0040 0x0000004F
  103 +DATA 4 0x021B0000 0x84180000
  104 +DATA 4 0x021B0890 0x00400000
  105 +DATA 4 0x021B001C 0x02008032
  106 +DATA 4 0x021B001C 0x00008033
  107 +DATA 4 0x021B001C 0x00048031
  108 +DATA 4 0x021B001C 0x15208030
  109 +DATA 4 0x021B001C 0x04008040
  110 +DATA 4 0x021B0020 0x00000800
  111 +DATA 4 0x021B0818 0x00000227
  112 +DATA 4 0x021B0004 0x0002552D
  113 +DATA 4 0x021B0404 0x00011006
  114 +DATA 4 0x021B001C 0x00000000
  115 +
  116 +#endif
board/freescale/mx6ullevk/imximage_lpddr2.cfg
Diff comments   View file @ 56cb080
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x020c4068 0xffffffff
  54 +DATA 4 0x020c406c 0xffffffff
  55 +DATA 4 0x020c4070 0xffffffff
  56 +DATA 4 0x020c4074 0xffffffff
  57 +DATA 4 0x020c4078 0xffffffff
  58 +DATA 4 0x020c407c 0xffffffff
  59 +DATA 4 0x020c4080 0xffffffff
  60 +DATA 4 0x020c4084 0xffffffff
  61 +
  62 +DATA 4 0x020E04B4 0x00080000
  63 +DATA 4 0x020E04AC 0x00000000
  64 +DATA 4 0x020E027C 0x00000030
  65 +DATA 4 0x020E0250 0x00000030
  66 +DATA 4 0x020E024C 0x00000030
  67 +DATA 4 0x020E0490 0x00000030
  68 +DATA 4 0x020E0288 0x00000030
  69 +DATA 4 0x020E0270 0x00000000
  70 +DATA 4 0x020E0260 0x00000000
  71 +DATA 4 0x020E0264 0x00000000
  72 +DATA 4 0x020E04A0 0x00000030
  73 +DATA 4 0x020E0494 0x00020000
  74 +DATA 4 0x020E0280 0x00003030
  75 +DATA 4 0x020E0284 0x00003030
  76 +DATA 4 0x020E04B0 0x00020000
  77 +DATA 4 0x020E0498 0x00000030
  78 +DATA 4 0x020E04A4 0x00000030
  79 +DATA 4 0x020E0244 0x00000030
  80 +DATA 4 0x020E0248 0x00000030
  81 +
  82 +DATA 4 0x021B001C 0x00008000
  83 +DATA 4 0x021B085C 0x1b4700c7
  84 +DATA 4 0x021B0800 0xA1390003
  85 +DATA 4 0x021B0890 0x00470000
  86 +DATA 4 0x021B08b8 0x00000800
  87 +
  88 +DATA 4 0x021B081C 0x33333333
  89 +DATA 4 0x021B0820 0x33333333
  90 +DATA 4 0x021B082C 0xf3333333
  91 +DATA 4 0x021B0830 0xf3333333
  92 +DATA 4 0x021B083C 0x20000000
  93 +DATA 4 0x021B0848 0x4040484F
  94 +DATA 4 0x021B0850 0x40405247
  95 +DATA 4 0x021B08C0 0x00922012
  96 +DATA 4 0x021B08b8 0x00000800
  97 +
  98 +DATA 4 0x021B0004 0x00020012
  99 +DATA 4 0x021B0008 0x00000000
  100 +DATA 4 0x021B000C 0x33374133
  101 +DATA 4 0x021B0010 0x00100A82
  102 +DATA 4 0x021B0038 0x00170557
  103 +DATA 4 0x021B0014 0x00000093
  104 +DATA 4 0x021B0018 0x00001748
  105 +DATA 4 0x021B001C 0x00008000
  106 +DATA 4 0x021B002C 0x0F9F0682
  107 +DATA 4 0x021B0030 0x009F0010
  108 +DATA 4 0x021B0040 0x00000047
  109 +DATA 4 0x021B0000 0x83100000
  110 +DATA 4 0x021B001C 0x003F8030
  111 +DATA 4 0x021B001C 0xFF0A8030
  112 +DATA 4 0x021B001C 0x82018030
  113 +DATA 4 0x021B001C 0x04028030
  114 +DATA 4 0x021B001C 0x01038030
  115 +DATA 4 0x021B0020 0x00001800
  116 +DATA 4 0x021B0818 0x00000000
  117 +DATA 4 0x021B0800 0xA1310003
  118 +DATA 4 0x021B0004 0x00025576
  119 +DATA 4 0x021B0404 0x00011006
  120 +DATA 4 0x021B001C 0x00000000
  121 +#endif
board/freescale/mx6ullevk/mx6ullevk.c
Diff comments   View file @ 56cb080
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/iomux.h>
  9 +#include <asm/arch/imx-regs.h>
  10 +#include <asm/arch/crm_regs.h>
  11 +#include <asm/arch/mx6-pins.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <asm/gpio.h>
  14 +#include <asm/imx-common/iomux-v3.h>
  15 +#include <asm/imx-common/boot_mode.h>
  16 +#include <asm/imx-common/mxc_i2c.h>
  17 +#include <asm/io.h>
  18 +#include <common.h>
  19 +#include <fsl_esdhc.h>
  20 +#include <i2c.h>
  21 +#include <miiphy.h>
  22 +#include <linux/sizes.h>
  23 +#include <mmc.h>
  24 +#include <mxsfb.h>
  25 +#include <netdev.h>
  26 +#include <power/pmic.h>
  27 +#include <power/pfuze3000_pmic.h>
  28 +#include "../common/pfuze.h"
  29 +#include <usb.h>
  30 +#include <usb/ehci-fsl.h>
  31 +#include <asm/imx-common/video.h>
  32 +
  33 +#ifdef CONFIG_FSL_FASTBOOT
  34 +#include <fsl_fastboot.h>
  35 +#ifdef CONFIG_ANDROID_RECOVERY
  36 +#include <recovery.h>
  37 +#endif
  38 +#endif /*CONFIG_FSL_FASTBOOT*/
  39 +
  40 +DECLARE_GLOBAL_DATA_PTR;
  41 +
  42 +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  43 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  44 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45 +
  46 +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  47 + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  48 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  49 +
  50 +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  51 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  52 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  53 +
  54 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  55 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  56 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  57 + PAD_CTL_ODE)
  58 +
  59 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  60 + PAD_CTL_SPEED_HIGH | \
  61 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  62 +
  63 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  64 + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  65 +
  66 +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  67 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  68 +
  69 +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  70 +
  71 +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  72 + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  73 +
  74 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  75 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  76 + PAD_CTL_SRE_FAST)
  77 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  78 +
  79 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  80 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  81 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  82 +
  83 +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
  84 + PAD_CTL_SPEED_MED | \
  85 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  86 +
  87 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  88 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  89 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  90 +
  91 +#define IOX_SDI IMX_GPIO_NR(5, 10)
  92 +#define IOX_STCP IMX_GPIO_NR(5, 7)
  93 +#define IOX_SHCP IMX_GPIO_NR(5, 11)
  94 +#define IOX_OE IMX_GPIO_NR(5, 8)
  95 +
  96 +static iomux_v3_cfg_t const iox_pads[] = {
  97 + /* IOX_SDI */
  98 + MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  99 + /* IOX_SHCP */
  100 + MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  101 + /* IOX_STCP */
  102 + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  103 + /* IOX_nOE */
  104 + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  105 +};
  106 +
  107 +/*
  108 + * HDMI_nRST --> Q0
  109 + * ENET1_nRST --> Q1
  110 + * ENET2_nRST --> Q2
  111 + * CAN1_2_STBY --> Q3
  112 + * BT_nPWD --> Q4
  113 + * CSI_RST --> Q5
  114 + * CSI_PWDN --> Q6
  115 + * LCD_nPWREN --> Q7
  116 + */
  117 +enum qn {
  118 + HDMI_NRST,
  119 + ENET1_NRST,
  120 + ENET2_NRST,
  121 + CAN1_2_STBY,
  122 + BT_NPWD,
  123 + CSI_RST,
  124 + CSI_PWDN,
  125 + LCD_NPWREN,
  126 +};
  127 +
  128 +enum qn_func {
  129 + qn_reset,
  130 + qn_enable,
  131 + qn_disable,
  132 +};
  133 +
  134 +enum qn_level {
  135 + qn_low = 0,
  136 + qn_high = 1,
  137 +};
  138 +
  139 +static enum qn_level seq[3][2] = {
  140 + {0, 1}, {1, 1}, {0, 0}
  141 +};
  142 +
  143 +static enum qn_func qn_output[8] = {
  144 + qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
  145 + qn_disable, qn_disable
  146 +};
  147 +
  148 +static void iox74lv_init(void)
  149 +{
  150 + int i;
  151 +
  152 + gpio_direction_output(IOX_OE, 0);
  153 +
  154 + for (i = 7; i >= 0; i--) {
  155 + gpio_direction_output(IOX_SHCP, 0);
  156 + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
  157 + udelay(500);
  158 + gpio_direction_output(IOX_SHCP, 1);
  159 + udelay(500);
  160 + }
  161 +
  162 + gpio_direction_output(IOX_STCP, 0);
  163 + udelay(500);
  164 + /*
  165 + * shift register will be output to pins
  166 + */
  167 + gpio_direction_output(IOX_STCP, 1);
  168 +
  169 + for (i = 7; i >= 0; i--) {
  170 + gpio_direction_output(IOX_SHCP, 0);
  171 + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
  172 + udelay(500);
  173 + gpio_direction_output(IOX_SHCP, 1);
  174 + udelay(500);
  175 + }
  176 + gpio_direction_output(IOX_STCP, 0);
  177 + udelay(500);
  178 + /*
  179 + * shift register will be output to pins
  180 + */
  181 + gpio_direction_output(IOX_STCP, 1);
  182 +};
  183 +
  184 +void iox74lv_set(int index)
  185 +{
  186 + int i;
  187 +
  188 + for (i = 7; i >= 0; i--) {
  189 + gpio_direction_output(IOX_SHCP, 0);
  190 +
  191 + if (i == index)
  192 + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
  193 + else
  194 + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
  195 + udelay(500);
  196 + gpio_direction_output(IOX_SHCP, 1);
  197 + udelay(500);
  198 + }
  199 +
  200 + gpio_direction_output(IOX_STCP, 0);
  201 + udelay(500);
  202 + /*
  203 + * shift register will be output to pins
  204 + */
  205 + gpio_direction_output(IOX_STCP, 1);
  206 +
  207 + for (i = 7; i >= 0; i--) {
  208 + gpio_direction_output(IOX_SHCP, 0);
  209 + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
  210 + udelay(500);
  211 + gpio_direction_output(IOX_SHCP, 1);
  212 + udelay(500);
  213 + }
  214 +
  215 + gpio_direction_output(IOX_STCP, 0);
  216 + udelay(500);
  217 + /*
  218 + * shift register will be output to pins
  219 + */
  220 + gpio_direction_output(IOX_STCP, 1);
  221 +};
  222 +
  223 +
  224 +#ifdef CONFIG_SYS_I2C_MXC
  225 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  226 +/* I2C1 for PMIC and EEPROM */
  227 +static struct i2c_pads_info i2c_pad_info1 = {
  228 + .scl = {
  229 + .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
  230 + .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
  231 + .gp = IMX_GPIO_NR(1, 28),
  232 + },
  233 + .sda = {
  234 + .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
  235 + .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
  236 + .gp = IMX_GPIO_NR(1, 29),
  237 + },
  238 +};
  239 +
  240 +#ifdef CONFIG_POWER
  241 +#define I2C_PMIC 0
  242 +int power_init_board(void)
  243 +{
  244 + if (is_mx6ull_9x9_evk()) {
  245 + struct pmic *pfuze;
  246 + int ret;
  247 + unsigned int reg, rev_id;
  248 +
  249 + ret = power_pfuze3000_init(I2C_PMIC);
  250 + if (ret)
  251 + return ret;
  252 +
  253 + pfuze = pmic_get("PFUZE3000");
  254 + ret = pmic_probe(pfuze);
  255 + if (ret)
  256 + return ret;
  257 +
  258 + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
  259 + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
  260 + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
  261 + reg, rev_id);
  262 +
  263 + /* disable Low Power Mode during standby mode */
  264 + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
  265 + reg |= 0x1;
  266 + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
  267 +
  268 + /* SW1B step ramp up time from 2us to 4us/25mV */
  269 + reg = 0x40;
  270 + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
  271 +
  272 + /* SW1B mode to APS/PFM */
  273 + reg = 0xc;
  274 + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
  275 +
  276 + /* SW1B standby voltage set to 0.975V */
  277 + reg = 0xb;
  278 + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
  279 + }
  280 +
  281 + return 0;
  282 +}
  283 +
  284 +#ifdef CONFIG_LDO_BYPASS_CHECK
  285 +void ldo_mode_set(int ldo_bypass)
  286 +{
  287 + unsigned int value;
  288 + u32 vddarm;
  289 +
  290 + struct pmic *p = pmic_get("PFUZE3000");
  291 +
  292 + if (!p) {
  293 + printf("No PMIC found!\n");
  294 + return;
  295 + }
  296 +
  297 + /* switch to ldo_bypass mode */
  298 + if (ldo_bypass) {
  299 + prep_anatop_bypass();
  300 + /* decrease VDDARM to 1.275V */
  301 + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
  302 + value &= ~0x1f;
  303 + value |= PFUZE3000_SW1AB_SETP(1275);
  304 + pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
  305 +
  306 + set_anatop_bypass(1);
  307 + vddarm = PFUZE3000_SW1AB_SETP(1175);
  308 +
  309 + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
  310 + value &= ~0x1f;
  311 + value |= vddarm;
  312 + pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
  313 +
  314 + finish_anatop_bypass();
  315 +
  316 + printf("switch to ldo_bypass mode!\n");
  317 + }
  318 +}
  319 +#endif
  320 +#endif
  321 +#endif
  322 +
  323 +int dram_init(void)
  324 +{
  325 + gd->ram_size = imx_ddr_size();
  326 +
  327 + return 0;
  328 +}
  329 +
  330 +static iomux_v3_cfg_t const uart1_pads[] = {
  331 + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  332 + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  333 +};
  334 +
  335 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  336 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  337 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  338 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  339 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  340 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  341 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  342 +
  343 + /* VSELECT */
  344 + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  345 + /* CD */
  346 + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  347 + /* RST_B */
  348 + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  349 +};
  350 +
  351 +/*
  352 + * mx6ull_14x14_evk board default supports sd card. If want to use
  353 + * EMMC, need to do board rework for sd2.
  354 + * Introduce CONFIG_MX6ULL_EVK_EMMC_REWORK, if sd2 reworked to support
  355 + * emmc, need to define this macro.
  356 + */
  357 +#if defined(CONFIG_MX6ULL_EVK_EMMC_REWORK)
  358 +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
  359 + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  360 + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  361 + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  362 + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  363 + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  364 + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  365 + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  366 + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  367 + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  368 + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  369 +
  370 + /*
  371 + * RST_B
  372 + */
  373 + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  374 +};
  375 +#else
  376 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  377 + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  378 + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  379 + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  380 + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  381 + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  382 + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  383 +};
  384 +
  385 +static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
  386 + /*
  387 + * The evk board uses DAT3 to detect CD card plugin,
  388 + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
  389 + */
  390 + MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
  391 +};
  392 +
  393 +static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
  394 + MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
  395 + MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
  396 +};
  397 +#endif
  398 +
  399 +static void setup_iomux_uart(void)
  400 +{
  401 + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  402 +}
  403 +
  404 +#ifdef CONFIG_FSL_QSPI
  405 +
  406 +#define QSPI_PAD_CTRL1 \
  407 + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
  408 + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
  409 +
  410 +static iomux_v3_cfg_t const quadspi_pads[] = {
  411 + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  412 + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  413 + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  414 + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  415 + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  416 + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  417 +};
  418 +
  419 +static int board_qspi_init(void)
  420 +{
  421 + /* Set the iomux */
  422 + imx_iomux_v3_setup_multiple_pads(quadspi_pads,
  423 + ARRAY_SIZE(quadspi_pads));
  424 + /* Set the clock */
  425 + enable_qspi_clk(0);
  426 +
  427 + return 0;
  428 +}
  429 +#endif
  430 +
  431 +#ifdef CONFIG_FSL_ESDHC
  432 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  433 + {USDHC1_BASE_ADDR, 0, 4},
  434 +#if defined(CONFIG_MX6ULL_EVK_EMMC_REWORK)
  435 + {USDHC2_BASE_ADDR, 0, 8},
  436 +#else
  437 + {USDHC2_BASE_ADDR, 0, 4},
  438 +#endif
  439 +};
  440 +
  441 +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
  442 +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
  443 +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
  444 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
  445 +
  446 +int board_mmc_get_env_dev(int devno)
  447 +{
  448 + if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
  449 + devno = 0;
  450 +
  451 + return devno;
  452 +}
  453 +
  454 +int mmc_map_to_kernel_blk(int devno)
  455 +{
  456 + if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
  457 + devno = 1;
  458 +
  459 + return devno;
  460 +}
  461 +
  462 +int board_mmc_getcd(struct mmc *mmc)
  463 +{
  464 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  465 + int ret = 0;
  466 +
  467 + switch (cfg->esdhc_base) {
  468 + case USDHC1_BASE_ADDR:
  469 + ret = !gpio_get_value(USDHC1_CD_GPIO);
  470 + break;
  471 + case USDHC2_BASE_ADDR:
  472 +#if defined(CONFIG_MX6ULL_EVK_EMMC_REWORK)
  473 + ret = 1;
  474 +#else
  475 + imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
  476 + ARRAY_SIZE(usdhc2_cd_pads));
  477 + gpio_direction_input(USDHC2_CD_GPIO);
  478 +
  479 + /*
  480 + * Since it is the DAT3 pin, this pin is pulled to
  481 + * low voltage if no card
  482 + */
  483 + ret = gpio_get_value(USDHC2_CD_GPIO);
  484 +
  485 + imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
  486 + ARRAY_SIZE(usdhc2_dat3_pads));
  487 +#endif
  488 + break;
  489 + }
  490 +
  491 + return ret;
  492 +}
  493 +
  494 +int board_mmc_init(bd_t *bis)
  495 +{
  496 +#ifdef CONFIG_SPL_BUILD
  497 +#if defined(CONFIG_MX6ULL_EVK_EMMC_REWORK)
  498 + imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
  499 + ARRAY_SIZE(usdhc2_emmc_pads));
  500 +#else
  501 + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  502 +#endif
  503 + gpio_direction_output(USDHC2_PWR_GPIO, 0);
  504 + udelay(500);
  505 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  506 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  507 + return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  508 +#else
  509 + int i, ret;
  510 +
  511 + /*
  512 + * According to the board_mmc_init() the following map is done:
  513 + * (U-Boot device node) (Physical Port)
  514 + * mmc0 USDHC1
  515 + * mmc1 USDHC2
  516 + */
  517 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  518 + switch (i) {
  519 + case 0:
  520 + imx_iomux_v3_setup_multiple_pads(
  521 + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  522 + gpio_direction_input(USDHC1_CD_GPIO);
  523 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  524 +
  525 + gpio_direction_output(USDHC1_PWR_GPIO, 0);
  526 + udelay(500);
  527 + gpio_direction_output(USDHC1_PWR_GPIO, 1);
  528 + break;
  529 + case 1:
  530 +#if defined(CONFIG_MX6ULL_EVK_EMMC_REWORK)
  531 + imx_iomux_v3_setup_multiple_pads(
  532 + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
  533 +#else
  534 +#ifndef CONFIG_SYS_USE_NAND
  535 + imx_iomux_v3_setup_multiple_pads(
  536 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  537 +#endif
  538 +#endif
  539 + gpio_direction_output(USDHC2_PWR_GPIO, 0);
  540 + udelay(500);
  541 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  542 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  543 + break;
  544 + default:
  545 + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
  546 + return -EINVAL;
  547 + }
  548 +
  549 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  550 + if (ret) {
  551 + printf("Warning: failed to initialize mmc dev %d\n", i);
  552 + }
  553 + }
  554 +#endif
  555 + return 0;
  556 +}
  557 +#endif
  558 +
  559 +#ifdef CONFIG_USB_EHCI_MX6
  560 +#define USB_OTHERREGS_OFFSET 0x800
  561 +#define UCTRL_PWR_POL (1 << 9)
  562 +
  563 +static iomux_v3_cfg_t const usb_otg_pads[] = {
  564 + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  565 +};
  566 +
  567 +/* At default the 3v3 enables the MIC2026 for VBUS power */
  568 +static void setup_usb(void)
  569 +{
  570 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  571 + ARRAY_SIZE(usb_otg_pads));
  572 +}
  573 +
  574 +int board_usb_phy_mode(int port)
  575 +{
  576 + if (port == 1)
  577 + return USB_INIT_HOST;
  578 + else
  579 + return usb_phy_mode(port);
  580 +}
  581 +
  582 +int board_ehci_hcd_init(int port)
  583 +{
  584 + u32 *usbnc_usb_ctrl;
  585 +
  586 + if (port > 1)
  587 + return -EINVAL;
  588 +
  589 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  590 + port * 4);
  591 +
  592 + /* Set Power polarity */
  593 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  594 +
  595 + return 0;
  596 +}
  597 +#endif
  598 +
  599 +#ifdef CONFIG_NAND_MXS
  600 +static iomux_v3_cfg_t const nand_pads[] = {
  601 + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  602 + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  603 + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  604 + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  605 + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  606 + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  607 + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  608 + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  609 + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  610 + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  611 + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  612 + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  613 + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  614 + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  615 + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  616 + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  617 + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  618 +};
  619 +
  620 +static void setup_gpmi_nand(void)
  621 +{
  622 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  623 +
  624 + /* config gpmi nand iomux */
  625 + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  626 +
  627 + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  628 + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  629 +
  630 + /* enable apbh clock gating */
  631 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  632 +}
  633 +#endif
  634 +
  635 +#ifdef CONFIG_FEC_MXC
  636 +/*
  637 + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  638 + * be used for ENET1 or ENET2, cannot be used for both.
  639 + */
  640 +static iomux_v3_cfg_t const fec1_pads[] = {
  641 + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  642 + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  643 + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  644 + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  645 + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  646 + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  647 + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  648 + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  649 + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  650 + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  651 +};
  652 +
  653 +static iomux_v3_cfg_t const fec2_pads[] = {
  654 + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  655 + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  656 +
  657 + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  658 + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  659 + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  660 + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  661 +
  662 + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  663 + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  664 + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  665 + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  666 +};
  667 +
  668 +static void setup_iomux_fec(int fec_id)
  669 +{
  670 + if (fec_id == 0)
  671 + imx_iomux_v3_setup_multiple_pads(fec1_pads,
  672 + ARRAY_SIZE(fec1_pads));
  673 + else
  674 + imx_iomux_v3_setup_multiple_pads(fec2_pads,
  675 + ARRAY_SIZE(fec2_pads));
  676 +}
  677 +
  678 +int board_eth_init(bd_t *bis)
  679 +{
  680 + setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  681 +
  682 + return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  683 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  684 +}
  685 +
  686 +static int setup_fec(int fec_id)
  687 +{
  688 + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  689 + int ret;
  690 +
  691 + if (fec_id == 0) {
  692 + /*
  693 + * Use 50M anatop loopback REF_CLK1 for ENET1,
  694 + * clear gpr1[13], set gpr1[17].
  695 + */
  696 + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  697 + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  698 + } else {
  699 + /*
  700 + * Use 50M anatop loopback REF_CLK2 for ENET2,
  701 + * clear gpr1[14], set gpr1[18].
  702 + */
  703 + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  704 + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  705 + }
  706 +
  707 + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  708 + if (ret)
  709 + return ret;
  710 +
  711 + enable_enet_clk(1);
  712 +
  713 + return 0;
  714 +}
  715 +
  716 +int board_phy_config(struct phy_device *phydev)
  717 +{
  718 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  719 +
  720 + if (phydev->drv->config)
  721 + phydev->drv->config(phydev);
  722 +
  723 + return 0;
  724 +}
  725 +#endif
  726 +
  727 +#ifdef CONFIG_VIDEO_MXS
  728 +static iomux_v3_cfg_t const lcd_pads[] = {
  729 + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  730 + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  731 + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  732 + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  733 + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  734 + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  735 + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  736 + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  737 + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  738 + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  739 + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  740 + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  741 + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  742 + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  743 + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  744 + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  745 + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  746 + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  747 + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  748 + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  749 + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  750 + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  751 + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  752 + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  753 + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  754 + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  755 + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  756 + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  757 +
  758 + /* LCD_RST */
  759 + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  760 +
  761 + /* Use GPIO for Brightness adjustment, duty cycle = period. */
  762 + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  763 +};
  764 +
  765 +void do_enable_parallel_lcd(struct display_info_t const *dev)
  766 +{
  767 + enable_lcdif_clock(dev->bus);
  768 +
  769 + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  770 +
  771 + /* Reset the LCD */
  772 + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
  773 + udelay(500);
  774 + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
  775 +
  776 + /* Set Brightness to high */
  777 + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
  778 +}
  779 +
  780 +struct display_info_t const displays[] = {{
  781 + .bus = MX6UL_LCDIF1_BASE_ADDR,
  782 + .addr = 0,
  783 + .pixfmt = 24,
  784 + .detect = NULL,
  785 + .enable = do_enable_parallel_lcd,
  786 + .mode = {
  787 + .name = "TFT43AB",
  788 + .xres = 480,
  789 + .yres = 272,
  790 + .pixclock = 108695,
  791 + .left_margin = 8,
  792 + .right_margin = 4,
  793 + .upper_margin = 2,
  794 + .lower_margin = 4,
  795 + .hsync_len = 41,
  796 + .vsync_len = 10,
  797 + .sync = 0,
  798 + .vmode = FB_VMODE_NONINTERLACED
  799 +} } };
  800 +size_t display_count = ARRAY_SIZE(displays);
  801 +#endif
  802 +
  803 +int board_early_init_f(void)
  804 +{
  805 + setup_iomux_uart();
  806 +
  807 + return 0;
  808 +}
  809 +
  810 +int board_init(void)
  811 +{
  812 + /* Address of boot parameters */
  813 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  814 +
  815 + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
  816 +
  817 + iox74lv_init();
  818 +
  819 +#ifdef CONFIG_SYS_I2C_MXC
  820 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  821 +#endif
  822 +
  823 +#ifdef CONFIG_FEC_MXC
  824 + setup_fec(CONFIG_FEC_ENET_DEV);
  825 +#endif
  826 +
  827 +#ifdef CONFIG_USB_EHCI_MX6
  828 + setup_usb();
  829 +#endif
  830 +
  831 +#ifdef CONFIG_FSL_QSPI
  832 + board_qspi_init();
  833 +#endif
  834 +
  835 +#ifdef CONFIG_NAND_MXS
  836 + setup_gpmi_nand();
  837 +#endif
  838 +
  839 + return 0;
  840 +}
  841 +
  842 +#ifdef CONFIG_CMD_BMODE
  843 +static const struct boot_mode board_boot_modes[] = {
  844 + /* 4 bit bus width */
  845 + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  846 + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  847 + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  848 + {NULL, 0},
  849 +};
  850 +#endif
  851 +
  852 +int board_late_init(void)
  853 +{
  854 +#ifdef CONFIG_CMD_BMODE
  855 + add_board_boot_modes(board_boot_modes);
  856 +#endif
  857 +
  858 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  859 + setenv("board_name", "EVK");
  860 +
  861 + if (is_mx6ull_9x9_evk())
  862 + setenv("board_rev", "9X9");
  863 + else
  864 + setenv("board_rev", "14X14");
  865 +#endif
  866 +
  867 +#ifdef CONFIG_ENV_IS_IN_MMC
  868 + board_late_mmc_env_init();
  869 +#endif
  870 +
  871 + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
  872 +
  873 + return 0;
  874 +}
  875 +
  876 +int checkboard(void)
  877 +{
  878 + if (is_mx6ull_9x9_evk())
  879 + puts("Board: MX6ULL 9x9 EVK\n");
  880 + else
  881 + puts("Board: MX6ULL 14x14 EVK\n");
  882 +
  883 + return 0;
  884 +}
  885 +
  886 +#ifdef CONFIG_FSL_FASTBOOT
  887 +void board_fastboot_setup(void)
  888 +{
  889 + switch (get_boot_device()) {
  890 +#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
  891 + case SD1_BOOT:
  892 + case MMC1_BOOT:
  893 + if (!getenv("fastboot_dev"))
  894 + setenv("fastboot_dev", "mmc0");
  895 + if (!getenv("bootcmd"))
  896 + setenv("bootcmd", "boota mmc0");
  897 + break;
  898 + case SD2_BOOT:
  899 + case MMC2_BOOT:
  900 + if (!getenv("fastboot_dev"))
  901 + setenv("fastboot_dev", "mmc1");
  902 + if (!getenv("bootcmd"))
  903 + setenv("bootcmd", "boota mmc1");
  904 + break;
  905 +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
  906 +#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
  907 + case NAND_BOOT:
  908 + if (!getenv("fastboot_dev"))
  909 + setenv("fastboot_dev", "nand");
  910 + if (!getenv("fbparts"))
  911 + setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
  912 + if (!getenv("bootcmd"))
  913 + setenv("bootcmd",
  914 + "nand read ${loadaddr} ${boot_nand_offset} "
  915 + "${boot_nand_size};boota ${loadaddr}");
  916 + break;
  917 +#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
  918 +
  919 + default:
  920 + printf("unsupported boot devices\n");
  921 + break;
  922 + }
  923 +}
  924 +
  925 +#ifdef CONFIG_ANDROID_RECOVERY
  926 +int check_recovery_cmd_file(void)
  927 +{
  928 + int recovery_mode = 0;
  929 +
  930 + recovery_mode = recovery_check_and_clean_flag();
  931 +
  932 + return recovery_mode;
  933 +}
  934 +
  935 +void board_recovery_setup(void)
  936 +{
  937 + int bootdev = get_boot_device();
  938 +
  939 + switch (bootdev) {
  940 +#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
  941 + case SD1_BOOT:
  942 + case MMC1_BOOT:
  943 + if (!getenv("bootcmd_android_recovery"))
  944 + setenv("bootcmd_android_recovery", "boota mmc0 recovery");
  945 + break;
  946 + case SD2_BOOT:
  947 + case MMC2_BOOT:
  948 + if (!getenv("bootcmd_android_recovery"))
  949 + setenv("bootcmd_android_recovery", "boota mmc1 recovery");
  950 + break;
  951 +#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
  952 +#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
  953 + case NAND_BOOT:
  954 + if (!getenv("bootcmd_android_recovery"))
  955 + setenv("bootcmd_android_recovery",
  956 + "nand read ${loadaddr} ${recovery_nand_offset} "
  957 + "${recovery_nand_size};boota ${loadaddr}");
  958 + break;
  959 +#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
  960 +
  961 + default:
  962 + printf("Unsupported bootup device for recovery: dev: %d\n",
  963 + bootdev);
  964 + return;
  965 + }
  966 +
  967 + printf("setup env for recovery..\n");
  968 + setenv("bootcmd", "run bootcmd_android_recovery");
  969 +}
  970 +#endif /*CONFIG_ANDROID_RECOVERY*/
  971 +
  972 +#endif /*CONFIG_FSL_FASTBOOT*/
  973 +
  974 +#ifdef CONFIG_SPL_BUILD
  975 +#include <libfdt.h>
  976 +#include <spl.h>
  977 +#include <asm/arch/mx6-ddr.h>
  978 +
  979 +
  980 +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  981 + .grp_addds = 0x00000030,
  982 + .grp_ddrmode_ctl = 0x00020000,
  983 + .grp_b0ds = 0x00000030,
  984 + .grp_ctlds = 0x00000030,
  985 + .grp_b1ds = 0x00000030,
  986 + .grp_ddrpke = 0x00000000,
  987 + .grp_ddrmode = 0x00020000,
  988 +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  989 + .grp_ddr_type = 0x00080000,
  990 +#else
  991 + .grp_ddr_type = 0x000c0000,
  992 +#endif
  993 +};
  994 +
  995 +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  996 +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  997 + .dram_dqm0 = 0x00000030,
  998 + .dram_dqm1 = 0x00000030,
  999 + .dram_ras = 0x00000030,
  1000 + .dram_cas = 0x00000030,
  1001 + .dram_odt0 = 0x00000000,
  1002 + .dram_odt1 = 0x00000000,
  1003 + .dram_sdba2 = 0x00000000,
  1004 + .dram_sdclk_0 = 0x00000030,
  1005 + .dram_sdqs0 = 0x00003030,
  1006 + .dram_sdqs1 = 0x00003030,
  1007 + .dram_reset = 0x00000030,
  1008 +};
  1009 +
  1010 +static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  1011 + .p0_mpwldectrl0 = 0x00000000,
  1012 + .p0_mpdgctrl0 = 0x20000000,
  1013 + .p0_mprddlctl = 0x4040484f,
  1014 + .p0_mpwrdlctl = 0x40405247,
  1015 + .mpzqlp2ctl = 0x1b4700c7,
  1016 +};
  1017 +
  1018 +static struct mx6_lpddr2_cfg mem_ddr = {
  1019 + .mem_speed = 800,
  1020 + .density = 2,
  1021 + .width = 16,
  1022 + .banks = 4,
  1023 + .rowaddr = 14,
  1024 + .coladdr = 10,
  1025 + .trcd_lp = 1500,
  1026 + .trppb_lp = 1500,
  1027 + .trpab_lp = 2000,
  1028 + .trasmin = 4250,
  1029 +};
  1030 +
  1031 +struct mx6_ddr_sysinfo ddr_sysinfo = {
  1032 + .dsize = 0,
  1033 + .cs_density = 18,
  1034 + .ncs = 1,
  1035 + .cs1_mirror = 0,
  1036 + .walat = 0,
  1037 + .ralat = 5,
  1038 + .mif3_mode = 3,
  1039 + .bi_on = 1,
  1040 + .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
  1041 + .rtt_nom = 0,
  1042 + .sde_to_rst = 0, /* LPDDR2 does not need this field */
  1043 + .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
  1044 + .ddr_type = DDR_TYPE_LPDDR2,
  1045 +};
  1046 +
  1047 +#else
  1048 +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  1049 + .dram_dqm0 = 0x00000030,
  1050 + .dram_dqm1 = 0x00000030,
  1051 + .dram_ras = 0x00000030,
  1052 + .dram_cas = 0x00000030,
  1053 + .dram_odt0 = 0x00000030,
  1054 + .dram_odt1 = 0x00000030,
  1055 + .dram_sdba2 = 0x00000000,
  1056 + .dram_sdclk_0 = 0x00000008,
  1057 + .dram_sdqs0 = 0x00000038,
  1058 + .dram_sdqs1 = 0x00000030,
  1059 + .dram_reset = 0x00000030,
  1060 +};
  1061 +
  1062 +static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  1063 + .p0_mpwldectrl0 = 0x00070007,
  1064 + .p0_mpdgctrl0 = 0x41490145,
  1065 + .p0_mprddlctl = 0x40404546,
  1066 + .p0_mpwrdlctl = 0x4040524D,
  1067 +};
  1068 +
  1069 +struct mx6_ddr_sysinfo ddr_sysinfo = {
  1070 + .dsize = 0,
  1071 + .cs_density = 20,
  1072 + .ncs = 1,
  1073 + .cs1_mirror = 0,
  1074 + .rtt_wr = 2,
  1075 + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  1076 + .walat = 1, /* Write additional latency */
  1077 + .ralat = 5, /* Read additional latency */
  1078 + .mif3_mode = 3, /* Command prediction working mode */
  1079 + .bi_on = 1, /* Bank interleaving enabled */
  1080 + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  1081 + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  1082 + .ddr_type = DDR_TYPE_DDR3,
  1083 +};
  1084 +
  1085 +static struct mx6_ddr3_cfg mem_ddr = {
  1086 + .mem_speed = 800,
  1087 + .density = 4,
  1088 + .width = 16,
  1089 + .banks = 8,
  1090 + .rowaddr = 15,
  1091 + .coladdr = 10,
  1092 + .pagesz = 2,
  1093 + .trcd = 1375,
  1094 + .trcmin = 4875,
  1095 + .trasmin = 3500,
  1096 +};
  1097 +#endif
  1098 +
  1099 +static void ccgr_init(void)
  1100 +{
  1101 + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1102 +
  1103 + writel(0xFFFFFFFF, &ccm->CCGR0);
  1104 + writel(0xFFFFFFFF, &ccm->CCGR1);
  1105 + writel(0xFFFFFFFF, &ccm->CCGR2);
  1106 + writel(0xFFFFFFFF, &ccm->CCGR3);
  1107 + writel(0xFFFFFFFF, &ccm->CCGR4);
  1108 + writel(0xFFFFFFFF, &ccm->CCGR5);
  1109 + writel(0xFFFFFFFF, &ccm->CCGR6);
  1110 + writel(0xFFFFFFFF, &ccm->CCGR7);
  1111 +}
  1112 +
  1113 +static void spl_dram_init(void)
  1114 +{
  1115 + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  1116 + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  1117 +}
  1118 +
  1119 +void board_init_f(ulong dummy)
  1120 +{
  1121 + /* setup AIPS and disable watchdog */
  1122 + arch_cpu_init();
  1123 +
  1124 + ccgr_init();
  1125 +
  1126 + /* iomux and setup of i2c */
  1127 + board_early_init_f();
  1128 +
  1129 + /* setup GP timer */
  1130 + timer_init();
  1131 +
  1132 + /* UART clocks enabled and gd valid - init serial console */
  1133 + preloader_console_init();
  1134 +
  1135 + /* DDR initialization */
  1136 + spl_dram_init();
  1137 +
  1138 + /* Clear the BSS. */
  1139 + memset(__bss_start, 0, __bss_end - __bss_start);
  1140 +
  1141 + /* load/boot image from boot device */
  1142 + board_init_r(NULL, 0);
  1143 +}
  1144 +#endif
board/freescale/mx6ullevk/plugin.S
Diff comments   View file @ 56cb080
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6ull_ddr3_evk_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000C0000
  13 + str r1, [r0, #0x4B4]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x4AC]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x27C]
  18 + ldr r1, =0x00000030
  19 + str r1, [r0, #0x250]
  20 + str r1, [r0, #0x24C]
  21 + str r1, [r0, #0x490]
  22 + ldr r1, =0x000C0030
  23 + str r1, [r0, #0x288]
  24 +
  25 + ldr r1, =0x00000000
  26 + str r1, [r0, #0x270]
  27 +
  28 + ldr r1, =0x00000030
  29 + str r1, [r0, #0x260]
  30 + str r1, [r0, #0x264]
  31 + str r1, [r0, #0x4A0]
  32 +
  33 + ldr r1, =0x00020000
  34 + str r1, [r0, #0x494]
  35 +
  36 + ldr r1, =0x00000030
  37 + str r1, [r0, #0x280]
  38 + ldr r1, =0x00000030
  39 + str r1, [r0, #0x284]
  40 +
  41 + ldr r1, =0x00020000
  42 + str r1, [r0, #0x4B0]
  43 +
  44 + ldr r1, =0x00000030
  45 + str r1, [r0, #0x498]
  46 + str r1, [r0, #0x4A4]
  47 + str r1, [r0, #0x244]
  48 + str r1, [r0, #0x248]
  49 +
  50 + ldr r0, =MMDC_P0_BASE_ADDR
  51 + ldr r1, =0x00008000
  52 + str r1, [r0, #0x1C]
  53 + ldr r1, =0xA1390003
  54 + str r1, [r0, #0x800]
  55 + ldr r1, =0x00000004
  56 + str r1, [r0, #0x80C]
  57 + ldr r1, =0x41640158
  58 + str r1, [r0, #0x83C]
  59 + ldr r1, =0x40403237
  60 + str r1, [r0, #0x848]
  61 + ldr r1, =0x40403C33
  62 + str r1, [r0, #0x850]
  63 + ldr r1, =0x33333333
  64 + str r1, [r0, #0x81C]
  65 + str r1, [r0, #0x820]
  66 + ldr r1, =0xF3333333
  67 + str r1, [r0, #0x82C]
  68 + str r1, [r0, #0x830]
  69 + ldr r1, =0x00944009
  70 + str r1, [r0, #0x8C0]
  71 + ldr r1, =0x00000800
  72 + str r1, [r0, #0x8B8]
  73 + ldr r1, =0x0002002D
  74 + str r1, [r0, #0x004]
  75 + ldr r1, =0x1B333030
  76 + str r1, [r0, #0x008]
  77 + ldr r1, =0x676B52F3
  78 + str r1, [r0, #0x00C]
  79 + ldr r1, =0xB66D0B63
  80 + str r1, [r0, #0x010]
  81 + ldr r1, =0x01FF00DB
  82 + str r1, [r0, #0x014]
  83 + ldr r1, =0x00201740
  84 + str r1, [r0, #0x018]
  85 + ldr r1, =0x00008000
  86 + str r1, [r0, #0x01C]
  87 + ldr r1, =0x000026D2
  88 + str r1, [r0, #0x02C]
  89 + ldr r1, =0x006B1023
  90 + str r1, [r0, #0x030]
  91 + ldr r1, =0x0000004F
  92 + str r1, [r0, #0x040]
  93 + ldr r1, =0x84180000
  94 + str r1, [r0, #0x000]
  95 + ldr r1, =0x00400000
  96 + str r1, [r0, #0x890]
  97 + ldr r1, =0x02008032
  98 + str r1, [r0, #0x01C]
  99 + ldr r1, =0x00008033
  100 + str r1, [r0, #0x01C]
  101 + ldr r1, =0x00048031
  102 + str r1, [r0, #0x01C]
  103 + ldr r1, =0x15208030
  104 + str r1, [r0, #0x01C]
  105 + ldr r1, =0x04008040
  106 + str r1, [r0, #0x01C]
  107 + ldr r1, =0x00000800
  108 + str r1, [r0, #0x020]
  109 + ldr r1, =0x00000227
  110 + str r1, [r0, #0x818]
  111 + ldr r1, =0x0002552D
  112 + str r1, [r0, #0x004]
  113 + ldr r1, =0x00011006
  114 + str r1, [r0, #0x404]
  115 + ldr r1, =0x00000000
  116 + str r1, [r0, #0x01C]
  117 +.endm
  118 +
  119 +.macro imx6ull_lpddr2_evk_setting
  120 + ldr r0, =IOMUXC_BASE_ADDR
  121 + ldr r1, =0x00080000
  122 + str r1, [r0, #0x4B4]
  123 + ldr r1, =0x00000000
  124 + str r1, [r0, #0x4AC]
  125 + ldr r1, =0x00000030
  126 + str r1, [r0, #0x27C]
  127 + str r1, [r0, #0x250]
  128 + str r1, [r0, #0x24C]
  129 + str r1, [r0, #0x490]
  130 + str r1, [r0, #0x288]
  131 +
  132 + ldr r1, =0x00000000
  133 + str r1, [r0, #0x270]
  134 + str r1, [r0, #0x260]
  135 + str r1, [r0, #0x264]
  136 +
  137 + ldr r1, =0x00000030
  138 + str r1, [r0, #0x4A0]
  139 +
  140 + ldr r1, =0x00020000
  141 + str r1, [r0, #0x494]
  142 +
  143 + ldr r1, =0x00003030
  144 + str r1, [r0, #0x280]
  145 + ldr r1, =0x00003030
  146 + str r1, [r0, #0x284]
  147 +
  148 + ldr r1, =0x00020000
  149 + str r1, [r0, #0x4B0]
  150 +
  151 + ldr r1, =0x00000030
  152 + str r1, [r0, #0x498]
  153 + str r1, [r0, #0x4A4]
  154 + str r1, [r0, #0x244]
  155 + str r1, [r0, #0x248]
  156 +
  157 + ldr r0, =MMDC_P0_BASE_ADDR
  158 + ldr r1, =0x00008000
  159 + str r1, [r0, #0x1C]
  160 + ldr r1, =0x1b4700c7
  161 + str r1, [r0, #0x85c]
  162 + ldr r1, =0xA1390003
  163 + str r1, [r0, #0x800]
  164 + ldr r1, =0x00470000
  165 + str r1, [r0, #0x890]
  166 + ldr r1, =0x00000800
  167 + str r1, [r0, #0x8b8]
  168 + ldr r1, =0x33333333
  169 + str r1, [r0, #0x81C]
  170 + str r1, [r0, #0x820]
  171 + ldr r1, =0xF3333333
  172 + str r1, [r0, #0x82C]
  173 + str r1, [r0, #0x830]
  174 + ldr r1, =0x20000000
  175 + str r1, [r0, #0x83C]
  176 + ldr r1, =0x4040484F
  177 + str r1, [r0, #0x848]
  178 + ldr r1, =0x40405247
  179 + str r1, [r0, #0x850]
  180 + ldr r1, =0x00922012
  181 + str r1, [r0, #0x8C0]
  182 + ldr r1, =0x00000800
  183 + str r1, [r0, #0x8B8]
  184 +
  185 + ldr r1, =0x00020012
  186 + str r1, [r0, #0x004]
  187 + ldr r1, =0x00000000
  188 + str r1, [r0, #0x008]
  189 + ldr r1, =0x33374133
  190 + str r1, [r0, #0x00C]
  191 + ldr r1, =0x00100A82
  192 + str r1, [r0, #0x010]
  193 + ldr r1, =0x00170557
  194 + str r1, [r0, #0x038]
  195 + ldr r1, =0x00000093
  196 + str r1, [r0, #0x014]
  197 + ldr r1, =0x00001748
  198 + str r1, [r0, #0x018]
  199 + ldr r1, =0x00008000
  200 + str r1, [r0, #0x01C]
  201 + ldr r1, =0x0F9F0682
  202 + str r1, [r0, #0x02C]
  203 + ldr r1, =0x009F0010
  204 + str r1, [r0, #0x030]
  205 + ldr r1, =0x00000047
  206 + str r1, [r0, #0x040]
  207 + ldr r1, =0x83100000
  208 + str r1, [r0, #0x000]
  209 + ldr r1, =0x003F8030
  210 + str r1, [r0, #0x01C]
  211 + ldr r1, =0xFF0A8030
  212 + str r1, [r0, #0x01C]
  213 + ldr r1, =0x82018030
  214 + str r1, [r0, #0x01C]
  215 + ldr r1, =0x04028030
  216 + str r1, [r0, #0x01C]
  217 + ldr r1, =0x01038030
  218 + str r1, [r0, #0x01C]
  219 + ldr r1, =0x00001800
  220 + str r1, [r0, #0x020]
  221 + ldr r1, =0x00000000
  222 + str r1, [r0, #0x818]
  223 + ldr r1, =0xA1310003
  224 + str r1, [r0, #0x800]
  225 + ldr r1, =0x00025576
  226 + str r1, [r0, #0x004]
  227 + ldr r1, =0x00010106
  228 + str r1, [r0, #0x404]
  229 + ldr r1, =0x00000000
  230 + str r1, [r0, #0x01C]
  231 +.endm
  232 +
  233 +.macro imx6_clock_gating
  234 + ldr r0, =CCM_BASE_ADDR
  235 + ldr r1, =0xFFFFFFFF
  236 + str r1, [r0, #0x68]
  237 + str r1, [r0, #0x6C]
  238 + str r1, [r0, #0x70]
  239 + str r1, [r0, #0x74]
  240 + str r1, [r0, #0x78]
  241 + str r1, [r0, #0x7C]
  242 + str r1, [r0, #0x80]
  243 +.endm
  244 +
  245 +.macro imx6_qos_setting
  246 +.endm
  247 +
  248 +.macro imx6_ddr_setting
  249 +#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK)
  250 + imx6ull_lpddr2_evk_setting
  251 +#else
  252 + imx6ull_ddr3_evk_setting
  253 +#endif
  254 +.endm
  255 +
  256 +/* include the common plugin code here */
  257 +#include <asm/arch/mx6_plugin.S>
configs/mx6ull_14x14_evk_defconfig
Diff comments   View file @ 56cb080
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_14X14_EVK=y
  5 +CONFIG_CMD_GPIO=y
include/configs/mx6ullevk.h
Diff comments   View file @ 56cb080
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +#ifndef __MX6ULLEVK_CONFIG_H
  9 +#define __MX6ULLEVK_CONFIG_H
  10 +
  11 +
  12 +#include <asm/arch/imx-regs.h>
  13 +#include <linux/sizes.h>
  14 +#include "mx6_common.h"
  15 +#include <asm/imx-common/gpio.h>
  16 +
  17 +/* uncomment for PLUGIN mode support */
  18 +/* #define CONFIG_USE_PLUGIN */
  19 +
  20 +/* uncomment for SECURE mode support */
  21 +/* #define CONFIG_SECURE_BOOT */
  22 +
  23 +#ifdef CONFIG_SECURE_BOOT
  24 +#ifndef CONFIG_CSF_SIZE
  25 +#define CONFIG_CSF_SIZE 0x4000
  26 +#endif
  27 +#endif
  28 +
  29 +#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK)
  30 +
  31 +#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK
  32 +#define PHYS_SDRAM_SIZE SZ_256M
  33 +#define CONFIG_BOOTARGS_CMA_SIZE "cma=96M "
  34 +#else
  35 +#define PHYS_SDRAM_SIZE SZ_512M
  36 +#define CONFIG_BOOTARGS_CMA_SIZE ""
  37 +/* DCDC used on 14x14 EVK, no PMIC */
  38 +#undef CONFIG_LDO_BYPASS_CHECK
  39 +#endif
  40 +
  41 +/* SPL options */
  42 +/* We default not support SPL
  43 + * #define CONFIG_SPL_LIBCOMMON_SUPPORT
  44 + * #define CONFIG_SPL_MMC_SUPPORT
  45 + * #include "imx6_spl.h"
  46 +*/
  47 +
  48 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  49 +
  50 +#define CONFIG_DISPLAY_CPUINFO
  51 +#define CONFIG_DISPLAY_BOARDINFO
  52 +
  53 +/* Size of malloc() pool */
  54 +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
  55 +
  56 +#define CONFIG_BOARD_EARLY_INIT_F
  57 +#define CONFIG_BOARD_LATE_INIT
  58 +
  59 +#define CONFIG_MXC_UART
  60 +#define CONFIG_MXC_UART_BASE UART1_BASE
  61 +
  62 +/* MMC Configs */
  63 +#ifdef CONFIG_FSL_USDHC
  64 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
  65 +
  66 +/* NAND pin conflicts with usdhc2 */
  67 +#ifdef CONFIG_SYS_USE_NAND
  68 +#define CONFIG_SYS_FSL_USDHC_NUM 1
  69 +#else
  70 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  71 +#endif
  72 +#endif
  73 +
  74 +/* I2C configs */
  75 +#define CONFIG_CMD_I2C
  76 +#ifdef CONFIG_CMD_I2C
  77 +#define CONFIG_SYS_I2C
  78 +#define CONFIG_SYS_I2C_MXC
  79 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  80 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  81 +#define CONFIG_SYS_I2C_SPEED 100000
  82 +
  83 +/* PMIC only for 9X9 EVK */
  84 +#define CONFIG_POWER
  85 +#define CONFIG_POWER_I2C
  86 +#define CONFIG_POWER_PFUZE3000
  87 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
  88 +#endif
  89 +
  90 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  91 +
  92 +#ifdef CONFIG_SYS_BOOT_NAND
  93 +#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
  94 +#else
  95 +#define CONFIG_MFG_NAND_PARTITION ""
  96 +#endif
  97 +
  98 +#define CONFIG_MFG_ENV_SETTINGS \
  99 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  100 + CONFIG_BOOTARGS_CMA_SIZE \
  101 + "rdinit=/linuxrc " \
  102 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  103 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  104 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  105 + "g_mass_storage.iSerialNumber=\"\" "\
  106 + CONFIG_MFG_NAND_PARTITION \
  107 + "clk_ignore_unused "\
  108 + "\0" \
  109 + "initrd_addr=0x83800000\0" \
  110 + "initrd_high=0xffffffff\0" \
  111 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  112 +
  113 +#if defined(CONFIG_SYS_BOOT_NAND)
  114 +#define CONFIG_EXTRA_ENV_SETTINGS \
  115 + CONFIG_MFG_ENV_SETTINGS \
  116 + "panel=TFT43AB\0" \
  117 + "fdt_addr=0x83000000\0" \
  118 + "fdt_high=0xffffffff\0" \
  119 + "console=ttymxc0\0" \
  120 + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \
  121 + "root=ubi0:rootfs rootfstype=ubifs " \
  122 + CONFIG_BOOTARGS_CMA_SIZE \
  123 + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
  124 + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
  125 + "nand read ${fdt_addr} 0x5000000 0x100000;"\
  126 + "bootz ${loadaddr} - ${fdt_addr}\0"
  127 +
  128 +#else
  129 +#define CONFIG_EXTRA_ENV_SETTINGS \
  130 + CONFIG_MFG_ENV_SETTINGS \
  131 + "script=boot.scr\0" \
  132 + "image=zImage\0" \
  133 + "console=ttymxc0\0" \
  134 + "fdt_high=0xffffffff\0" \
  135 + "initrd_high=0xffffffff\0" \
  136 + "fdt_file=undefined\0" \
  137 + "fdt_addr=0x83000000\0" \
  138 + "boot_fdt=try\0" \
  139 + "ip_dyn=yes\0" \
  140 + "panel=TFT43AB\0" \
  141 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  142 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  143 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  144 + "mmcautodetect=yes\0" \
  145 + "mmcargs=setenv bootargs console=${console},${baudrate} " \
  146 + CONFIG_BOOTARGS_CMA_SIZE \
  147 + "root=${mmcroot}\0" \
  148 + "loadbootscript=" \
  149 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  150 + "bootscript=echo Running bootscript from mmc ...; " \
  151 + "source\0" \
  152 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  153 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  154 + "mmcboot=echo Booting from mmc ...; " \
  155 + "run mmcargs; " \
  156 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  157 + "if run loadfdt; then " \
  158 + "bootz ${loadaddr} - ${fdt_addr}; " \
  159 + "else " \
  160 + "if test ${boot_fdt} = try; then " \
  161 + "bootz; " \
  162 + "else " \
  163 + "echo WARN: Cannot load the DT; " \
  164 + "fi; " \
  165 + "fi; " \
  166 + "else " \
  167 + "bootz; " \
  168 + "fi;\0" \
  169 + "netargs=setenv bootargs console=${console},${baudrate} " \
  170 + CONFIG_BOOTARGS_CMA_SIZE \
  171 + "root=/dev/nfs " \
  172 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  173 + "netboot=echo Booting from net ...; " \
  174 + "run netargs; " \
  175 + "if test ${ip_dyn} = yes; then " \
  176 + "setenv get_cmd dhcp; " \
  177 + "else " \
  178 + "setenv get_cmd tftp; " \
  179 + "fi; " \
  180 + "${get_cmd} ${image}; " \
  181 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  182 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  183 + "bootz ${loadaddr} - ${fdt_addr}; " \
  184 + "else " \
  185 + "if test ${boot_fdt} = try; then " \
  186 + "bootz; " \
  187 + "else " \
  188 + "echo WARN: Cannot load the DT; " \
  189 + "fi; " \
  190 + "fi; " \
  191 + "else " \
  192 + "bootz; " \
  193 + "fi;\0" \
  194 + "findfdt="\
  195 + "if test $fdt_file = undefined; then " \
  196 + "if test $board_name = EVK && test $board_rev = 9X9; then " \
  197 + "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \
  198 + "if test $board_name = EVK && test $board_rev = 14X14; then " \
  199 + "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
  200 + "if test $fdt_file = undefined; then " \
  201 + "echo WARNING: Could not determine dtb to use; fi; " \
  202 + "fi;\0" \
  203 +
  204 +#define CONFIG_BOOTCOMMAND \
  205 + "run findfdt;" \
  206 + "mmc dev ${mmcdev};" \
  207 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  208 + "if run loadbootscript; then " \
  209 + "run bootscript; " \
  210 + "else " \
  211 + "if run loadimage; then " \
  212 + "run mmcboot; " \
  213 + "else run netboot; " \
  214 + "fi; " \
  215 + "fi; " \
  216 + "else run netboot; fi"
  217 +#endif
  218 +
  219 +/* Miscellaneous configurable options */
  220 +#define CONFIG_CMD_MEMTEST
  221 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  222 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
  223 +
  224 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  225 +#define CONFIG_SYS_HZ 1000
  226 +
  227 +#define CONFIG_STACKSIZE SZ_128K
  228 +
  229 +/* Physical Memory Map */
  230 +#define CONFIG_NR_DRAM_BANKS 1
  231 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  232 +
  233 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  234 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  235 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  236 +
  237 +#define CONFIG_SYS_INIT_SP_OFFSET \
  238 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  239 +#define CONFIG_SYS_INIT_SP_ADDR \
  240 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  241 +
  242 +/* FLASH and environment organization */
  243 +#define CONFIG_SYS_NO_FLASH
  244 +
  245 +#ifdef CONFIG_SYS_BOOT_QSPI
  246 +#define CONFIG_FSL_QSPI
  247 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  248 +#elif defined CONFIG_SYS_BOOT_NAND
  249 +#define CONFIG_SYS_USE_NAND
  250 +#define CONFIG_ENV_IS_IN_NAND
  251 +#else
  252 +#define CONFIG_FSL_QSPI
  253 +#define CONFIG_ENV_IS_IN_MMC
  254 +#endif
  255 +
  256 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  257 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  258 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  259 +
  260 +#define CONFIG_CMD_BMODE
  261 +
  262 +#ifdef CONFIG_FSL_QSPI
  263 +#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR
  264 +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE
  265 +
  266 +#define CONFIG_CMD_SF
  267 +#define CONFIG_SPI_FLASH
  268 +#define CONFIG_SPI_FLASH_BAR
  269 +#define CONFIG_SF_DEFAULT_BUS 0
  270 +#define CONFIG_SF_DEFAULT_CS 0
  271 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  272 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  273 +#define CONFIG_SPI_FLASH_STMICRO
  274 +#endif
  275 +
  276 +/* NAND stuff */
  277 +#ifdef CONFIG_SYS_USE_NAND
  278 +#define CONFIG_CMD_NAND
  279 +#define CONFIG_CMD_NAND_TRIMFFS
  280 +
  281 +#define CONFIG_NAND_MXS
  282 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  283 +#define CONFIG_SYS_NAND_BASE 0x40000000
  284 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  285 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  286 +
  287 +/* DMA stuff, needed for GPMI/MXS NAND support */
  288 +#define CONFIG_APBH_DMA
  289 +#define CONFIG_APBH_DMA_BURST
  290 +#define CONFIG_APBH_DMA_BURST8
  291 +#endif
  292 +
  293 +#define CONFIG_ENV_SIZE SZ_8K
  294 +#if defined(CONFIG_ENV_IS_IN_MMC)
  295 +#define CONFIG_ENV_OFFSET (12 * SZ_64K)
  296 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  297 +#define CONFIG_ENV_OFFSET (768 * 1024)
  298 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  299 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  300 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  301 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  302 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  303 +#elif defined(CONFIG_ENV_IS_IN_NAND)
  304 +#undef CONFIG_ENV_SIZE
  305 +#define CONFIG_ENV_OFFSET (60 << 20)
  306 +#define CONFIG_ENV_SECT_SIZE (128 << 10)
  307 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  308 +#endif
  309 +
  310 +
  311 +/* USB Configs */
  312 +#define CONFIG_CMD_USB
  313 +#ifdef CONFIG_CMD_USB
  314 +#define CONFIG_USB_EHCI
  315 +#define CONFIG_USB_EHCI_MX6
  316 +#define CONFIG_USB_STORAGE
  317 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  318 +#define CONFIG_USB_HOST_ETHER
  319 +#define CONFIG_USB_ETHER_ASIX
  320 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  321 +#define CONFIG_MXC_USB_FLAGS 0
  322 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  323 +#endif
  324 +
  325 +#ifdef CONFIG_CMD_NET
  326 +#define CONFIG_CMD_PING
  327 +#define CONFIG_CMD_DHCP
  328 +#define CONFIG_CMD_MII
  329 +#define CONFIG_FEC_MXC
  330 +#define CONFIG_MII
  331 +#define CONFIG_FEC_ENET_DEV 1
  332 +
  333 +#if (CONFIG_FEC_ENET_DEV == 0)
  334 +#define IMX_FEC_BASE ENET_BASE_ADDR
  335 +#define CONFIG_FEC_MXC_PHYADDR 0x2
  336 +#define CONFIG_FEC_XCV_TYPE RMII
  337 +#elif (CONFIG_FEC_ENET_DEV == 1)
  338 +#define IMX_FEC_BASE ENET2_BASE_ADDR
  339 +#define CONFIG_FEC_MXC_PHYADDR 0x1
  340 +#define CONFIG_FEC_XCV_TYPE RMII
  341 +#endif
  342 +#define CONFIG_ETHPRIME "FEC"
  343 +
  344 +#define CONFIG_PHYLIB
  345 +#define CONFIG_PHY_MICREL
  346 +#endif
  347 +
  348 +#define CONFIG_IMX_THERMAL
  349 +
  350 +#ifndef CONFIG_SPL_BUILD
  351 +#define CONFIG_VIDEO
  352 +#ifdef CONFIG_VIDEO
  353 +#define CONFIG_CFB_CONSOLE
  354 +#define CONFIG_VIDEO_MXS
  355 +#define CONFIG_VIDEO_LOGO
  356 +#define CONFIG_VIDEO_SW_CURSOR
  357 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  358 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  359 +#define CONFIG_SPLASH_SCREEN
  360 +#define CONFIG_SPLASH_SCREEN_ALIGN
  361 +#define CONFIG_CMD_BMP
  362 +#define CONFIG_BMP_16BPP
  363 +#define CONFIG_VIDEO_BMP_RLE8
  364 +#define CONFIG_VIDEO_BMP_LOGO
  365 +#define CONFIG_IMX_VIDEO_SKIP
  366 +#endif
  367 +#endif
  368 +
  369 +#define CONFIG_IOMUX_LPSR
  370 +
  371 +#if defined(CONFIG_ANDROID_SUPPORT)
  372 +#include "mx6ullevk_android.h"
  373 +#endif
  374 +
  375 +#endif