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Commit 56f86e39e80c5cbb17bec42cf6931cd203176830

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 601fbec7cf
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: kirkwood: move SOC sources to mach-kirkwood 

Move
arch/arm/cpu/arm926ejs/kirkwood/* -> arch/arm/mach-kirkwood/*

Note:
 Perhaps, can we merge arch/arm/mach-kirkwood and
 arch/arm/mvebu-common into arch/arm/mach-mvebu, like Linux?

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Showing 14 changed files with 533 additions and 532 deletions Side-by-side Diff

... ... @@ -99,7 +99,7 @@
99 99 M: Luka Perkov <luka.perkov@sartura.hr>
100 100 S: Maintained
101 101 T: git git://git.denx.de/u-boot-marvell.git
102   -F: arch/arm/cpu/arm926ejs/kirkwood/
  102 +F: arch/arm/mach-kirkwood/
103 103 F: arch/arm/include/asm/arch-kirkwood/
104 104  
105 105 ARM MARVELL PXA
... ... @@ -726,7 +726,7 @@
726 726  
727 727 source "arch/arm/cpu/armv7/keystone/Kconfig"
728 728  
729   -source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
  729 +source "arch/arm/mach-kirkwood/Kconfig"
730 730  
731 731 source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
732 732  
... ... @@ -6,6 +6,8 @@
6 6 # by CONFIG_* macro name.
7 7 machine-$(CONFIG_ARCH_AT91) += at91
8 8 machine-$(CONFIG_ARCH_DAVINCI) += davinci
  9 +# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
  10 +machine-$(CONFIG_KIRKWOOD) += kirkwood
9 11 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
10 12 machine-$(CONFIG_TEGRA) += tegra
11 13  
arch/arm/cpu/arm926ejs/Makefile
Diff comments   View file @ 56f86e3
... ... @@ -15,7 +15,6 @@
15 15 endif
16 16  
17 17 obj-$(CONFIG_ARMADA100) += armada100/
18   -obj-$(CONFIG_KIRKWOOD) += kirkwood/
19 18 obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
20 19 obj-$(CONFIG_MB86R0x) += mb86r0x/
21 20 obj-$(CONFIG_MX25) += mx25/
arch/arm/cpu/arm926ejs/kirkwood/Kconfig
View file @ 56f86e3
1   -if KIRKWOOD
2   -
3   -choice
4   - prompt "Marvell Kirkwood board select"
5   -
6   -config TARGET_OPENRD
7   - bool "Marvell OpenRD Board"
8   -
9   -config TARGET_MV88F6281GTW_GE
10   - bool "MV88f6281GTW_GE Board"
11   -
12   -config TARGET_RD6281A
13   - bool "RD6281A Board"
14   -
15   -config TARGET_DREAMPLUG
16   - bool "DreamPlug Board"
17   -
18   -config TARGET_GURUPLUG
19   - bool "GuruPlug Board"
20   -
21   -config TARGET_SHEEVAPLUG
22   - bool "SheevaPlug Board"
23   -
24   -config TARGET_LSXL
25   - bool "lsxl Board"
26   -
27   -config TARGET_POGO_E02
28   - bool "pogo_e02 Board"
29   -
30   -config TARGET_DNS325
31   - bool "dns325 Board"
32   -
33   -config TARGET_ICONNECT
34   - bool "iconnect Board"
35   -
36   -config TARGET_TK71
37   - bool "TK71 Board"
38   -
39   -config TARGET_KM_KIRKWOOD
40   - bool "KM_KIRKWOOD Board"
41   -
42   -config TARGET_NET2BIG_V2
43   - bool "LaCie 2Big Network v2 NAS Board"
44   -
45   -config TARGET_NETSPACE_V2
46   - bool "LaCie netspace_v2 Board"
47   -
48   -config TARGET_WIRELESS_SPACE
49   - bool "LaCie Wireless_space Board"
50   -
51   -config TARGET_IB62X0
52   - bool "ib62x0 Board"
53   -
54   -config TARGET_DOCKSTAR
55   - bool "Dockstar Board"
56   -
57   -config TARGET_GOFLEXHOME
58   - bool "GoFlex Home Board"
59   -
60   -config TARGET_NAS220
61   - bool "BlackArmor NAS220"
62   -
63   -endchoice
64   -
65   -config SYS_SOC
66   - default "kirkwood"
67   -
68   -source "board/Marvell/openrd/Kconfig"
69   -source "board/Marvell/mv88f6281gtw_ge/Kconfig"
70   -source "board/Marvell/rd6281a/Kconfig"
71   -source "board/Marvell/dreamplug/Kconfig"
72   -source "board/Marvell/guruplug/Kconfig"
73   -source "board/Marvell/sheevaplug/Kconfig"
74   -source "board/buffalo/lsxl/Kconfig"
75   -source "board/cloudengines/pogo_e02/Kconfig"
76   -source "board/d-link/dns325/Kconfig"
77   -source "board/iomega/iconnect/Kconfig"
78   -source "board/karo/tk71/Kconfig"
79   -source "board/keymile/km_arm/Kconfig"
80   -source "board/LaCie/net2big_v2/Kconfig"
81   -source "board/LaCie/netspace_v2/Kconfig"
82   -source "board/LaCie/wireless_space/Kconfig"
83   -source "board/raidsonic/ib62x0/Kconfig"
84   -source "board/Seagate/dockstar/Kconfig"
85   -source "board/Seagate/goflexhome/Kconfig"
86   -source "board/Seagate/nas220/Kconfig"
87   -
88   -endif
arch/arm/cpu/arm926ejs/kirkwood/Makefile
View file @ 56f86e3
1   -#
2   -# (C) Copyright 2009
3   -# Marvell Semiconductor <www.marvell.com>
4   -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   -#
6   -# SPDX-License-Identifier: GPL-2.0+
7   -#
8   -
9   -obj-y = cpu.o
10   -obj-y += cache.o
11   -obj-y += mpp.o
arch/arm/cpu/arm926ejs/kirkwood/cache.c
View file @ 56f86e3
1   -/*
2   - * Copyright (c) 2012 Michael Walle
3   - * Michael Walle <michael@walle.cc>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -#include <common.h>
8   -#include <asm/arch/cpu.h>
9   -
10   -#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
11   -
12   -void l2_cache_disable()
13   -{
14   - u32 ctrl;
15   -
16   - ctrl = readfr_extra_feature_reg();
17   - ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
18   - writefr_extra_feature_reg(ctrl);
19   -}
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
View file @ 56f86e3
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <netdev.h>
11   -#include <asm/cache.h>
12   -#include <asm/io.h>
13   -#include <asm/arch/cpu.h>
14   -#include <asm/arch/soc.h>
15   -#include <mvebu_mmc.h>
16   -
17   -void reset_cpu(unsigned long ignored)
18   -{
19   - struct kwcpu_registers *cpureg =
20   - (struct kwcpu_registers *)KW_CPU_REG_BASE;
21   -
22   - writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
23   - &cpureg->rstoutn_mask);
24   - writel(readl(&cpureg->sys_soft_rst) | 1,
25   - &cpureg->sys_soft_rst);
26   - while (1) ;
27   -}
28   -
29   -/*
30   - * Window Size
31   - * Used with the Base register to set the address window size and location.
32   - * Must be programmed from LSB to MSB as sequence of ones followed by
33   - * sequence of zeros. The number of ones specifies the size of the window in
34   - * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
35   - * NOTE: A value of 0x0 specifies 64-KByte size.
36   - */
37   -unsigned int kw_winctrl_calcsize(unsigned int sizeval)
38   -{
39   - int i;
40   - unsigned int j = 0;
41   - u32 val = sizeval >> 1;
42   -
43   - for (i = 0; val >= 0x10000; i++) {
44   - j |= (1 << i);
45   - val = val >> 1;
46   - }
47   - return (0x0000ffff & j);
48   -}
49   -
50   -/*
51   - * kw_config_adr_windows - Configure address Windows
52   - *
53   - * There are 8 address windows supported by Kirkwood Soc to addess different
54   - * devices. Each window can be configured for size, BAR and remap addr
55   - * Below configuration is standard for most of the cases
56   - *
57   - * If remap function not used, remap_lo must be set as base
58   - *
59   - * Reference Documentation:
60   - * Mbus-L to Mbus Bridge Registers Configuration.
61   - * (Sec 25.1 and 25.3 of Datasheet)
62   - */
63   -int kw_config_adr_windows(void)
64   -{
65   - struct kwwin_registers *winregs =
66   - (struct kwwin_registers *)KW_CPU_WIN_BASE;
67   -
68   - /* Window 0: PCIE MEM address space */
69   - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
70   - KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
71   -
72   - writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
73   - writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
74   - writel(0x0, &winregs[0].remap_hi);
75   -
76   - /* Window 1: PCIE IO address space */
77   - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
78   - KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
79   - writel(KW_DEFADR_PCI_IO, &winregs[1].base);
80   - writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
81   - writel(0x0, &winregs[1].remap_hi);
82   -
83   - /* Window 2: NAND Flash address space */
84   - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
85   - KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
86   - writel(KW_DEFADR_NANDF, &winregs[2].base);
87   - writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
88   - writel(0x0, &winregs[2].remap_hi);
89   -
90   - /* Window 3: SPI Flash address space */
91   - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
92   - KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
93   - writel(KW_DEFADR_SPIF, &winregs[3].base);
94   - writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
95   - writel(0x0, &winregs[3].remap_hi);
96   -
97   - /* Window 4: BOOT Memory address space */
98   - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
99   - KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
100   - writel(KW_DEFADR_BOOTROM, &winregs[4].base);
101   -
102   - /* Window 5: Security SRAM address space */
103   - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
104   - KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
105   - writel(KW_DEFADR_SASRAM, &winregs[5].base);
106   -
107   - /* Window 6-7: Disabled */
108   - writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
109   - writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
110   -
111   - return 0;
112   -}
113   -
114   -/*
115   - * SYSRSTn Duration Counter Support
116   - *
117   - * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
118   - * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
119   - * The SYSRSTn duration counter is useful for implementing a manufacturer
120   - * or factory reset. Upon a long reset assertion that is greater than a
121   - * pre-configured environment variable value for sysrstdelay,
122   - * The counter value is stored in the SYSRSTn Length Counter Register
123   - * The counter is based on the 25-MHz reference clock (40ns)
124   - * It is a 29-bit counter, yielding a maximum counting duration of
125   - * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
126   - * it remains at this value until counter reset is triggered by setting
127   - * bit 31 of KW_REG_SYSRST_CNT
128   - */
129   -static void kw_sysrst_action(void)
130   -{
131   - int ret;
132   - char *s = getenv("sysrstcmd");
133   -
134   - if (!s) {
135   - debug("Error.. %s failed, check sysrstcmd\n",
136   - __FUNCTION__);
137   - return;
138   - }
139   -
140   - debug("Starting %s process...\n", __FUNCTION__);
141   - ret = run_command(s, 0);
142   - if (ret != 0)
143   - debug("Error.. %s failed\n", __FUNCTION__);
144   - else
145   - debug("%s process finished\n", __FUNCTION__);
146   -}
147   -
148   -static void kw_sysrst_check(void)
149   -{
150   - u32 sysrst_cnt, sysrst_dly;
151   - char *s;
152   -
153   - /*
154   - * no action if sysrstdelay environment variable is not defined
155   - */
156   - s = getenv("sysrstdelay");
157   - if (s == NULL)
158   - return;
159   -
160   - /* read sysrstdelay value */
161   - sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
162   -
163   - /* read SysRst Length counter register (bits 28:0) */
164   - sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
165   - debug("H/w Rst hold time: %d.%d secs\n",
166   - sysrst_cnt / SYSRST_CNT_1SEC_VAL,
167   - sysrst_cnt % SYSRST_CNT_1SEC_VAL);
168   -
169   - /* clear the counter for next valid read*/
170   - writel(1 << 31, KW_REG_SYSRST_CNT);
171   -
172   - /*
173   - * sysrst_action:
174   - * if H/w Reset key is pressed and hold for time
175   - * more than sysrst_dly in seconds
176   - */
177   - if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
178   - kw_sysrst_action();
179   -}
180   -
181   -#if defined(CONFIG_DISPLAY_CPUINFO)
182   -int print_cpuinfo(void)
183   -{
184   - char *rev = "??";
185   - u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
186   - u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
187   -
188   - if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
189   - printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
190   - return -1;
191   - }
192   -
193   - switch (revid) {
194   - case 0:
195   - if (devid == 0x6281)
196   - rev = "Z0";
197   - else if (devid == 0x6282)
198   - rev = "A0";
199   - break;
200   - case 1:
201   - rev = "A1";
202   - break;
203   - case 2:
204   - rev = "A0";
205   - break;
206   - case 3:
207   - rev = "A1";
208   - break;
209   - default:
210   - break;
211   - }
212   -
213   - printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
214   - return 0;
215   -}
216   -#endif /* CONFIG_DISPLAY_CPUINFO */
217   -
218   -#ifdef CONFIG_ARCH_CPU_INIT
219   -int arch_cpu_init(void)
220   -{
221   - u32 reg;
222   - struct kwcpu_registers *cpureg =
223   - (struct kwcpu_registers *)KW_CPU_REG_BASE;
224   -
225   - /* Linux expects` the internal registers to be at 0xf1000000 */
226   - writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
227   -
228   - /* Enable and invalidate L2 cache in write through mode */
229   - writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
230   - invalidate_l2_cache();
231   -
232   - kw_config_adr_windows();
233   -
234   -#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
235   - /*
236   - * Configures the I/O voltage of the pads connected to Egigabit
237   - * Ethernet interface to 1.8V
238   - * By default it is set to 3.3V
239   - */
240   - reg = readl(KW_REG_MPP_OUT_DRV_REG);
241   - reg |= (1 << 7);
242   - writel(reg, KW_REG_MPP_OUT_DRV_REG);
243   -#endif
244   -#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
245   - /*
246   - * Set egiga port0/1 in normal functional mode
247   - * This is required becasue on kirkwood by default ports are in reset mode
248   - * OS egiga driver may not have provision to set them in normal mode
249   - * and if u-boot is build without network support, network may fail at OS level
250   - */
251   - reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
252   - reg &= ~(1 << 4); /* Clear PortReset Bit */
253   - writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
254   - reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
255   - reg &= ~(1 << 4); /* Clear PortReset Bit */
256   - writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
257   -#endif
258   -#ifdef CONFIG_KIRKWOOD_PCIE_INIT
259   - /*
260   - * Enable PCI Express Port0
261   - */
262   - reg = readl(&cpureg->ctrl_stat);
263   - reg |= (1 << 0); /* Set PEX0En Bit */
264   - writel(reg, &cpureg->ctrl_stat);
265   -#endif
266   - return 0;
267   -}
268   -#endif /* CONFIG_ARCH_CPU_INIT */
269   -
270   -/*
271   - * SOC specific misc init
272   - */
273   -#if defined(CONFIG_ARCH_MISC_INIT)
274   -int arch_misc_init(void)
275   -{
276   - volatile u32 temp;
277   -
278   - /*CPU streaming & write allocate */
279   - temp = readfr_extra_feature_reg();
280   - temp &= ~(1 << 28); /* disable wr alloc */
281   - writefr_extra_feature_reg(temp);
282   -
283   - temp = readfr_extra_feature_reg();
284   - temp &= ~(1 << 29); /* streaming disabled */
285   - writefr_extra_feature_reg(temp);
286   -
287   - /* L2Cache settings */
288   - temp = readfr_extra_feature_reg();
289   - /* Disable L2C pre fetch - Set bit 24 */
290   - temp |= (1 << 24);
291   - /* enable L2C - Set bit 22 */
292   - temp |= (1 << 22);
293   - writefr_extra_feature_reg(temp);
294   -
295   - icache_enable();
296   - /* Change reset vector to address 0x0 */
297   - temp = get_cr();
298   - set_cr(temp & ~CR_V);
299   -
300   - /* checks and execute resset to factory event */
301   - kw_sysrst_check();
302   -
303   - return 0;
304   -}
305   -#endif /* CONFIG_ARCH_MISC_INIT */
306   -
307   -#ifdef CONFIG_MVGBE
308   -int cpu_eth_init(bd_t *bis)
309   -{
310   - mvgbe_initialize(bis);
311   - return 0;
312   -}
313   -#endif
314   -
315   -#ifdef CONFIG_MVEBU_MMC
316   -int board_mmc_init(bd_t *bis)
317   -{
318   - mvebu_mmc_init(bis);
319   - return 0;
320   -}
321   -#endif /* CONFIG_MVEBU_MMC */
arch/arm/cpu/arm926ejs/kirkwood/mpp.c
View file @ 56f86e3
1   -/*
2   - * arch/arm/mach-kirkwood/mpp.c
3   - *
4   - * MPP functions for Marvell Kirkwood SoCs
5   - * Referenced from Linux kernel source
6   - *
7   - * This file is licensed under the terms of the GNU General Public
8   - * License version 2. This program is licensed "as is" without any
9   - * warranty of any kind, whether express or implied.
10   - */
11   -
12   -#include <common.h>
13   -#include <asm/io.h>
14   -#include <asm/arch/cpu.h>
15   -#include <asm/arch/soc.h>
16   -#include <asm/arch/mpp.h>
17   -
18   -static u32 kirkwood_variant(void)
19   -{
20   - switch (readl(KW_REG_DEVICE_ID) & 0x03) {
21   - case 1:
22   - return MPP_F6192_MASK;
23   - case 2:
24   - return MPP_F6281_MASK;
25   - default:
26   - debug("MPP setup: unknown kirkwood variant\n");
27   - return 0;
28   - }
29   -}
30   -
31   -#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
32   -#define MPP_NR_REGS (1 + MPP_MAX/8)
33   -
34   -void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
35   -{
36   - u32 mpp_ctrl[MPP_NR_REGS];
37   - unsigned int variant_mask;
38   - int i;
39   -
40   - variant_mask = kirkwood_variant();
41   - if (!variant_mask)
42   - return;
43   -
44   - debug( "initial MPP regs:");
45   - for (i = 0; i < MPP_NR_REGS; i++) {
46   - mpp_ctrl[i] = readl(MPP_CTRL(i));
47   - debug(" %08x", mpp_ctrl[i]);
48   - }
49   - debug("\n");
50   -
51   -
52   - while (*mpp_list) {
53   - unsigned int num = MPP_NUM(*mpp_list);
54   - unsigned int sel = MPP_SEL(*mpp_list);
55   - unsigned int sel_save;
56   - int shift;
57   -
58   - if (num > MPP_MAX) {
59   - debug("kirkwood_mpp_conf: invalid MPP "
60   - "number (%u)\n", num);
61   - continue;
62   - }
63   - if (!(*mpp_list & variant_mask)) {
64   - debug("kirkwood_mpp_conf: requested MPP%u config "
65   - "unavailable on this hardware\n", num);
66   - continue;
67   - }
68   -
69   - shift = (num & 7) << 2;
70   -
71   - if (mpp_save) {
72   - sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
73   - *mpp_save = num | (sel_save << 8) | variant_mask;
74   - mpp_save++;
75   - }
76   -
77   - mpp_ctrl[num / 8] &= ~(0xf << shift);
78   - mpp_ctrl[num / 8] |= sel << shift;
79   -
80   - mpp_list++;
81   - }
82   -
83   - debug(" final MPP regs:");
84   - for (i = 0; i < MPP_NR_REGS; i++) {
85   - writel(mpp_ctrl[i], MPP_CTRL(i));
86   - debug(" %08x", mpp_ctrl[i]);
87   - }
88   - debug("\n");
89   -
90   -}
arch/arm/mach-kirkwood/Kconfig
Diff comments   View file @ 56f86e3
  1 +if KIRKWOOD
  2 +
  3 +choice
  4 + prompt "Marvell Kirkwood board select"
  5 +
  6 +config TARGET_OPENRD
  7 + bool "Marvell OpenRD Board"
  8 +
  9 +config TARGET_MV88F6281GTW_GE
  10 + bool "MV88f6281GTW_GE Board"
  11 +
  12 +config TARGET_RD6281A
  13 + bool "RD6281A Board"
  14 +
  15 +config TARGET_DREAMPLUG
  16 + bool "DreamPlug Board"
  17 +
  18 +config TARGET_GURUPLUG
  19 + bool "GuruPlug Board"
  20 +
  21 +config TARGET_SHEEVAPLUG
  22 + bool "SheevaPlug Board"
  23 +
  24 +config TARGET_LSXL
  25 + bool "lsxl Board"
  26 +
  27 +config TARGET_POGO_E02
  28 + bool "pogo_e02 Board"
  29 +
  30 +config TARGET_DNS325
  31 + bool "dns325 Board"
  32 +
  33 +config TARGET_ICONNECT
  34 + bool "iconnect Board"
  35 +
  36 +config TARGET_TK71
  37 + bool "TK71 Board"
  38 +
  39 +config TARGET_KM_KIRKWOOD
  40 + bool "KM_KIRKWOOD Board"
  41 +
  42 +config TARGET_NET2BIG_V2
  43 + bool "LaCie 2Big Network v2 NAS Board"
  44 +
  45 +config TARGET_NETSPACE_V2
  46 + bool "LaCie netspace_v2 Board"
  47 +
  48 +config TARGET_WIRELESS_SPACE
  49 + bool "LaCie Wireless_space Board"
  50 +
  51 +config TARGET_IB62X0
  52 + bool "ib62x0 Board"
  53 +
  54 +config TARGET_DOCKSTAR
  55 + bool "Dockstar Board"
  56 +
  57 +config TARGET_GOFLEXHOME
  58 + bool "GoFlex Home Board"
  59 +
  60 +config TARGET_NAS220
  61 + bool "BlackArmor NAS220"
  62 +
  63 +endchoice
  64 +
  65 +config SYS_SOC
  66 + default "kirkwood"
  67 +
  68 +source "board/Marvell/openrd/Kconfig"
  69 +source "board/Marvell/mv88f6281gtw_ge/Kconfig"
  70 +source "board/Marvell/rd6281a/Kconfig"
  71 +source "board/Marvell/dreamplug/Kconfig"
  72 +source "board/Marvell/guruplug/Kconfig"
  73 +source "board/Marvell/sheevaplug/Kconfig"
  74 +source "board/buffalo/lsxl/Kconfig"
  75 +source "board/cloudengines/pogo_e02/Kconfig"
  76 +source "board/d-link/dns325/Kconfig"
  77 +source "board/iomega/iconnect/Kconfig"
  78 +source "board/karo/tk71/Kconfig"
  79 +source "board/keymile/km_arm/Kconfig"
  80 +source "board/LaCie/net2big_v2/Kconfig"
  81 +source "board/LaCie/netspace_v2/Kconfig"
  82 +source "board/LaCie/wireless_space/Kconfig"
  83 +source "board/raidsonic/ib62x0/Kconfig"
  84 +source "board/Seagate/dockstar/Kconfig"
  85 +source "board/Seagate/goflexhome/Kconfig"
  86 +source "board/Seagate/nas220/Kconfig"
  87 +
  88 +endif
arch/arm/mach-kirkwood/Makefile
Diff comments   View file @ 56f86e3
  1 +#
  2 +# (C) Copyright 2009
  3 +# Marvell Semiconductor <www.marvell.com>
  4 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 +#
  6 +# SPDX-License-Identifier: GPL-2.0+
  7 +#
  8 +
  9 +obj-y = cpu.o
  10 +obj-y += cache.o
  11 +obj-y += mpp.o
arch/arm/mach-kirkwood/cache.c
Diff comments   View file @ 56f86e3
  1 +/*
  2 + * Copyright (c) 2012 Michael Walle
  3 + * Michael Walle <michael@walle.cc>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +#include <common.h>
  8 +#include <asm/arch/cpu.h>
  9 +
  10 +#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
  11 +
  12 +void l2_cache_disable()
  13 +{
  14 + u32 ctrl;
  15 +
  16 + ctrl = readfr_extra_feature_reg();
  17 + ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
  18 + writefr_extra_feature_reg(ctrl);
  19 +}
arch/arm/mach-kirkwood/cpu.c
Diff comments   View file @ 56f86e3
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <netdev.h>
  11 +#include <asm/cache.h>
  12 +#include <asm/io.h>
  13 +#include <asm/arch/cpu.h>
  14 +#include <asm/arch/soc.h>
  15 +#include <mvebu_mmc.h>
  16 +
  17 +void reset_cpu(unsigned long ignored)
  18 +{
  19 + struct kwcpu_registers *cpureg =
  20 + (struct kwcpu_registers *)KW_CPU_REG_BASE;
  21 +
  22 + writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  23 + &cpureg->rstoutn_mask);
  24 + writel(readl(&cpureg->sys_soft_rst) | 1,
  25 + &cpureg->sys_soft_rst);
  26 + while (1) ;
  27 +}
  28 +
  29 +/*
  30 + * Window Size
  31 + * Used with the Base register to set the address window size and location.
  32 + * Must be programmed from LSB to MSB as sequence of ones followed by
  33 + * sequence of zeros. The number of ones specifies the size of the window in
  34 + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  35 + * NOTE: A value of 0x0 specifies 64-KByte size.
  36 + */
  37 +unsigned int kw_winctrl_calcsize(unsigned int sizeval)
  38 +{
  39 + int i;
  40 + unsigned int j = 0;
  41 + u32 val = sizeval >> 1;
  42 +
  43 + for (i = 0; val >= 0x10000; i++) {
  44 + j |= (1 << i);
  45 + val = val >> 1;
  46 + }
  47 + return (0x0000ffff & j);
  48 +}
  49 +
  50 +/*
  51 + * kw_config_adr_windows - Configure address Windows
  52 + *
  53 + * There are 8 address windows supported by Kirkwood Soc to addess different
  54 + * devices. Each window can be configured for size, BAR and remap addr
  55 + * Below configuration is standard for most of the cases
  56 + *
  57 + * If remap function not used, remap_lo must be set as base
  58 + *
  59 + * Reference Documentation:
  60 + * Mbus-L to Mbus Bridge Registers Configuration.
  61 + * (Sec 25.1 and 25.3 of Datasheet)
  62 + */
  63 +int kw_config_adr_windows(void)
  64 +{
  65 + struct kwwin_registers *winregs =
  66 + (struct kwwin_registers *)KW_CPU_WIN_BASE;
  67 +
  68 + /* Window 0: PCIE MEM address space */
  69 + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
  70 + KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
  71 +
  72 + writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
  73 + writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
  74 + writel(0x0, &winregs[0].remap_hi);
  75 +
  76 + /* Window 1: PCIE IO address space */
  77 + writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
  78 + KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
  79 + writel(KW_DEFADR_PCI_IO, &winregs[1].base);
  80 + writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
  81 + writel(0x0, &winregs[1].remap_hi);
  82 +
  83 + /* Window 2: NAND Flash address space */
  84 + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
  85 + KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
  86 + writel(KW_DEFADR_NANDF, &winregs[2].base);
  87 + writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
  88 + writel(0x0, &winregs[2].remap_hi);
  89 +
  90 + /* Window 3: SPI Flash address space */
  91 + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
  92 + KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
  93 + writel(KW_DEFADR_SPIF, &winregs[3].base);
  94 + writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
  95 + writel(0x0, &winregs[3].remap_hi);
  96 +
  97 + /* Window 4: BOOT Memory address space */
  98 + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
  99 + KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
  100 + writel(KW_DEFADR_BOOTROM, &winregs[4].base);
  101 +
  102 + /* Window 5: Security SRAM address space */
  103 + writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
  104 + KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
  105 + writel(KW_DEFADR_SASRAM, &winregs[5].base);
  106 +
  107 + /* Window 6-7: Disabled */
  108 + writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
  109 + writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
  110 +
  111 + return 0;
  112 +}
  113 +
  114 +/*
  115 + * SYSRSTn Duration Counter Support
  116 + *
  117 + * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
  118 + * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
  119 + * The SYSRSTn duration counter is useful for implementing a manufacturer
  120 + * or factory reset. Upon a long reset assertion that is greater than a
  121 + * pre-configured environment variable value for sysrstdelay,
  122 + * The counter value is stored in the SYSRSTn Length Counter Register
  123 + * The counter is based on the 25-MHz reference clock (40ns)
  124 + * It is a 29-bit counter, yielding a maximum counting duration of
  125 + * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
  126 + * it remains at this value until counter reset is triggered by setting
  127 + * bit 31 of KW_REG_SYSRST_CNT
  128 + */
  129 +static void kw_sysrst_action(void)
  130 +{
  131 + int ret;
  132 + char *s = getenv("sysrstcmd");
  133 +
  134 + if (!s) {
  135 + debug("Error.. %s failed, check sysrstcmd\n",
  136 + __FUNCTION__);
  137 + return;
  138 + }
  139 +
  140 + debug("Starting %s process...\n", __FUNCTION__);
  141 + ret = run_command(s, 0);
  142 + if (ret != 0)
  143 + debug("Error.. %s failed\n", __FUNCTION__);
  144 + else
  145 + debug("%s process finished\n", __FUNCTION__);
  146 +}
  147 +
  148 +static void kw_sysrst_check(void)
  149 +{
  150 + u32 sysrst_cnt, sysrst_dly;
  151 + char *s;
  152 +
  153 + /*
  154 + * no action if sysrstdelay environment variable is not defined
  155 + */
  156 + s = getenv("sysrstdelay");
  157 + if (s == NULL)
  158 + return;
  159 +
  160 + /* read sysrstdelay value */
  161 + sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
  162 +
  163 + /* read SysRst Length counter register (bits 28:0) */
  164 + sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
  165 + debug("H/w Rst hold time: %d.%d secs\n",
  166 + sysrst_cnt / SYSRST_CNT_1SEC_VAL,
  167 + sysrst_cnt % SYSRST_CNT_1SEC_VAL);
  168 +
  169 + /* clear the counter for next valid read*/
  170 + writel(1 << 31, KW_REG_SYSRST_CNT);
  171 +
  172 + /*
  173 + * sysrst_action:
  174 + * if H/w Reset key is pressed and hold for time
  175 + * more than sysrst_dly in seconds
  176 + */
  177 + if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
  178 + kw_sysrst_action();
  179 +}
  180 +
  181 +#if defined(CONFIG_DISPLAY_CPUINFO)
  182 +int print_cpuinfo(void)
  183 +{
  184 + char *rev = "??";
  185 + u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
  186 + u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
  187 +
  188 + if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
  189 + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
  190 + return -1;
  191 + }
  192 +
  193 + switch (revid) {
  194 + case 0:
  195 + if (devid == 0x6281)
  196 + rev = "Z0";
  197 + else if (devid == 0x6282)
  198 + rev = "A0";
  199 + break;
  200 + case 1:
  201 + rev = "A1";
  202 + break;
  203 + case 2:
  204 + rev = "A0";
  205 + break;
  206 + case 3:
  207 + rev = "A1";
  208 + break;
  209 + default:
  210 + break;
  211 + }
  212 +
  213 + printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
  214 + return 0;
  215 +}
  216 +#endif /* CONFIG_DISPLAY_CPUINFO */
  217 +
  218 +#ifdef CONFIG_ARCH_CPU_INIT
  219 +int arch_cpu_init(void)
  220 +{
  221 + u32 reg;
  222 + struct kwcpu_registers *cpureg =
  223 + (struct kwcpu_registers *)KW_CPU_REG_BASE;
  224 +
  225 + /* Linux expects` the internal registers to be at 0xf1000000 */
  226 + writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
  227 +
  228 + /* Enable and invalidate L2 cache in write through mode */
  229 + writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
  230 + invalidate_l2_cache();
  231 +
  232 + kw_config_adr_windows();
  233 +
  234 +#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
  235 + /*
  236 + * Configures the I/O voltage of the pads connected to Egigabit
  237 + * Ethernet interface to 1.8V
  238 + * By default it is set to 3.3V
  239 + */
  240 + reg = readl(KW_REG_MPP_OUT_DRV_REG);
  241 + reg |= (1 << 7);
  242 + writel(reg, KW_REG_MPP_OUT_DRV_REG);
  243 +#endif
  244 +#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
  245 + /*
  246 + * Set egiga port0/1 in normal functional mode
  247 + * This is required becasue on kirkwood by default ports are in reset mode
  248 + * OS egiga driver may not have provision to set them in normal mode
  249 + * and if u-boot is build without network support, network may fail at OS level
  250 + */
  251 + reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
  252 + reg &= ~(1 << 4); /* Clear PortReset Bit */
  253 + writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
  254 + reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
  255 + reg &= ~(1 << 4); /* Clear PortReset Bit */
  256 + writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
  257 +#endif
  258 +#ifdef CONFIG_KIRKWOOD_PCIE_INIT
  259 + /*
  260 + * Enable PCI Express Port0
  261 + */
  262 + reg = readl(&cpureg->ctrl_stat);
  263 + reg |= (1 << 0); /* Set PEX0En Bit */
  264 + writel(reg, &cpureg->ctrl_stat);
  265 +#endif
  266 + return 0;
  267 +}
  268 +#endif /* CONFIG_ARCH_CPU_INIT */
  269 +
  270 +/*
  271 + * SOC specific misc init
  272 + */
  273 +#if defined(CONFIG_ARCH_MISC_INIT)
  274 +int arch_misc_init(void)
  275 +{
  276 + volatile u32 temp;
  277 +
  278 + /*CPU streaming & write allocate */
  279 + temp = readfr_extra_feature_reg();
  280 + temp &= ~(1 << 28); /* disable wr alloc */
  281 + writefr_extra_feature_reg(temp);
  282 +
  283 + temp = readfr_extra_feature_reg();
  284 + temp &= ~(1 << 29); /* streaming disabled */
  285 + writefr_extra_feature_reg(temp);
  286 +
  287 + /* L2Cache settings */
  288 + temp = readfr_extra_feature_reg();
  289 + /* Disable L2C pre fetch - Set bit 24 */
  290 + temp |= (1 << 24);
  291 + /* enable L2C - Set bit 22 */
  292 + temp |= (1 << 22);
  293 + writefr_extra_feature_reg(temp);
  294 +
  295 + icache_enable();
  296 + /* Change reset vector to address 0x0 */
  297 + temp = get_cr();
  298 + set_cr(temp & ~CR_V);
  299 +
  300 + /* checks and execute resset to factory event */
  301 + kw_sysrst_check();
  302 +
  303 + return 0;
  304 +}
  305 +#endif /* CONFIG_ARCH_MISC_INIT */
  306 +
  307 +#ifdef CONFIG_MVGBE
  308 +int cpu_eth_init(bd_t *bis)
  309 +{
  310 + mvgbe_initialize(bis);
  311 + return 0;
  312 +}
  313 +#endif
  314 +
  315 +#ifdef CONFIG_MVEBU_MMC
  316 +int board_mmc_init(bd_t *bis)
  317 +{
  318 + mvebu_mmc_init(bis);
  319 + return 0;
  320 +}
  321 +#endif /* CONFIG_MVEBU_MMC */
arch/arm/mach-kirkwood/mpp.c
Diff comments   View file @ 56f86e3
  1 +/*
  2 + * arch/arm/mach-kirkwood/mpp.c
  3 + *
  4 + * MPP functions for Marvell Kirkwood SoCs
  5 + * Referenced from Linux kernel source
  6 + *
  7 + * This file is licensed under the terms of the GNU General Public
  8 + * License version 2. This program is licensed "as is" without any
  9 + * warranty of any kind, whether express or implied.
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <asm/io.h>
  14 +#include <asm/arch/cpu.h>
  15 +#include <asm/arch/soc.h>
  16 +#include <asm/arch/mpp.h>
  17 +
  18 +static u32 kirkwood_variant(void)
  19 +{
  20 + switch (readl(KW_REG_DEVICE_ID) & 0x03) {
  21 + case 1:
  22 + return MPP_F6192_MASK;
  23 + case 2:
  24 + return MPP_F6281_MASK;
  25 + default:
  26 + debug("MPP setup: unknown kirkwood variant\n");
  27 + return 0;
  28 + }
  29 +}
  30 +
  31 +#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
  32 +#define MPP_NR_REGS (1 + MPP_MAX/8)
  33 +
  34 +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
  35 +{
  36 + u32 mpp_ctrl[MPP_NR_REGS];
  37 + unsigned int variant_mask;
  38 + int i;
  39 +
  40 + variant_mask = kirkwood_variant();
  41 + if (!variant_mask)
  42 + return;
  43 +
  44 + debug( "initial MPP regs:");
  45 + for (i = 0; i < MPP_NR_REGS; i++) {
  46 + mpp_ctrl[i] = readl(MPP_CTRL(i));
  47 + debug(" %08x", mpp_ctrl[i]);
  48 + }
  49 + debug("\n");
  50 +
  51 +
  52 + while (*mpp_list) {
  53 + unsigned int num = MPP_NUM(*mpp_list);
  54 + unsigned int sel = MPP_SEL(*mpp_list);
  55 + unsigned int sel_save;
  56 + int shift;
  57 +
  58 + if (num > MPP_MAX) {
  59 + debug("kirkwood_mpp_conf: invalid MPP "
  60 + "number (%u)\n", num);
  61 + continue;
  62 + }
  63 + if (!(*mpp_list & variant_mask)) {
  64 + debug("kirkwood_mpp_conf: requested MPP%u config "
  65 + "unavailable on this hardware\n", num);
  66 + continue;
  67 + }
  68 +
  69 + shift = (num & 7) << 2;
  70 +
  71 + if (mpp_save) {
  72 + sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
  73 + *mpp_save = num | (sel_save << 8) | variant_mask;
  74 + mpp_save++;
  75 + }
  76 +
  77 + mpp_ctrl[num / 8] &= ~(0xf << shift);
  78 + mpp_ctrl[num / 8] |= sel << shift;
  79 +
  80 + mpp_list++;
  81 + }
  82 +
  83 + debug(" final MPP regs:");
  84 + for (i = 0; i < MPP_NR_REGS; i++) {
  85 + writel(mpp_ctrl[i], MPP_CTRL(i));
  86 + debug(" %08x", mpp_ctrl[i]);
  87 + }
  88 + debug("\n");
  89 +
  90 +}