zynq: Add Z-Turn board

The Z-Turn board is a low cost development board based on the Xilinx Zynq SoC. While it's powerful and quite versatile, it so far lacked upstream support. This patch adds basic support for the Z-Turn. It does however for now miss enablement for MIO51 reset which means that USB and ethernet don't work. For that either FSBL or SPL need to be adjusted. The SPL part will follow later. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

zynq: Add Z-Turn board
The Z-Turn board is a low cost development board based on the Xilinx Zynq SoC. While it's powerful and quite versatile, it so far lacked upstream support. This patch adds basic support for the Z-Turn. It does however for now miss enablement for MIO51 reset which means that USB and ethernet don't work. For that either FSBL or SPL need to be adjusted. The SPL part will follow later. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf · Michal Simek
1 parent 61d8eeb0bc
Showing 3 changed files with 221 additions and 0 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/zynq-zturn-myir.dts
configs/zynq_z_turn_defconfig
@@ -132,6 +132,7 @@
 	zynq-topic-miami.dtb \
 	zynq-topic-miamilite.dtb \
 	zynq-topic-miamiplus.dtb \
+	zynq-zturn-myir.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm011.dtb \
 	zynq-zc770-xm012.dtb \
+/*
+ *  Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
+ *  Copyright (C) 2017 Alexander Graf <agraf@suse.de>
+ *
+ *  Based on zynq-zed.dts which is:
+ *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq Z-Turn MYIR Board";
+	compatible = "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		led_r {
+			label = "led_r";
+			gpios = <&gpio0 0x72 0x1>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_g {
+			label = "led_g";
+			gpios = <&gpio0 0x73 0x1>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_b {
+			label = "led_b";
+			gpios = <&gpio0 0x74 0x1>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		usr_led1 {
+			label = "usr_led1";
+			gpios = <&gpio0 0x0 0x1>;
+			default-state = "off";
+			linux,default-trigger = "none";
+		};
+
+		usr_led2 {
+			label = "usr_led2";
+			gpios = <&gpio0 0x9 0x1>;
+			default-state = "off";
+			linux,default-trigger = "none";
+		};
+	};
+
+	gpio-beep {
+		compatible = "gpio-beeper";
+		label = "pl-beep";
+		gpios = <&gpio0 0x75 0x0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		autorepeat;
+		K1 {
+			label = "K1";
+			gpios = <&gpio0 0x32 0x1>;
+			linux,code = <0x66>;
+			gpio-key,wakeup;
+			autorepeat;
+		};
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+	fclk-enable = <0xf>;
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	stlm75@49 {
+		status = "okay";
+		compatible = "lm75";
+		reg = <0x49>;
+	};
+
+	adxl345@53 {
+		compatible = "adi,adxl34x", "adxl34x";
+		reg = <0x53>;
+		interrupt-parent = <&intc>;
+		interrupts = <0x0 0x1e 0x4>;
+	};
+};
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_NOWHERE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
...	...	@@ -132,6 +132,7 @@
132	132	zynq-topic-miami.dtb \
133	133	zynq-topic-miamilite.dtb \
134	134	zynq-topic-miamiplus.dtb \
	135	+ zynq-zturn-myir.dtb \
135	136	zynq-zc770-xm010.dtb \
136	137	zynq-zc770-xm011.dtb \
137	138	zynq-zc770-xm012.dtb \
	1	+/*
	2	+ * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
	3	+ * Copyright (C) 2017 Alexander Graf <agraf@suse.de>
	4	+ *
	5	+ * Based on zynq-zed.dts which is:
	6	+ * Copyright (C) 2011 - 2014 Xilinx
	7	+ * Copyright (C) 2012 National Instruments Corp.
	8	+ *
	9	+ * This software is licensed under the terms of the GNU General Public
	10	+ * License version 2, as published by the Free Software Foundation, and
	11	+ * may be copied, distributed, and modified under those terms.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ */
	18	+/dts-v1/;
	19	+/include/ "zynq-7000.dtsi"
	20	+
	21	+/ {
	22	+ model = "Zynq Z-Turn MYIR Board";
	23	+ compatible = "xlnx,zynq-7000";
	24	+
	25	+ aliases {
	26	+ ethernet0 = &gem0;
	27	+ serial0 = &uart1;
	28	+ serial1 = &uart0;
	29	+ spi0 = &qspi;
	30	+ mmc0 = &sdhci0;
	31	+ };
	32	+
	33	+ memory {
	34	+ device_type = "memory";
	35	+ reg = <0x0 0x40000000>;
	36	+ };
	37	+
	38	+ chosen {
	39	+ stdout-path = "serial0:115200n8";
	40	+ };
	41	+
	42	+ gpio-leds {
	43	+ compatible = "gpio-leds";
	44	+ led_r {
	45	+ label = "led_r";
	46	+ gpios = <&gpio0 0x72 0x1>;
	47	+ default-state = "on";
	48	+ linux,default-trigger = "heartbeat";
	49	+ };
	50	+
	51	+ led_g {
	52	+ label = "led_g";
	53	+ gpios = <&gpio0 0x73 0x1>;
	54	+ default-state = "on";
	55	+ linux,default-trigger = "heartbeat";
	56	+ };
	57	+
	58	+ led_b {
	59	+ label = "led_b";
	60	+ gpios = <&gpio0 0x74 0x1>;
	61	+ default-state = "on";
	62	+ linux,default-trigger = "heartbeat";
	63	+ };
	64	+
	65	+ usr_led1 {
	66	+ label = "usr_led1";
	67	+ gpios = <&gpio0 0x0 0x1>;
	68	+ default-state = "off";
	69	+ linux,default-trigger = "none";
	70	+ };
	71	+
	72	+ usr_led2 {
	73	+ label = "usr_led2";
	74	+ gpios = <&gpio0 0x9 0x1>;
	75	+ default-state = "off";
	76	+ linux,default-trigger = "none";
	77	+ };
	78	+ };
	79	+
	80	+ gpio-beep {
	81	+ compatible = "gpio-beeper";
	82	+ label = "pl-beep";
	83	+ gpios = <&gpio0 0x75 0x0>;
	84	+ };
	85	+
	86	+ gpio-keys {
	87	+ compatible = "gpio-keys";
	88	+ #address-cells = <0x1>;
	89	+ #size-cells = <0x0>;
	90	+ autorepeat;
	91	+ K1 {
	92	+ label = "K1";
	93	+ gpios = <&gpio0 0x32 0x1>;
	94	+ linux,code = <0x66>;
	95	+ gpio-key,wakeup;
	96	+ autorepeat;
	97	+ };
	98	+ };
	99	+};
	100	+
	101	+&clkc {
	102	+ ps-clk-frequency = <33333333>;
	103	+ fclk-enable = <0xf>;
	104	+};
	105	+
	106	+&qspi {
	107	+ u-boot,dm-pre-reloc;
	108	+ status = "okay";
	109	+};
	110	+
	111	+&gem0 {
	112	+ status = "okay";
	113	+ phy-mode = "rgmii-id";
	114	+ phy-handle = <&ethernet_phy>;
	115	+
	116	+ ethernet_phy: ethernet-phy@0 {
	117	+ reg = <0x0>;
	118	+ };
	119	+};
	120	+
	121	+&sdhci0 {
	122	+ u-boot,dm-pre-reloc;
	123	+ status = "okay";
	124	+};
	125	+
	126	+&uart0 {
	127	+ u-boot,dm-pre-reloc;
	128	+ status = "okay";
	129	+};
	130	+
	131	+&uart1 {
	132	+ u-boot,dm-pre-reloc;
	133	+ status = "okay";
	134	+};
	135	+
	136	+&usb0 {
	137	+ status = "okay";
	138	+ dr_mode = "host";
	139	+};
	140	+
	141	+&can0 {
	142	+ status = "okay";
	143	+};
	144	+
	145	+&i2c0 {
	146	+ status = "okay";
	147	+ clock-frequency = <400000>;
	148	+
	149	+ stlm75@49 {
	150	+ status = "okay";
	151	+ compatible = "lm75";
	152	+ reg = <0x49>;
	153	+ };
	154	+
	155	+ adxl345@53 {
	156	+ compatible = "adi,adxl34x", "adxl34x";
	157	+ reg = <0x53>;
	158	+ interrupt-parent = <&intc>;
	159	+ interrupts = <0x0 0x1e 0x4>;
	160	+ };
	161	+};
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_ZYNQ=y
	3	+CONFIG_SYS_TEXT_BASE=0x4000000
	4	+CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
	5	+CONFIG_DEBUG_UART=y
	6	+CONFIG_FIT=y
	7	+CONFIG_FIT_SIGNATURE=y
	8	+CONFIG_FIT_VERBOSE=y
	9	+CONFIG_ENV_IS_NOWHERE=y
	10	+# CONFIG_DISPLAY_CPUINFO is not set
	11	+CONFIG_SPL=y
	12	+CONFIG_SPL_OS_BOOT=y
	13	+CONFIG_HUSH_PARSER=y
	14	+CONFIG_SYS_PROMPT="Zynq> "
	15	+# CONFIG_CMD_IMLS is not set
	16	+# CONFIG_CMD_FLASH is not set
	17	+CONFIG_CMD_MMC=y
	18	+CONFIG_CMD_SF=y
	19	+CONFIG_CMD_USB=y
	20	+CONFIG_CMD_DFU=y
	21	+CONFIG_CMD_GPIO=y
	22	+# CONFIG_CMD_SETEXPR is not set
	23	+CONFIG_CMD_TFTPPUT=y
	24	+CONFIG_CMD_DHCP=y
	25	+CONFIG_CMD_MII=y
	26	+CONFIG_CMD_PING=y
	27	+CONFIG_CMD_CACHE=y
	28	+CONFIG_CMD_EXT2=y
	29	+CONFIG_CMD_EXT4=y
	30	+CONFIG_CMD_EXT4_WRITE=y
	31	+CONFIG_CMD_FAT=y
	32	+CONFIG_CMD_FS_GENERIC=y
	33	+CONFIG_NET_RANDOM_ETHADDR=y
	34	+CONFIG_SPL_DM_SEQ_ALIAS=y
	35	+CONFIG_DFU_MMC=y
	36	+CONFIG_DFU_RAM=y
	37	+CONFIG_MMC_SDHCI=y
	38	+CONFIG_MMC_SDHCI_ZYNQ=y
	39	+CONFIG_SPI_FLASH=y
	40	+CONFIG_SPI_FLASH_BAR=y
	41	+CONFIG_SPI_FLASH_SPANSION=y
	42	+CONFIG_SPI_FLASH_STMICRO=y
	43	+CONFIG_SPI_FLASH_WINBOND=y
	44	+CONFIG_ZYNQ_GEM=y
	45	+CONFIG_DEBUG_UART_ZYNQ=y
	46	+CONFIG_DEBUG_UART_BASE=0xe0001000
	47	+CONFIG_DEBUG_UART_CLOCK=50000000
	48	+CONFIG_ZYNQ_QSPI=y
	49	+CONFIG_USB=y
	50	+CONFIG_USB_EHCI_HCD=y
	51	+CONFIG_USB_ULPI_VIEWPORT=y
	52	+CONFIG_USB_ULPI=y
	53	+CONFIG_USB_STORAGE=y
	54	+CONFIG_USB_GADGET=y
	55	+CONFIG_CI_UDC=y
	56	+CONFIG_USB_GADGET_DOWNLOAD=y
	57	+CONFIG_G_DNL_MANUFACTURER="Xilinx"
	58	+CONFIG_G_DNL_VENDOR_NUM=0x03FD
	59	+CONFIG_G_DNL_PRODUCT_NUM=0x0300