x86: Add queensbay and crownbay Kconfig files

Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>

x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng · Simon Glass
1 parent 240a79d95c
Showing 3 changed files with 112 additions and 0 deletions Side-by-side Diff
arch/x86/Kconfig
arch/x86/cpu/queensbay/Kconfig
board/intel/crownbay/Kconfig
@@ -32,6 +32,15 @@
 	  and it provides a 2560x1700 high resolution touch-enabled LCD
 	  display.
  
+config TARGET_CROWNBAY
+	bool "Support Intel Crown Bay CRB"
+	help
+	  This is the Intel Crown Bay Customer Reference Board. It contains
+	  the Intel Atom Processor E6xx populated on the COM Express module
+	  with 1GB DDR2 soldered down memory and a carrier board with the
+	  Intel Platform Controller Hub EG20T, other system components and
+	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
 endchoice
  
 config RAMBASE
  
@@ -310,9 +319,13 @@
  
 source "arch/x86/cpu/ivybridge/Kconfig"
  
+source "arch/x86/cpu/queensbay/Kconfig"
+
 source "board/coreboot/coreboot/Kconfig"
  
 source "board/google/chromebook_link/Kconfig"
+
+source "board/intel/crownbay/Kconfig"
  
 endmenu
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_QUEENSBAY
+	bool
+	select HAVE_FSP
+	select HAVE_CMC
+
+if INTEL_QUEENSBAY
+
+config HAVE_FSP
+	bool "Add an Firmware Support Package binary"
+	help
+	  Select this option to add an Firmware Support Package binary to
+	  the resulting U-Boot image. It is a binary blob which U-Boot uses
+	  to set up SDRAM and other chipset specific initialization.
+
+	  Note: Without this binary U-Boot will not be able to set up its
+	  SDRAM so will not boot.
+
+config FSP_FILE
+	string "Firmware Support Package binary filename"
+	depends on HAVE_FSP
+	default "fsp.bin"
+	help
+	  The filename of the file to use as Firmware Support Package binary
+	  in the board directory.
+
+config FSP_LOCATION
+	hex "Firmware Support Package binary location"
+	depends on HAVE_FSP
+	default 0xfffc0000
+	help
+	  FSP is not Position Independent Code (PIC) and the whole FSP has to
+	  be rebased if it is placed at a location which is different from the
+	  perferred base address specified during the FSP build. Use Intel's
+	  Binary Configuration Tool (BCT) to do the rebase.
+
+	  The default base address of 0xfffc0000 indicates that the binary must
+	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
+
+config FSP_TEMP_RAM_ADDR
+	hex
+	default 0x2000000
+	help
+	  Stack top address which is used in FspInit after DRAM is ready and
+	  CAR is disabled.
+
+config HAVE_CMC
+	bool "Add a Chipset Micro Code state machine binary"
+	help
+	  Select this option to add a Chipset Micro Code state machine binary
+	  to the resulting U-Boot image. It is a 64K data block of machine
+	  specific code which must be put in the flash for the processor to
+	  access when powered up before system BIOS is executed.
+
+config CMC_FILE
+	string "Chipset Micro Code state machine filename"
+	depends on HAVE_CMC
+	default "cmc.bin"
+	help
+	  The filename of the file to use as Chipset Micro Code state machine
+	  binary in the board directory.
+
+config CMC_LOCATION
+	hex "Chipset Micro Code state machine binary location"
+	depends on HAVE_CMC
+	default 0xfffb0000
+	help
+	  The location of the CMC binary is determined by a strap. It must be
+	  put in flash at a location matching the strap-determined base address.
+
+	  The default base address of 0xfffb0000 indicates that the binary must
+	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
+
+endif
+if TARGET_CROWNBAY
+
+config SYS_BOARD
+	default "crownbay"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "queensbay"
+
+config SYS_CONFIG_NAME
+	default "crownbay"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select INTEL_QUEENSBAY
+	select BOARD_ROMSIZE_KB_1024
+
+endif
...	...	@@ -32,6 +32,15 @@
32	32	and it provides a 2560x1700 high resolution touch-enabled LCD
33	33	display.
34	34
	35	+config TARGET_CROWNBAY
	36	+ bool "Support Intel Crown Bay CRB"
	37	+ help
	38	+ This is the Intel Crown Bay Customer Reference Board. It contains
	39	+ the Intel Atom Processor E6xx populated on the COM Express module
	40	+ with 1GB DDR2 soldered down memory and a carrier board with the
	41	+ Intel Platform Controller Hub EG20T, other system components and
	42	+ peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
	43	+
35	44	endchoice
36	45
37	46	config RAMBASE
38	47
...	...	@@ -310,9 +319,13 @@
310	319
311	320	source "arch/x86/cpu/ivybridge/Kconfig"
312	321
	322	+source "arch/x86/cpu/queensbay/Kconfig"
	323	+
313	324	source "board/coreboot/coreboot/Kconfig"
314	325
315	326	source "board/google/chromebook_link/Kconfig"
	327	+
	328	+source "board/intel/crownbay/Kconfig"
316	329
317	330	endmenu
	1	+#
	2	+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+config INTEL_QUEENSBAY
	8	+ bool
	9	+ select HAVE_FSP
	10	+ select HAVE_CMC
	11	+
	12	+if INTEL_QUEENSBAY
	13	+
	14	+config HAVE_FSP
	15	+ bool "Add an Firmware Support Package binary"
	16	+ help
	17	+ Select this option to add an Firmware Support Package binary to
	18	+ the resulting U-Boot image. It is a binary blob which U-Boot uses
	19	+ to set up SDRAM and other chipset specific initialization.
	20	+
	21	+ Note: Without this binary U-Boot will not be able to set up its
	22	+ SDRAM so will not boot.
	23	+
	24	+config FSP_FILE
	25	+ string "Firmware Support Package binary filename"
	26	+ depends on HAVE_FSP
	27	+ default "fsp.bin"
	28	+ help
	29	+ The filename of the file to use as Firmware Support Package binary
	30	+ in the board directory.
	31	+
	32	+config FSP_LOCATION
	33	+ hex "Firmware Support Package binary location"
	34	+ depends on HAVE_FSP
	35	+ default 0xfffc0000
	36	+ help
	37	+ FSP is not Position Independent Code (PIC) and the whole FSP has to
	38	+ be rebased if it is placed at a location which is different from the
	39	+ perferred base address specified during the FSP build. Use Intel's
	40	+ Binary Configuration Tool (BCT) to do the rebase.
	41	+
	42	+ The default base address of 0xfffc0000 indicates that the binary must
	43	+ be located at offset 0xc0000 from the beginning of a 1MB flash device.
	44	+
	45	+config FSP_TEMP_RAM_ADDR
	46	+ hex
	47	+ default 0x2000000
	48	+ help
	49	+ Stack top address which is used in FspInit after DRAM is ready and
	50	+ CAR is disabled.
	51	+
	52	+config HAVE_CMC
	53	+ bool "Add a Chipset Micro Code state machine binary"
	54	+ help
	55	+ Select this option to add a Chipset Micro Code state machine binary
	56	+ to the resulting U-Boot image. It is a 64K data block of machine
	57	+ specific code which must be put in the flash for the processor to
	58	+ access when powered up before system BIOS is executed.
	59	+
	60	+config CMC_FILE
	61	+ string "Chipset Micro Code state machine filename"
	62	+ depends on HAVE_CMC
	63	+ default "cmc.bin"
	64	+ help
	65	+ The filename of the file to use as Chipset Micro Code state machine
	66	+ binary in the board directory.
	67	+
	68	+config CMC_LOCATION
	69	+ hex "Chipset Micro Code state machine binary location"
	70	+ depends on HAVE_CMC
	71	+ default 0xfffb0000
	72	+ help
	73	+ The location of the CMC binary is determined by a strap. It must be
	74	+ put in flash at a location matching the strap-determined base address.
	75	+
	76	+ The default base address of 0xfffb0000 indicates that the binary must
	77	+ be located at offset 0xb0000 from the beginning of a 1MB flash device.
	78	+
	79	+endif
	1	+if TARGET_CROWNBAY
	2	+
	3	+config SYS_BOARD
	4	+ default "crownbay"
	5	+
	6	+config SYS_VENDOR
	7	+ default "intel"
	8	+
	9	+config SYS_SOC
	10	+ default "queensbay"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "crownbay"
	14	+
	15	+config BOARD_SPECIFIC_OPTIONS # dummy
	16	+ def_bool y
	17	+ select INTEL_QUEENSBAY
	18	+ select BOARD_ROMSIZE_KB_1024
	19	+
	20	+endif