Commit 58fd563ffb279b3a93d6ab332f14d041ac500bb9
1 parent
1bcdde2499
Exists in
master
and in
50 other branches
at91: remove all occourances of CONFIG_AT91_LEGACY
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Showing 8 changed files with 13 additions and 246 deletions Side-by-side Diff
- arch/arm/include/asm/arch-at91/at91_pio.h
- arch/arm/include/asm/arch-at91/at91_pit.h
- arch/arm/include/asm/arch-at91/at91_pmc.h
- arch/arm/include/asm/arch-at91/at91_spi.h
- arch/arm/include/asm/arch-at91/at91_wdt.h
- arch/arm/include/asm/arch-at91/at91cap9.h
- arch/arm/include/asm/arch-at91/at91sam9_smc.h
- doc/README.at91-soc
arch/arm/include/asm/arch-at91/at91_pio.h
... | ... | @@ -151,38 +151,5 @@ |
151 | 151 | #define AT91_PIO_PORTD 0x3 |
152 | 152 | #define AT91_PIO_PORTE 0x4 |
153 | 153 | |
154 | -#ifdef CONFIG_AT91_LEGACY | |
155 | - | |
156 | -#define PIO_PER 0x00 /* Enable Register */ | |
157 | -#define PIO_PDR 0x04 /* Disable Register */ | |
158 | -#define PIO_PSR 0x08 /* Status Register */ | |
159 | -#define PIO_OER 0x10 /* Output Enable Register */ | |
160 | -#define PIO_ODR 0x14 /* Output Disable Register */ | |
161 | -#define PIO_OSR 0x18 /* Output Status Register */ | |
162 | -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | |
163 | -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | |
164 | -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | |
165 | -#define PIO_SODR 0x30 /* Set Output Data Register */ | |
166 | -#define PIO_CODR 0x34 /* Clear Output Data Register */ | |
167 | -#define PIO_ODSR 0x38 /* Output Data Status Register */ | |
168 | -#define PIO_PDSR 0x3c /* Pin Data Status Register */ | |
169 | -#define PIO_IER 0x40 /* Interrupt Enable Register */ | |
170 | -#define PIO_IDR 0x44 /* Interrupt Disable Register */ | |
171 | -#define PIO_IMR 0x48 /* Interrupt Mask Register */ | |
172 | -#define PIO_ISR 0x4c /* Interrupt Status Register */ | |
173 | -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ | |
174 | -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | |
175 | -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ | |
176 | -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ | |
177 | -#define PIO_PUER 0x64 /* Pull-up Enable Register */ | |
178 | -#define PIO_PUSR 0x68 /* Pull-up Status Register */ | |
179 | -#define PIO_ASR 0x70 /* Peripheral A Select Register */ | |
180 | -#define PIO_BSR 0x74 /* Peripheral B Select Register */ | |
181 | -#define PIO_ABSR 0x78 /* AB Status Register */ | |
182 | -#define PIO_OWER 0xa0 /* Output Write Enable Register */ | |
183 | -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ | |
184 | -#define PIO_OWSR 0xa8 /* Output Write Status Register */ | |
185 | -#endif | |
186 | - | |
187 | 154 | #endif |
arch/arm/include/asm/arch-at91/at91_pit.h
... | ... | @@ -25,21 +25,5 @@ |
25 | 25 | #define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff) |
26 | 26 | #define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) |
27 | 27 | |
28 | -#ifdef CONFIG_AT91_LEGACY | |
29 | - | |
30 | -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ | |
31 | -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | |
32 | -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ | |
33 | -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ | |
34 | - | |
35 | -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ | |
36 | -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ | |
37 | - | |
38 | -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ | |
39 | -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ | |
40 | -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ | |
41 | -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ | |
42 | - | |
43 | -#endif /* CONFIG_AT91_LEGACY */ | |
44 | 28 | #endif |
arch/arm/include/asm/arch-at91/at91_pmc.h
... | ... | @@ -14,13 +14,15 @@ |
14 | 14 | #ifndef AT91_PMC_H |
15 | 15 | #define AT91_PMC_H |
16 | 16 | |
17 | +#ifdef __ASSEMBLY__ | |
18 | + | |
17 | 19 | #define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) |
18 | 20 | #define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) |
19 | 21 | #define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) |
20 | 22 | #define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) |
21 | 23 | #define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) |
22 | 24 | |
23 | -#ifndef __ASSEMBLY__ | |
25 | +#else | |
24 | 26 | |
25 | 27 | #include <asm/types.h> |
26 | 28 | |
... | ... | @@ -137,13 +139,6 @@ |
137 | 139 | #define AT91_PMC_IXR_PCKRDY2 0x00000400 |
138 | 140 | #define AT91_PMC_IXR_PCKRDY3 0x00000800 |
139 | 141 | |
140 | -#ifdef CONFIG_AT91_LEGACY | |
141 | -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | |
142 | -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | |
143 | - | |
144 | -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | |
145 | -#endif | |
146 | - | |
147 | 142 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
148 | 143 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
149 | 144 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
150 | 145 | |
151 | 146 | |
152 | 147 | |
... | ... | @@ -159,34 +154,18 @@ |
159 | 154 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
160 | 155 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ |
161 | 156 | |
162 | -#ifdef CONFIG_AT91_LEGACY | |
163 | -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | |
164 | -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | |
165 | -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | |
166 | - | |
167 | -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ | |
168 | -#endif | |
169 | - | |
170 | 157 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
171 | 158 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ |
172 | 159 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ |
173 | 160 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ |
174 | 161 | |
175 | -#ifdef CONFIG_AT91_LEGACY | |
176 | -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | |
177 | -#endif | |
178 | 162 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
179 | 163 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ |
180 | 164 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
181 | -#ifdef CONFIG_AT91_LEGACY | |
182 | -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | |
183 | -#endif | |
165 | + | |
184 | 166 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
185 | 167 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ |
186 | -#ifdef CONFIG_AT91_LEGACY | |
187 | -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | |
188 | -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | |
189 | -#endif | |
168 | + | |
190 | 169 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ |
191 | 170 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
192 | 171 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
... | ... | @@ -198,9 +177,6 @@ |
198 | 177 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
199 | 178 | #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ |
200 | 179 | |
201 | -#ifdef CONFIG_AT91_LEGACY | |
202 | -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | |
203 | -#endif | |
204 | 180 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
205 | 181 | #define AT91_PMC_CSS_SLOW (0 << 0) |
206 | 182 | #define AT91_PMC_CSS_MAIN (1 << 0) |
... | ... | @@ -228,9 +204,6 @@ |
228 | 204 | #define AT91_PMC_PDIV_1 (0 << 12) |
229 | 205 | #define AT91_PMC_PDIV_2 (1 << 12) |
230 | 206 | |
231 | -#ifdef CONFIG_AT91_LEGACY | |
232 | -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */ | |
233 | -#endif | |
234 | 207 | #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ |
235 | 208 | #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ |
236 | 209 | #define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ |
... | ... | @@ -238,13 +211,6 @@ |
238 | 211 | #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ |
239 | 212 | #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ |
240 | 213 | |
241 | -#ifdef CONFIG_AT91_LEGACY | |
242 | -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | |
243 | - | |
244 | -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | |
245 | -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | |
246 | -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | |
247 | -#endif | |
248 | 214 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
249 | 215 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
250 | 216 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
251 | 217 | |
252 | 218 | |
... | ... | @@ -255,14 +221,7 @@ |
255 | 221 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
256 | 222 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
257 | 223 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
258 | -#ifdef CONFIG_AT91_LEGACY | |
259 | -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | |
260 | 224 | |
261 | -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ | |
262 | -#endif | |
263 | 225 | #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ |
264 | -#ifdef CONFIG_AT91_LEGACY | |
265 | -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ | |
266 | -#endif /* CONFIG_AT91_LEGACY */ | |
267 | 226 | #endif |
arch/arm/include/asm/arch-at91/at91_spi.h
arch/arm/include/asm/arch-at91/at91_wdt.h
... | ... | @@ -40,26 +40,5 @@ |
40 | 40 | #define AT91_WDT_MR_WDDBGHLT 0x10000000 |
41 | 41 | #define AT91_WDT_MR_WDIDLEHLT 0x20000000 |
42 | 42 | |
43 | -#ifdef CONFIG_AT91_LEGACY | |
44 | - | |
45 | -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | |
46 | -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | |
47 | -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ | |
48 | - | |
49 | -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | |
50 | -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | |
51 | -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | |
52 | -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | |
53 | -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | |
54 | -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | |
55 | -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | |
56 | -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | |
57 | -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | |
58 | - | |
59 | -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | |
60 | -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | |
61 | -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | |
62 | - | |
63 | -#endif /* CONFIG_AT91_LEGACY */ | |
64 | 43 | #endif |
arch/arm/include/asm/arch-at91/at91cap9.h
... | ... | @@ -55,75 +55,6 @@ |
55 | 55 | #define AT91_RSTC_BASE 0xfffffd00 |
56 | 56 | #define AT91_PIT_BASE 0xfffffd30 |
57 | 57 | |
58 | -#ifdef CONFIG_AT91_LEGACY | |
59 | - | |
60 | -/* | |
61 | - * User Peripheral physical base addresses. | |
62 | - */ | |
63 | -#define AT91CAP9_BASE_UDPHS 0xfff78000 | |
64 | -#define AT91CAP9_BASE_TCB0 0xfff7c000 | |
65 | -#define AT91CAP9_BASE_TC0 0xfff7c000 | |
66 | -#define AT91CAP9_BASE_TC1 0xfff7c040 | |
67 | -#define AT91CAP9_BASE_TC2 0xfff7c080 | |
68 | -#define AT91CAP9_BASE_MCI0 0xfff80000 | |
69 | -#define AT91CAP9_BASE_MCI1 0xfff84000 | |
70 | -#define AT91CAP9_BASE_TWI 0xfff88000 | |
71 | -#define AT91CAP9_BASE_US0 0xfff8c000 | |
72 | -#define AT91CAP9_BASE_US1 0xfff90000 | |
73 | -#define AT91CAP9_BASE_US2 0xfff94000 | |
74 | -#define AT91CAP9_BASE_SSC0 0xfff98000 | |
75 | -#define AT91CAP9_BASE_SSC1 0xfff9c000 | |
76 | -#define AT91CAP9_BASE_AC97C 0xfffa0000 | |
77 | -#define AT91CAP9_BASE_SPI0 0xfffa4000 | |
78 | -#define AT91CAP9_BASE_SPI1 0xfffa8000 | |
79 | -#define AT91CAP9_BASE_CAN 0xfffac000 | |
80 | -#define AT91CAP9_BASE_PWMC 0xfffb8000 | |
81 | -#define AT91CAP9_BASE_EMAC 0xfffbc000 | |
82 | -#define AT91CAP9_BASE_ADC 0xfffc0000 | |
83 | -#define AT91CAP9_BASE_ISI 0xfffc4000 | |
84 | -#define AT91_BASE_SYS 0xffffe200 | |
85 | - | |
86 | -/* | |
87 | - * System Peripherals (offset from AT91_BASE_SYS) | |
88 | - */ | |
89 | -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) | |
90 | -#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) | |
91 | -#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) | |
92 | -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) | |
93 | -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | |
94 | -#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) | |
95 | -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) | |
96 | -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | |
97 | -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | |
98 | -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | |
99 | -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | |
100 | -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | |
101 | -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | |
102 | -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | |
103 | -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | |
104 | -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | |
105 | -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | |
106 | -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | |
107 | -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | |
108 | -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | |
109 | -#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) | |
110 | -#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) | |
111 | - | |
112 | -#define AT91_USART0 AT91CAP9_BASE_US0 | |
113 | -#define AT91_USART1 AT91CAP9_BASE_US1 | |
114 | -#define AT91_USART2 AT91CAP9_BASE_US2 | |
115 | - | |
116 | -/* | |
117 | - * SCKCR flags | |
118 | - */ | |
119 | -#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ | |
120 | -#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ | |
121 | -#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ | |
122 | -#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ | |
123 | -#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) | |
124 | -#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) | |
125 | - | |
126 | -#endif /* CONFIG_AT91_LEGACY */ | |
127 | 58 | /* |
128 | 59 | * Internal Memory. |
129 | 60 | */ |
arch/arm/include/asm/arch-at91/at91sam9_smc.h
... | ... | @@ -73,65 +73,5 @@ |
73 | 73 | #define AT91_SMC_MODE_PS_16 0x20000000 |
74 | 74 | #define AT91_SMC_MODE_PS_32 0x30000000 |
75 | 75 | |
76 | -#ifdef CONFIG_AT91_LEGACY | |
77 | - | |
78 | -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | |
79 | -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | |
80 | -#define AT91_SMC_NWESETUP_(x) ((x) << 0) | |
81 | -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | |
82 | -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | |
83 | -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | |
84 | -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) | |
85 | -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | |
86 | -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | |
87 | - | |
88 | -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | |
89 | -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | |
90 | -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) | |
91 | -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | |
92 | -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | |
93 | -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | |
94 | -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) | |
95 | -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | |
96 | -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | |
97 | - | |
98 | -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | |
99 | -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | |
100 | -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) | |
101 | -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | |
102 | -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | |
103 | - | |
104 | -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | |
105 | -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | |
106 | -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | |
107 | -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | |
108 | -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | |
109 | -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | |
110 | -#define AT91_SMC_EXNWMODE_READY (3 << 4) | |
111 | -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | |
112 | -#define AT91_SMC_BAT_SELECT (0 << 8) | |
113 | -#define AT91_SMC_BAT_WRITE (1 << 8) | |
114 | -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | |
115 | -#define AT91_SMC_DBW_8 (0 << 12) | |
116 | -#define AT91_SMC_DBW_16 (1 << 12) | |
117 | -#define AT91_SMC_DBW_32 (2 << 12) | |
118 | -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | |
119 | -#define AT91_SMC_TDF_(x) ((x) << 16) | |
120 | -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | |
121 | -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | |
122 | -#define AT91_SMC_PS (3 << 28) /* Page Size */ | |
123 | -#define AT91_SMC_PS_4 (0 << 28) | |
124 | -#define AT91_SMC_PS_8 (1 << 28) | |
125 | -#define AT91_SMC_PS_16 (2 << 28) | |
126 | -#define AT91_SMC_PS_32 (3 << 28) | |
127 | - | |
128 | -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | |
129 | -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | |
130 | -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | |
131 | -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | |
132 | -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | |
133 | -#endif | |
134 | - | |
135 | -#endif | |
136 | 76 | #endif |
doc/README.at91-soc
... | ... | @@ -39,4 +39,11 @@ |
39 | 39 | 3. add new structures for SoC access |
40 | 40 | 4. Convert arch, driver and boards file to new SoC |
41 | 41 | 5. remove legacy code, if all boards and drives are ready |
42 | + | |
43 | +2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>: | |
44 | + | |
45 | +The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but | |
46 | +remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The | |
47 | +AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point | |
48 | +to fix until this README can be removed. |