Commit 59629c2897eb84c4550cf95b49e0761fbd23cef0
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8bc50f0b6d
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spl/mpc85xx: move udelay to cpu code
It applies to non-Freescale 85xx boards as well as Freescale boards, so it doesn't belong in board/freescale. Plus, it needs to come out of nand_spl if it's to be used by the new SPL. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Showing 5 changed files with 20 additions and 55 deletions Side-by-side Diff
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
... | ... | @@ -21,9 +21,13 @@ |
21 | 21 | */ |
22 | 22 | |
23 | 23 | #include <common.h> |
24 | +#include <asm/processor.h> | |
25 | +#include <asm/global_data.h> | |
24 | 26 | #include <asm/fsl_ifc.h> |
25 | 27 | #include <asm/io.h> |
26 | 28 | |
29 | +DECLARE_GLOBAL_DATA_PTR; | |
30 | + | |
27 | 31 | void cpu_init_f(void) |
28 | 32 | { |
29 | 33 | #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) |
... | ... | @@ -39,5 +43,18 @@ |
39 | 43 | out_be32(&l2cache->l2ctl, |
40 | 44 | (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); |
41 | 45 | #endif |
46 | +} | |
47 | + | |
48 | +#ifndef CONFIG_SYS_FSL_TBCLK_DIV | |
49 | +#define CONFIG_SYS_FSL_TBCLK_DIV 8 | |
50 | +#endif | |
51 | + | |
52 | +void udelay(unsigned long usec) | |
53 | +{ | |
54 | + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); | |
55 | + u32 ticks = ticks_per_usec * usec; | |
56 | + u32 s = mfspr(SPRN_TBRL); | |
57 | + | |
58 | + while ((mfspr(SPRN_TBRL) - s) < ticks); | |
42 | 59 | } |
nand_spl/board/freescale/common.c
1 | -/* | |
2 | - * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | - * Author: Matthew McClintock <msm@freescale.com> | |
4 | - * | |
5 | - * This program is free software; you can redistribute it and/or | |
6 | - * modify it under the terms of the GNU General Public License as | |
7 | - * published by the Free Software Foundation; either version 2 of | |
8 | - * the License, or (at your option) any later version. | |
9 | - * | |
10 | - * This program is distributed in the hope that it will be useful, | |
11 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | - * | |
14 | - * GNU General Public License for more details. | |
15 | - * | |
16 | - * You should have received a copy of the GNU General Public License | |
17 | - * along with this program; if not, write to the Free Software | |
18 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | - * MA 02111-1307 USA | |
20 | - * | |
21 | - */ | |
22 | - | |
23 | -#include <common.h> | |
24 | -#include <asm/processor.h> | |
25 | -#include <asm/global_data.h> | |
26 | - | |
27 | -DECLARE_GLOBAL_DATA_PTR; | |
28 | - | |
29 | -#ifndef CONFIG_SYS_FSL_TBCLK_DIV | |
30 | -#define CONFIG_SYS_FSL_TBCLK_DIV 8 | |
31 | -#endif | |
32 | - | |
33 | -void udelay(unsigned long usec) | |
34 | -{ | |
35 | - u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); | |
36 | - u32 ticks = ticks_per_usec * usec; | |
37 | - u32 s = mfspr(SPRN_TBRL); | |
38 | - | |
39 | - while ((mfspr(SPRN_TBRL) - s) < ticks); | |
40 | -} |
nand_spl/board/freescale/p1010rdb/Makefile
... | ... | @@ -40,8 +40,7 @@ |
40 | 40 | |
41 | 41 | SOBJS = start.o resetvec.o ticks.o |
42 | 42 | COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ |
43 | - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ | |
44 | - ../common.o | |
43 | + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o | |
45 | 44 | |
46 | 45 | SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) |
47 | 46 | OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) |
... | ... | @@ -130,9 +129,6 @@ |
130 | 129 | $(obj)nand_boot.c: |
131 | 130 | @rm -f $(obj)nand_boot.c |
132 | 131 | ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c |
133 | -$(obj)../common.c: | |
134 | - @rm -f $(obj)../common.c | |
135 | - ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c | |
136 | 132 | endif |
137 | 133 | |
138 | 134 | ######################################################################### |
nand_spl/board/freescale/p1023rds/Makefile
... | ... | @@ -35,8 +35,7 @@ |
35 | 35 | |
36 | 36 | SOBJS = start.o resetvec.o |
37 | 37 | COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ |
38 | - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ | |
39 | - ../common.o | |
38 | + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o | |
40 | 39 | |
41 | 40 | SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) |
42 | 41 | OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) |
... | ... | @@ -121,9 +120,6 @@ |
121 | 120 | $(obj)nand_boot.c: |
122 | 121 | @rm -f $(obj)nand_boot.c |
123 | 122 | ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c |
124 | -$(obj)../common.c: | |
125 | - @rm -f $(obj)../common.c | |
126 | - ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c | |
127 | 123 | endif |
128 | 124 | |
129 | 125 | ######################################################################### |
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
... | ... | @@ -40,8 +40,7 @@ |
40 | 40 | |
41 | 41 | SOBJS = start.o resetvec.o |
42 | 42 | COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ |
43 | - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ | |
44 | - ../common.o | |
43 | + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o | |
45 | 44 | |
46 | 45 | SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) |
47 | 46 | OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) |
... | ... | @@ -125,9 +124,6 @@ |
125 | 124 | $(obj)nand_boot.c: |
126 | 125 | @rm -f $(obj)nand_boot.c |
127 | 126 | ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c |
128 | -$(obj)../common.c: | |
129 | - @rm -f $(obj)../common.c | |
130 | - ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c | |
131 | 127 | endif |
132 | 128 | |
133 | 129 | ######################################################################### |