Eric Lee / smarc-uboot | Embedian Git Server

Commit 5a20397b007e9c1482997cf4418639e9ba3df5fe

Authored by Rob Herring 2015-03-24 06:56:59 +0800

Committed by Pantelis Antoniou 2015-05-05 17:29:36 +0800

Exists in v2017.01-smarct4x and in 37 other branches

mmc: remove the MMC_MODE_HC flag

High capacity support is not a host capability, but a device capability
that is queried via the OCR. The flag in the operating conditions
request argument can just be set unconditionally. This matches the Linux
implementation.

[panto] Hand merged and renumbering MMC_MODE_DDR_52MHz.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>

Showing 14 changed files with 12 additions and 22 deletions Inline Diff

drivers/mmc/dw_mmc.c
drivers/mmc/fsl_esdhc.c
drivers/mmc/kona_sdhci.c
drivers/mmc/mmc.c
drivers/mmc/mvebu_mmc.c
drivers/mmc/mxsmmc.c
drivers/mmc/omap_hsmmc.c
drivers/mmc/s3c_sdi.c
drivers/mmc/s5p_sdhci.c
drivers/mmc/sh_mmcif.c
drivers/mmc/sunxi_mmc.c
drivers/mmc/tegra_mmc.c
drivers/mmc/zynq_sdhci.c
include/mmc.h

drivers/mmc/dw_mmc.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* (C) Copyright 2012 SAMSUNG Electronics	2	* (C) Copyright 2012 SAMSUNG Electronics
3	* Jaehoon Chung <jh80.chung@samsung.com>	3	* Jaehoon Chung <jh80.chung@samsung.com>
4	* Rajeshawari Shinde <rajeshwari.s@samsung.com>	4	* Rajeshawari Shinde <rajeshwari.s@samsung.com>
5	*	5	*
6	* SPDX-License-Identifier: GPL-2.0+	6	* SPDX-License-Identifier: GPL-2.0+
7	*/	7	*/
8		8
9	#include <bouncebuf.h>	9	#include <bouncebuf.h>
10	#include <common.h>	10	#include <common.h>
11	#include <malloc.h>	11	#include <malloc.h>
12	#include <mmc.h>	12	#include <mmc.h>
13	#include <dwmmc.h>	13	#include <dwmmc.h>
14	#include <asm-generic/errno.h>	14	#include <asm-generic/errno.h>
15		15
16	#define PAGE_SIZE 4096	16	#define PAGE_SIZE 4096
17		17
18	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)	18	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
19	{	19	{
20	unsigned long timeout = 1000;	20	unsigned long timeout = 1000;
21	u32 ctrl;	21	u32 ctrl;
22		22
23	dwmci_writel(host, DWMCI_CTRL, value);	23	dwmci_writel(host, DWMCI_CTRL, value);
24		24
25	while (timeout--) {	25	while (timeout--) {
26	ctrl = dwmci_readl(host, DWMCI_CTRL);	26	ctrl = dwmci_readl(host, DWMCI_CTRL);
27	if (!(ctrl & DWMCI_RESET_ALL))	27	if (!(ctrl & DWMCI_RESET_ALL))
28	return 1;	28	return 1;
29	}	29	}
30	return 0;	30	return 0;
31	}	31	}
32		32
33	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,	33	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
34	u32 desc0, u32 desc1, u32 desc2)	34	u32 desc0, u32 desc1, u32 desc2)
35	{	35	{
36	struct dwmci_idmac *desc = idmac;	36	struct dwmci_idmac *desc = idmac;
37		37
38	desc->flags = desc0;	38	desc->flags = desc0;
39	desc->cnt = desc1;	39	desc->cnt = desc1;
40	desc->addr = desc2;	40	desc->addr = desc2;
41	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);	41	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
42	}	42	}
43		43
44	static void dwmci_prepare_data(struct dwmci_host *host,	44	static void dwmci_prepare_data(struct dwmci_host *host,
45	struct mmc_data *data,	45	struct mmc_data *data,
46	struct dwmci_idmac *cur_idmac,	46	struct dwmci_idmac *cur_idmac,
47	void *bounce_buffer)	47	void *bounce_buffer)
48	{	48	{
49	unsigned long ctrl;	49	unsigned long ctrl;
50	unsigned int i = 0, flags, cnt, blk_cnt;	50	unsigned int i = 0, flags, cnt, blk_cnt;
51	ulong data_start, data_end;	51	ulong data_start, data_end;
52		52
53		53
54	blk_cnt = data->blocks;	54	blk_cnt = data->blocks;
55		55
56	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);	56	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
57		57
58	data_start = (ulong)cur_idmac;	58	data_start = (ulong)cur_idmac;
59	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);	59	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
60		60
61	do {	61	do {
62	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;	62	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
63	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;	63	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
64	if (blk_cnt <= 8) {	64	if (blk_cnt <= 8) {
65	flags \|= DWMCI_IDMAC_LD;	65	flags \|= DWMCI_IDMAC_LD;
66	cnt = data->blocksize * blk_cnt;	66	cnt = data->blocksize * blk_cnt;
67	} else	67	} else
68	cnt = data->blocksize * 8;	68	cnt = data->blocksize * 8;
69		69
70	dwmci_set_idma_desc(cur_idmac, flags, cnt,	70	dwmci_set_idma_desc(cur_idmac, flags, cnt,
71	(u32)bounce_buffer + (i * PAGE_SIZE));	71	(u32)bounce_buffer + (i * PAGE_SIZE));
72		72
73	if (blk_cnt <= 8)	73	if (blk_cnt <= 8)
74	break;	74	break;
75	blk_cnt -= 8;	75	blk_cnt -= 8;
76	cur_idmac++;	76	cur_idmac++;
77	i++;	77	i++;
78	} while(1);	78	} while(1);
79		79
80	data_end = (ulong)cur_idmac;	80	data_end = (ulong)cur_idmac;
81	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);	81	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
82		82
83	ctrl = dwmci_readl(host, DWMCI_CTRL);	83	ctrl = dwmci_readl(host, DWMCI_CTRL);
84	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;	84	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
85	dwmci_writel(host, DWMCI_CTRL, ctrl);	85	dwmci_writel(host, DWMCI_CTRL, ctrl);
86		86
87	ctrl = dwmci_readl(host, DWMCI_BMOD);	87	ctrl = dwmci_readl(host, DWMCI_BMOD);
88	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;	88	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
89	dwmci_writel(host, DWMCI_BMOD, ctrl);	89	dwmci_writel(host, DWMCI_BMOD, ctrl);
90		90
91	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);	91	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
92	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);	92	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
93	}	93	}
94		94
95	static int dwmci_set_transfer_mode(struct dwmci_host *host,	95	static int dwmci_set_transfer_mode(struct dwmci_host *host,
96	struct mmc_data *data)	96	struct mmc_data *data)
97	{	97	{
98	unsigned long mode;	98	unsigned long mode;
99		99
100	mode = DWMCI_CMD_DATA_EXP;	100	mode = DWMCI_CMD_DATA_EXP;
101	if (data->flags & MMC_DATA_WRITE)	101	if (data->flags & MMC_DATA_WRITE)
102	mode \|= DWMCI_CMD_RW;	102	mode \|= DWMCI_CMD_RW;
103		103
104	return mode;	104	return mode;
105	}	105	}
106		106
107	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,	107	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
108	struct mmc_data *data)	108	struct mmc_data *data)
109	{	109	{
110	struct dwmci_host *host = mmc->priv;	110	struct dwmci_host *host = mmc->priv;
111	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,	111	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
112	data ? DIV_ROUND_UP(data->blocks, 8) : 0);	112	data ? DIV_ROUND_UP(data->blocks, 8) : 0);
113	int flags = 0, i;	113	int flags = 0, i;
114	unsigned int timeout = 100000;	114	unsigned int timeout = 100000;
115	u32 retry = 10000;	115	u32 retry = 10000;
116	u32 mask, ctrl;	116	u32 mask, ctrl;
117	ulong start = get_timer(0);	117	ulong start = get_timer(0);
118	struct bounce_buffer bbstate;	118	struct bounce_buffer bbstate;
119		119
120	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {	120	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
121	if (get_timer(start) > timeout) {	121	if (get_timer(start) > timeout) {
122	printf("%s: Timeout on data busy\n", __func__);	122	printf("%s: Timeout on data busy\n", __func__);
123	return TIMEOUT;	123	return TIMEOUT;
124	}	124	}
125	}	125	}
126		126
127	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);	127	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
128		128
129	if (data) {	129	if (data) {
130	if (data->flags == MMC_DATA_READ) {	130	if (data->flags == MMC_DATA_READ) {
131	bounce_buffer_start(&bbstate, (void*)data->dest,	131	bounce_buffer_start(&bbstate, (void*)data->dest,
132	data->blocksize *	132	data->blocksize *
133	data->blocks, GEN_BB_WRITE);	133	data->blocks, GEN_BB_WRITE);
134	} else {	134	} else {
135	bounce_buffer_start(&bbstate, (void*)data->src,	135	bounce_buffer_start(&bbstate, (void*)data->src,
136	data->blocksize *	136	data->blocksize *
137	data->blocks, GEN_BB_READ);	137	data->blocks, GEN_BB_READ);
138	}	138	}
139	dwmci_prepare_data(host, data, cur_idmac,	139	dwmci_prepare_data(host, data, cur_idmac,
140	bbstate.bounce_buffer);	140	bbstate.bounce_buffer);
141	}	141	}
142		142
143	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);	143	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
144		144
145	if (data)	145	if (data)
146	flags = dwmci_set_transfer_mode(host, data);	146	flags = dwmci_set_transfer_mode(host, data);
147		147
148	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))	148	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
149	return -1;	149	return -1;
150		150
151	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)	151	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
152	flags \|= DWMCI_CMD_ABORT_STOP;	152	flags \|= DWMCI_CMD_ABORT_STOP;
153	else	153	else
154	flags \|= DWMCI_CMD_PRV_DAT_WAIT;	154	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
155		155
156	if (cmd->resp_type & MMC_RSP_PRESENT) {	156	if (cmd->resp_type & MMC_RSP_PRESENT) {
157	flags \|= DWMCI_CMD_RESP_EXP;	157	flags \|= DWMCI_CMD_RESP_EXP;
158	if (cmd->resp_type & MMC_RSP_136)	158	if (cmd->resp_type & MMC_RSP_136)
159	flags \|= DWMCI_CMD_RESP_LENGTH;	159	flags \|= DWMCI_CMD_RESP_LENGTH;
160	}	160	}
161		161
162	if (cmd->resp_type & MMC_RSP_CRC)	162	if (cmd->resp_type & MMC_RSP_CRC)
163	flags \|= DWMCI_CMD_CHECK_CRC;	163	flags \|= DWMCI_CMD_CHECK_CRC;
164		164
165	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);	165	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
166		166
167	debug("Sending CMD%d\n",cmd->cmdidx);	167	debug("Sending CMD%d\n",cmd->cmdidx);
168		168
169	dwmci_writel(host, DWMCI_CMD, flags);	169	dwmci_writel(host, DWMCI_CMD, flags);
170		170
171	for (i = 0; i < retry; i++) {	171	for (i = 0; i < retry; i++) {
172	mask = dwmci_readl(host, DWMCI_RINTSTS);	172	mask = dwmci_readl(host, DWMCI_RINTSTS);
173	if (mask & DWMCI_INTMSK_CDONE) {	173	if (mask & DWMCI_INTMSK_CDONE) {
174	if (!data)	174	if (!data)
175	dwmci_writel(host, DWMCI_RINTSTS, mask);	175	dwmci_writel(host, DWMCI_RINTSTS, mask);
176	break;	176	break;
177	}	177	}
178	}	178	}
179		179
180	if (i == retry) {	180	if (i == retry) {
181	printf("%s: Timeout.\n", __func__);	181	printf("%s: Timeout.\n", __func__);
182	return TIMEOUT;	182	return TIMEOUT;
183	}	183	}
184		184
185	if (mask & DWMCI_INTMSK_RTO) {	185	if (mask & DWMCI_INTMSK_RTO) {
186	/*	186	/*
187	* Timeout here is not necessarily fatal. (e)MMC cards	187	* Timeout here is not necessarily fatal. (e)MMC cards
188	* will splat here when they receive CMD55 as they do	188	* will splat here when they receive CMD55 as they do
189	* not support this command and that is exactly the way	189	* not support this command and that is exactly the way
190	* to tell them apart from SD cards. Thus, this output	190	* to tell them apart from SD cards. Thus, this output
191	* below shall be debug(). eMMC cards also do not favor	191	* below shall be debug(). eMMC cards also do not favor
192	* CMD8, please keep that in mind.	192	* CMD8, please keep that in mind.
193	*/	193	*/
194	debug("%s: Response Timeout.\n", __func__);	194	debug("%s: Response Timeout.\n", __func__);
195	return TIMEOUT;	195	return TIMEOUT;
196	} else if (mask & DWMCI_INTMSK_RE) {	196	} else if (mask & DWMCI_INTMSK_RE) {
197	printf("%s: Response Error.\n", __func__);	197	printf("%s: Response Error.\n", __func__);
198	return -1;	198	return -1;
199	}	199	}
200		200
201		201
202	if (cmd->resp_type & MMC_RSP_PRESENT) {	202	if (cmd->resp_type & MMC_RSP_PRESENT) {
203	if (cmd->resp_type & MMC_RSP_136) {	203	if (cmd->resp_type & MMC_RSP_136) {
204	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);	204	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
205	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);	205	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
206	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);	206	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
207	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);	207	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
208	} else {	208	} else {
209	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);	209	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
210	}	210	}
211	}	211	}
212		212
213	if (data) {	213	if (data) {
214	do {	214	do {
215	mask = dwmci_readl(host, DWMCI_RINTSTS);	215	mask = dwmci_readl(host, DWMCI_RINTSTS);
216	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {	216	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
217	printf("%s: DATA ERROR!\n", __func__);	217	printf("%s: DATA ERROR!\n", __func__);
218	return -1;	218	return -1;
219	}	219	}
220	} while (!(mask & DWMCI_INTMSK_DTO));	220	} while (!(mask & DWMCI_INTMSK_DTO));
221		221
222	dwmci_writel(host, DWMCI_RINTSTS, mask);	222	dwmci_writel(host, DWMCI_RINTSTS, mask);
223		223
224	ctrl = dwmci_readl(host, DWMCI_CTRL);	224	ctrl = dwmci_readl(host, DWMCI_CTRL);
225	ctrl &= ~(DWMCI_DMA_EN);	225	ctrl &= ~(DWMCI_DMA_EN);
226	dwmci_writel(host, DWMCI_CTRL, ctrl);	226	dwmci_writel(host, DWMCI_CTRL, ctrl);
227		227
228	bounce_buffer_stop(&bbstate);	228	bounce_buffer_stop(&bbstate);
229	}	229	}
230		230
231	udelay(100);	231	udelay(100);
232		232
233	return 0;	233	return 0;
234	}	234	}
235		235
236	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)	236	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
237	{	237	{
238	u32 div, status;	238	u32 div, status;
239	int timeout = 10000;	239	int timeout = 10000;
240	unsigned long sclk;	240	unsigned long sclk;
241		241
242	if ((freq == host->clock) \|\| (freq == 0))	242	if ((freq == host->clock) \|\| (freq == 0))
243	return 0;	243	return 0;
244	/*	244	/*
245	* If host->get_mmc_clk isn't defined,	245	* If host->get_mmc_clk isn't defined,
246	* then assume that host->bus_hz is source clock value.	246	* then assume that host->bus_hz is source clock value.
247	* host->bus_hz should be set by user.	247	* host->bus_hz should be set by user.
248	*/	248	*/
249	if (host->get_mmc_clk)	249	if (host->get_mmc_clk)
250	sclk = host->get_mmc_clk(host);	250	sclk = host->get_mmc_clk(host);
251	else if (host->bus_hz)	251	else if (host->bus_hz)
252	sclk = host->bus_hz;	252	sclk = host->bus_hz;
253	else {	253	else {
254	printf("%s: Didn't get source clock value.\n", __func__);	254	printf("%s: Didn't get source clock value.\n", __func__);
255	return -EINVAL;	255	return -EINVAL;
256	}	256	}
257		257
258	if (sclk == freq)	258	if (sclk == freq)
259	div = 0; /* bypass mode */	259	div = 0; /* bypass mode */
260	else	260	else
261	div = DIV_ROUND_UP(sclk, 2 * freq);	261	div = DIV_ROUND_UP(sclk, 2 * freq);
262		262
263	dwmci_writel(host, DWMCI_CLKENA, 0);	263	dwmci_writel(host, DWMCI_CLKENA, 0);
264	dwmci_writel(host, DWMCI_CLKSRC, 0);	264	dwmci_writel(host, DWMCI_CLKSRC, 0);
265		265
266	dwmci_writel(host, DWMCI_CLKDIV, div);	266	dwmci_writel(host, DWMCI_CLKDIV, div);
267	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|	267	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
268	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);	268	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
269		269
270	do {	270	do {
271	status = dwmci_readl(host, DWMCI_CMD);	271	status = dwmci_readl(host, DWMCI_CMD);
272	if (timeout-- < 0) {	272	if (timeout-- < 0) {
273	printf("%s: Timeout!\n", __func__);	273	printf("%s: Timeout!\n", __func__);
274	return -ETIMEDOUT;	274	return -ETIMEDOUT;
275	}	275	}
276	} while (status & DWMCI_CMD_START);	276	} while (status & DWMCI_CMD_START);
277		277
278	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|	278	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
279	DWMCI_CLKEN_LOW_PWR);	279	DWMCI_CLKEN_LOW_PWR);
280		280
281	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|	281	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
282	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);	282	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
283		283
284	timeout = 10000;	284	timeout = 10000;
285	do {	285	do {
286	status = dwmci_readl(host, DWMCI_CMD);	286	status = dwmci_readl(host, DWMCI_CMD);
287	if (timeout-- < 0) {	287	if (timeout-- < 0) {
288	printf("%s: Timeout!\n", __func__);	288	printf("%s: Timeout!\n", __func__);
289	return -ETIMEDOUT;	289	return -ETIMEDOUT;
290	}	290	}
291	} while (status & DWMCI_CMD_START);	291	} while (status & DWMCI_CMD_START);
292		292
293	host->clock = freq;	293	host->clock = freq;
294		294
295	return 0;	295	return 0;
296	}	296	}
297		297
298	static void dwmci_set_ios(struct mmc *mmc)	298	static void dwmci_set_ios(struct mmc *mmc)
299	{	299	{
300	struct dwmci_host host = (struct dwmci_host )mmc->priv;	300	struct dwmci_host host = (struct dwmci_host )mmc->priv;
301	u32 ctype, regs;	301	u32 ctype, regs;
302		302
303	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);	303	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
304		304
305	dwmci_setup_bus(host, mmc->clock);	305	dwmci_setup_bus(host, mmc->clock);
306	switch (mmc->bus_width) {	306	switch (mmc->bus_width) {
307	case 8:	307	case 8:
308	ctype = DWMCI_CTYPE_8BIT;	308	ctype = DWMCI_CTYPE_8BIT;
309	break;	309	break;
310	case 4:	310	case 4:
311	ctype = DWMCI_CTYPE_4BIT;	311	ctype = DWMCI_CTYPE_4BIT;
312	break;	312	break;
313	default:	313	default:
314	ctype = DWMCI_CTYPE_1BIT;	314	ctype = DWMCI_CTYPE_1BIT;
315	break;	315	break;
316	}	316	}
317		317
318	dwmci_writel(host, DWMCI_CTYPE, ctype);	318	dwmci_writel(host, DWMCI_CTYPE, ctype);
319		319
320	regs = dwmci_readl(host, DWMCI_UHS_REG);	320	regs = dwmci_readl(host, DWMCI_UHS_REG);
321	if (mmc->ddr_mode)	321	if (mmc->ddr_mode)
322	regs \|= DWMCI_DDR_MODE;	322	regs \|= DWMCI_DDR_MODE;
323	else	323	else
324	regs &= ~DWMCI_DDR_MODE;	324	regs &= ~DWMCI_DDR_MODE;
325		325
326	dwmci_writel(host, DWMCI_UHS_REG, regs);	326	dwmci_writel(host, DWMCI_UHS_REG, regs);
327		327
328	if (host->clksel)	328	if (host->clksel)
329	host->clksel(host);	329	host->clksel(host);
330	}	330	}
331		331
332	static int dwmci_init(struct mmc *mmc)	332	static int dwmci_init(struct mmc *mmc)
333	{	333	{
334	struct dwmci_host *host = mmc->priv;	334	struct dwmci_host *host = mmc->priv;
335		335
336	if (host->board_init)	336	if (host->board_init)
337	host->board_init(host);	337	host->board_init(host);
338		338
339	dwmci_writel(host, DWMCI_PWREN, 1);	339	dwmci_writel(host, DWMCI_PWREN, 1);
340		340
341	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {	341	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
342	printf("%s[%d] Fail-reset!!\n", __func__, __LINE__);	342	printf("%s[%d] Fail-reset!!\n", __func__, __LINE__);
343	return -1;	343	return -1;
344	}	344	}
345		345
346	/* Enumerate at 400KHz */	346	/* Enumerate at 400KHz */
347	dwmci_setup_bus(host, mmc->cfg->f_min);	347	dwmci_setup_bus(host, mmc->cfg->f_min);
348		348
349	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);	349	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
350	dwmci_writel(host, DWMCI_INTMASK, 0);	350	dwmci_writel(host, DWMCI_INTMASK, 0);
351		351
352	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);	352	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
353		353
354	dwmci_writel(host, DWMCI_IDINTEN, 0);	354	dwmci_writel(host, DWMCI_IDINTEN, 0);
355	dwmci_writel(host, DWMCI_BMOD, 1);	355	dwmci_writel(host, DWMCI_BMOD, 1);
356		356
357	if (host->fifoth_val) {	357	if (host->fifoth_val) {
358	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);	358	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
359	}	359	}
360		360
361	dwmci_writel(host, DWMCI_CLKENA, 0);	361	dwmci_writel(host, DWMCI_CLKENA, 0);
362	dwmci_writel(host, DWMCI_CLKSRC, 0);	362	dwmci_writel(host, DWMCI_CLKSRC, 0);
363		363
364	return 0;	364	return 0;
365	}	365	}
366		366
367	static const struct mmc_ops dwmci_ops = {	367	static const struct mmc_ops dwmci_ops = {
368	.send_cmd = dwmci_send_cmd,	368	.send_cmd = dwmci_send_cmd,
369	.set_ios = dwmci_set_ios,	369	.set_ios = dwmci_set_ios,
370	.init = dwmci_init,	370	.init = dwmci_init,
371	};	371	};
372		372
373	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)	373	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
374	{	374	{
375	host->cfg.name = host->name;	375	host->cfg.name = host->name;
376	host->cfg.ops = &dwmci_ops;	376	host->cfg.ops = &dwmci_ops;
377	host->cfg.f_min = min_clk;	377	host->cfg.f_min = min_clk;
378	host->cfg.f_max = max_clk;	378	host->cfg.f_max = max_clk;
379		379
380	host->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;	380	host->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
381		381
382	host->cfg.host_caps = host->caps;	382	host->cfg.host_caps = host->caps;
383		383
384	if (host->buswidth == 8) {	384	if (host->buswidth == 8) {
385	host->cfg.host_caps \|= MMC_MODE_8BIT;	385	host->cfg.host_caps \|= MMC_MODE_8BIT;
386	host->cfg.host_caps &= ~MMC_MODE_4BIT;	386	host->cfg.host_caps &= ~MMC_MODE_4BIT;
387	} else {	387	} else {
388	host->cfg.host_caps \|= MMC_MODE_4BIT;	388	host->cfg.host_caps \|= MMC_MODE_4BIT;
389	host->cfg.host_caps &= ~MMC_MODE_8BIT;	389	host->cfg.host_caps &= ~MMC_MODE_8BIT;
390	}	390	}
391	host->cfg.host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_HC;	391	host->cfg.host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz;
392		392
393	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;	393	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
394		394
395	host->mmc = mmc_create(&host->cfg, host);	395	host->mmc = mmc_create(&host->cfg, host);
396	if (host->mmc == NULL)	396	if (host->mmc == NULL)
397	return -1;	397	return -1;
398		398
399	return 0;	399	return 0;
400	}	400	}
401		401

drivers/mmc/fsl_esdhc.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc	2	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
3	* Andy Fleming	3	* Andy Fleming
4	*	4	*
5	* Based vaguely on the pxa mmc code:	5	* Based vaguely on the pxa mmc code:
6	* (C) Copyright 2003	6	* (C) Copyright 2003
7	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net	7	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8	*	8	*
9	* SPDX-License-Identifier: GPL-2.0+	9	* SPDX-License-Identifier: GPL-2.0+
10	*/	10	*/
11		11
12	#include <config.h>	12	#include <config.h>
13	#include <common.h>	13	#include <common.h>
14	#include <command.h>	14	#include <command.h>
15	#include <hwconfig.h>	15	#include <hwconfig.h>
16	#include <mmc.h>	16	#include <mmc.h>
17	#include <part.h>	17	#include <part.h>
18	#include <malloc.h>	18	#include <malloc.h>
19	#include <mmc.h>	19	#include <mmc.h>
20	#include <fsl_esdhc.h>	20	#include <fsl_esdhc.h>
21	#include <fdt_support.h>	21	#include <fdt_support.h>
22	#include <asm/io.h>	22	#include <asm/io.h>
23		23
24	DECLARE_GLOBAL_DATA_PTR;	24	DECLARE_GLOBAL_DATA_PTR;
25		25
26	#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC \| IRQSTATEN_TC \| \	26	#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC \| IRQSTATEN_TC \| \
27	IRQSTATEN_CINT \| \	27	IRQSTATEN_CINT \| \
28	IRQSTATEN_CTOE \| IRQSTATEN_CCE \| IRQSTATEN_CEBE \| \	28	IRQSTATEN_CTOE \| IRQSTATEN_CCE \| IRQSTATEN_CEBE \| \
29	IRQSTATEN_CIE \| IRQSTATEN_DTOE \| IRQSTATEN_DCE \| \	29	IRQSTATEN_CIE \| IRQSTATEN_DTOE \| IRQSTATEN_DCE \| \
30	IRQSTATEN_DEBE \| IRQSTATEN_BRR \| IRQSTATEN_BWR \| \	30	IRQSTATEN_DEBE \| IRQSTATEN_BRR \| IRQSTATEN_BWR \| \
31	IRQSTATEN_DINT)	31	IRQSTATEN_DINT)
32		32
33	struct fsl_esdhc {	33	struct fsl_esdhc {
34	uint dsaddr; /* SDMA system address register */	34	uint dsaddr; /* SDMA system address register */
35	uint blkattr; /* Block attributes register */	35	uint blkattr; /* Block attributes register */
36	uint cmdarg; /* Command argument register */	36	uint cmdarg; /* Command argument register */
37	uint xfertyp; /* Transfer type register */	37	uint xfertyp; /* Transfer type register */
38	uint cmdrsp0; /* Command response 0 register */	38	uint cmdrsp0; /* Command response 0 register */
39	uint cmdrsp1; /* Command response 1 register */	39	uint cmdrsp1; /* Command response 1 register */
40	uint cmdrsp2; /* Command response 2 register */	40	uint cmdrsp2; /* Command response 2 register */
41	uint cmdrsp3; /* Command response 3 register */	41	uint cmdrsp3; /* Command response 3 register */
42	uint datport; /* Buffer data port register */	42	uint datport; /* Buffer data port register */
43	uint prsstat; /* Present state register */	43	uint prsstat; /* Present state register */
44	uint proctl; /* Protocol control register */	44	uint proctl; /* Protocol control register */
45	uint sysctl; /* System Control Register */	45	uint sysctl; /* System Control Register */
46	uint irqstat; /* Interrupt status register */	46	uint irqstat; /* Interrupt status register */
47	uint irqstaten; /* Interrupt status enable register */	47	uint irqstaten; /* Interrupt status enable register */
48	uint irqsigen; /* Interrupt signal enable register */	48	uint irqsigen; /* Interrupt signal enable register */
49	uint autoc12err; /* Auto CMD error status register */	49	uint autoc12err; /* Auto CMD error status register */
50	uint hostcapblt; /* Host controller capabilities register */	50	uint hostcapblt; /* Host controller capabilities register */
51	uint wml; /* Watermark level register */	51	uint wml; /* Watermark level register */
52	uint mixctrl; /* For USDHC */	52	uint mixctrl; /* For USDHC */
53	char reserved1[4]; /* reserved */	53	char reserved1[4]; /* reserved */
54	uint fevt; /* Force event register */	54	uint fevt; /* Force event register */
55	uint admaes; /* ADMA error status register */	55	uint admaes; /* ADMA error status register */
56	uint adsaddr; /* ADMA system address register */	56	uint adsaddr; /* ADMA system address register */
57	char reserved2[100]; /* reserved */	57	char reserved2[100]; /* reserved */
58	uint vendorspec; /* Vendor Specific register */	58	uint vendorspec; /* Vendor Specific register */
59	char reserved3[56]; /* reserved */	59	char reserved3[56]; /* reserved */
60	uint hostver; /* Host controller version register */	60	uint hostver; /* Host controller version register */
61	char reserved4[4]; /* reserved */	61	char reserved4[4]; /* reserved */
62	uint dmaerraddr; /* DMA error address register */	62	uint dmaerraddr; /* DMA error address register */
63	char reserved5[4]; /* reserved */	63	char reserved5[4]; /* reserved */
64	uint dmaerrattr; /* DMA error attribute register */	64	uint dmaerrattr; /* DMA error attribute register */
65	char reserved6[4]; /* reserved */	65	char reserved6[4]; /* reserved */
66	uint hostcapblt2; /* Host controller capabilities register 2 */	66	uint hostcapblt2; /* Host controller capabilities register 2 */
67	char reserved7[8]; /* reserved */	67	char reserved7[8]; /* reserved */
68	uint tcr; /* Tuning control register */	68	uint tcr; /* Tuning control register */
69	char reserved8[28]; /* reserved */	69	char reserved8[28]; /* reserved */
70	uint sddirctl; /* SD direction control register */	70	uint sddirctl; /* SD direction control register */
71	char reserved9[712]; /* reserved */	71	char reserved9[712]; /* reserved */
72	uint scr; /* eSDHC control register */	72	uint scr; /* eSDHC control register */
73	};	73	};
74		74
75	/* Return the XFERTYP flags for a given command and data packet */	75	/* Return the XFERTYP flags for a given command and data packet */
76	static uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)	76	static uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)
77	{	77	{
78	uint xfertyp = 0;	78	uint xfertyp = 0;
79		79
80	if (data) {	80	if (data) {
81	xfertyp \|= XFERTYP_DPSEL;	81	xfertyp \|= XFERTYP_DPSEL;
82	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO	82	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
83	xfertyp \|= XFERTYP_DMAEN;	83	xfertyp \|= XFERTYP_DMAEN;
84	#endif	84	#endif
85	if (data->blocks > 1) {	85	if (data->blocks > 1) {
86	xfertyp \|= XFERTYP_MSBSEL;	86	xfertyp \|= XFERTYP_MSBSEL;
87	xfertyp \|= XFERTYP_BCEN;	87	xfertyp \|= XFERTYP_BCEN;
88	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111	88	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
89	xfertyp \|= XFERTYP_AC12EN;	89	xfertyp \|= XFERTYP_AC12EN;
90	#endif	90	#endif
91	}	91	}
92		92
93	if (data->flags & MMC_DATA_READ)	93	if (data->flags & MMC_DATA_READ)
94	xfertyp \|= XFERTYP_DTDSEL;	94	xfertyp \|= XFERTYP_DTDSEL;
95	}	95	}
96		96
97	if (cmd->resp_type & MMC_RSP_CRC)	97	if (cmd->resp_type & MMC_RSP_CRC)
98	xfertyp \|= XFERTYP_CCCEN;	98	xfertyp \|= XFERTYP_CCCEN;
99	if (cmd->resp_type & MMC_RSP_OPCODE)	99	if (cmd->resp_type & MMC_RSP_OPCODE)
100	xfertyp \|= XFERTYP_CICEN;	100	xfertyp \|= XFERTYP_CICEN;
101	if (cmd->resp_type & MMC_RSP_136)	101	if (cmd->resp_type & MMC_RSP_136)
102	xfertyp \|= XFERTYP_RSPTYP_136;	102	xfertyp \|= XFERTYP_RSPTYP_136;
103	else if (cmd->resp_type & MMC_RSP_BUSY)	103	else if (cmd->resp_type & MMC_RSP_BUSY)
104	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;	104	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;
105	else if (cmd->resp_type & MMC_RSP_PRESENT)	105	else if (cmd->resp_type & MMC_RSP_PRESENT)
106	xfertyp \|= XFERTYP_RSPTYP_48;	106	xfertyp \|= XFERTYP_RSPTYP_48;
107		107
108	#if defined(CONFIG_MX53) \|\| defined(CONFIG_PPC_T4240) \|\| \	108	#if defined(CONFIG_MX53) \|\| defined(CONFIG_PPC_T4240) \|\| \
109	defined(CONFIG_LS102XA) \|\| defined(CONFIG_LS2085A)	109	defined(CONFIG_LS102XA) \|\| defined(CONFIG_LS2085A)
110	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)	110	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
111	xfertyp \|= XFERTYP_CMDTYP_ABORT;	111	xfertyp \|= XFERTYP_CMDTYP_ABORT;
112	#endif	112	#endif
113	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;	113	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;
114	}	114	}
115		115
116	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO	116	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
117	/*	117	/*
118	* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.	118	* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
119	*/	119	*/
120	static void	120	static void
121	esdhc_pio_read_write(struct mmc mmc, struct mmc_data data)	121	esdhc_pio_read_write(struct mmc mmc, struct mmc_data data)
122	{	122	{
123	struct fsl_esdhc_cfg *cfg = mmc->priv;	123	struct fsl_esdhc_cfg *cfg = mmc->priv;
124	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	124	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
125	uint blocks;	125	uint blocks;
126	char *buffer;	126	char *buffer;
127	uint databuf;	127	uint databuf;
128	uint size;	128	uint size;
129	uint irqstat;	129	uint irqstat;
130	uint timeout;	130	uint timeout;
131		131
132	if (data->flags & MMC_DATA_READ) {	132	if (data->flags & MMC_DATA_READ) {
133	blocks = data->blocks;	133	blocks = data->blocks;
134	buffer = data->dest;	134	buffer = data->dest;
135	while (blocks) {	135	while (blocks) {
136	timeout = PIO_TIMEOUT;	136	timeout = PIO_TIMEOUT;
137	size = data->blocksize;	137	size = data->blocksize;
138	irqstat = esdhc_read32(&regs->irqstat);	138	irqstat = esdhc_read32(&regs->irqstat);
139	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)	139	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
140	&& --timeout);	140	&& --timeout);
141	if (timeout <= 0) {	141	if (timeout <= 0) {
142	printf("\nData Read Failed in PIO Mode.");	142	printf("\nData Read Failed in PIO Mode.");
143	return;	143	return;
144	}	144	}
145	while (size && (!(irqstat & IRQSTAT_TC))) {	145	while (size && (!(irqstat & IRQSTAT_TC))) {
146	udelay(100); /* Wait before last byte transfer complete */	146	udelay(100); /* Wait before last byte transfer complete */
147	irqstat = esdhc_read32(&regs->irqstat);	147	irqstat = esdhc_read32(&regs->irqstat);
148	databuf = in_le32(&regs->datport);	148	databuf = in_le32(&regs->datport);
149	((uint )buffer) = databuf;	149	((uint )buffer) = databuf;
150	buffer += 4;	150	buffer += 4;
151	size -= 4;	151	size -= 4;
152	}	152	}
153	blocks--;	153	blocks--;
154	}	154	}
155	} else {	155	} else {
156	blocks = data->blocks;	156	blocks = data->blocks;
157	buffer = (char *)data->src;	157	buffer = (char *)data->src;
158	while (blocks) {	158	while (blocks) {
159	timeout = PIO_TIMEOUT;	159	timeout = PIO_TIMEOUT;
160	size = data->blocksize;	160	size = data->blocksize;
161	irqstat = esdhc_read32(&regs->irqstat);	161	irqstat = esdhc_read32(&regs->irqstat);
162	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)	162	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
163	&& --timeout);	163	&& --timeout);
164	if (timeout <= 0) {	164	if (timeout <= 0) {
165	printf("\nData Write Failed in PIO Mode.");	165	printf("\nData Write Failed in PIO Mode.");
166	return;	166	return;
167	}	167	}
168	while (size && (!(irqstat & IRQSTAT_TC))) {	168	while (size && (!(irqstat & IRQSTAT_TC))) {
169	udelay(100); /* Wait before last byte transfer complete */	169	udelay(100); /* Wait before last byte transfer complete */
170	databuf = ((uint )buffer);	170	databuf = ((uint )buffer);
171	buffer += 4;	171	buffer += 4;
172	size -= 4;	172	size -= 4;
173	irqstat = esdhc_read32(&regs->irqstat);	173	irqstat = esdhc_read32(&regs->irqstat);
174	out_le32(&regs->datport, databuf);	174	out_le32(&regs->datport, databuf);
175	}	175	}
176	blocks--;	176	blocks--;
177	}	177	}
178	}	178	}
179	}	179	}
180	#endif	180	#endif
181		181
182	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)	182	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)
183	{	183	{
184	int timeout;	184	int timeout;
185	struct fsl_esdhc_cfg *cfg = mmc->priv;	185	struct fsl_esdhc_cfg *cfg = mmc->priv;
186	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	186	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
187	#ifdef CONFIG_LS2085A	187	#ifdef CONFIG_LS2085A
188	dma_addr_t addr;	188	dma_addr_t addr;
189	#endif	189	#endif
190	uint wml_value;	190	uint wml_value;
191		191
192	wml_value = data->blocksize/4;	192	wml_value = data->blocksize/4;
193		193
194	if (data->flags & MMC_DATA_READ) {	194	if (data->flags & MMC_DATA_READ) {
195	if (wml_value > WML_RD_WML_MAX)	195	if (wml_value > WML_RD_WML_MAX)
196	wml_value = WML_RD_WML_MAX_VAL;	196	wml_value = WML_RD_WML_MAX_VAL;
197		197
198	esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);	198	esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
199	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO	199	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
200	#ifdef CONFIG_LS2085A	200	#ifdef CONFIG_LS2085A
201	addr = virt_to_phys((void *)(data->dest));	201	addr = virt_to_phys((void *)(data->dest));
202	if (upper_32_bits(addr))	202	if (upper_32_bits(addr))
203	printf("Error found for upper 32 bits\n");	203	printf("Error found for upper 32 bits\n");
204	else	204	else
205	esdhc_write32(&regs->dsaddr, lower_32_bits(addr));	205	esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
206	#else	206	#else
207	esdhc_write32(&regs->dsaddr, (u32)data->dest);	207	esdhc_write32(&regs->dsaddr, (u32)data->dest);
208	#endif	208	#endif
209	#endif	209	#endif
210	} else {	210	} else {
211	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO	211	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
212	flush_dcache_range((ulong)data->src,	212	flush_dcache_range((ulong)data->src,
213	(ulong)data->src+data->blocks	213	(ulong)data->src+data->blocks
214	*data->blocksize);	214	*data->blocksize);
215	#endif	215	#endif
216	if (wml_value > WML_WR_WML_MAX)	216	if (wml_value > WML_WR_WML_MAX)
217	wml_value = WML_WR_WML_MAX_VAL;	217	wml_value = WML_WR_WML_MAX_VAL;
218	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {	218	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
219	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");	219	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
220	return TIMEOUT;	220	return TIMEOUT;
221	}	221	}
222		222
223	esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,	223	esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
224	wml_value << 16);	224	wml_value << 16);
225	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO	225	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
226	#ifdef CONFIG_LS2085A	226	#ifdef CONFIG_LS2085A
227	addr = virt_to_phys((void *)(data->src));	227	addr = virt_to_phys((void *)(data->src));
228	if (upper_32_bits(addr))	228	if (upper_32_bits(addr))
229	printf("Error found for upper 32 bits\n");	229	printf("Error found for upper 32 bits\n");
230	else	230	else
231	esdhc_write32(&regs->dsaddr, lower_32_bits(addr));	231	esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
232	#else	232	#else
233	esdhc_write32(&regs->dsaddr, (u32)data->src);	233	esdhc_write32(&regs->dsaddr, (u32)data->src);
234	#endif	234	#endif
235	#endif	235	#endif
236	}	236	}
237		237
238	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);	238	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);
239		239
240	/* Calculate the timeout period for data transactions */	240	/* Calculate the timeout period for data transactions */
241	/*	241	/*
242	* 1)Timeout period = (2^(timeout+13)) SD Clock cycles	242	* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
243	* 2)Timeout period should be minimum 0.250sec as per SD Card spec	243	* 2)Timeout period should be minimum 0.250sec as per SD Card spec
244	* So, Number of SD Clock cycles for 0.25sec should be minimum	244	* So, Number of SD Clock cycles for 0.25sec should be minimum
245	* (SD Clock/sec * 0.25 sec) SD Clock cycles	245	* (SD Clock/sec * 0.25 sec) SD Clock cycles
246	* = (mmc->clock * 1/4) SD Clock cycles	246	* = (mmc->clock * 1/4) SD Clock cycles
247	* As 1) >= 2)	247	* As 1) >= 2)
248	* => (2^(timeout+13)) >= mmc->clock * 1/4	248	* => (2^(timeout+13)) >= mmc->clock * 1/4
249	* Taking log2 both the sides	249	* Taking log2 both the sides
250	* => timeout + 13 >= log2(mmc->clock/4)	250	* => timeout + 13 >= log2(mmc->clock/4)
251	* Rounding up to next power of 2	251	* Rounding up to next power of 2
252	* => timeout + 13 = log2(mmc->clock/4) + 1	252	* => timeout + 13 = log2(mmc->clock/4) + 1
253	* => timeout + 13 = fls(mmc->clock/4)	253	* => timeout + 13 = fls(mmc->clock/4)
254	*/	254	*/
255	timeout = fls(mmc->clock/4);	255	timeout = fls(mmc->clock/4);
256	timeout -= 13;	256	timeout -= 13;
257		257
258	if (timeout > 14)	258	if (timeout > 14)
259	timeout = 14;	259	timeout = 14;
260		260
261	if (timeout < 0)	261	if (timeout < 0)
262	timeout = 0;	262	timeout = 0;
263		263
264	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001	264	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
265	if ((timeout == 4) \|\| (timeout == 8) \|\| (timeout == 12))	265	if ((timeout == 4) \|\| (timeout == 8) \|\| (timeout == 12))
266	timeout++;	266	timeout++;
267	#endif	267	#endif
268		268
269	#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE	269	#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
270	timeout = 0xE;	270	timeout = 0xE;
271	#endif	271	#endif
272	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);	272	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
273		273
274	return 0;	274	return 0;
275	}	275	}
276		276
277	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO	277	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
278	static void check_and_invalidate_dcache_range	278	static void check_and_invalidate_dcache_range
279	(struct mmc_cmd *cmd,	279	(struct mmc_cmd *cmd,
280	struct mmc_data *data) {	280	struct mmc_data *data) {
281	#ifdef CONFIG_LS2085A	281	#ifdef CONFIG_LS2085A
282	unsigned start = 0;	282	unsigned start = 0;
283	#else	283	#else
284	unsigned start = (unsigned)data->dest ;	284	unsigned start = (unsigned)data->dest ;
285	#endif	285	#endif
286	unsigned size = roundup(ARCH_DMA_MINALIGN,	286	unsigned size = roundup(ARCH_DMA_MINALIGN,
287	data->blocks*data->blocksize);	287	data->blocks*data->blocksize);
288	unsigned end = start+size ;	288	unsigned end = start+size ;
289	#ifdef CONFIG_LS2085A	289	#ifdef CONFIG_LS2085A
290	dma_addr_t addr;	290	dma_addr_t addr;
291		291
292	addr = virt_to_phys((void *)(data->dest));	292	addr = virt_to_phys((void *)(data->dest));
293	if (upper_32_bits(addr))	293	if (upper_32_bits(addr))
294	printf("Error found for upper 32 bits\n");	294	printf("Error found for upper 32 bits\n");
295	else	295	else
296	start = lower_32_bits(addr);	296	start = lower_32_bits(addr);
297	#endif	297	#endif
298	invalidate_dcache_range(start, end);	298	invalidate_dcache_range(start, end);
299	}	299	}
300	#endif	300	#endif
301		301
302	/*	302	/*
303	* Sends a command out on the bus. Takes the mmc pointer,	303	* Sends a command out on the bus. Takes the mmc pointer,
304	* a command pointer, and an optional data pointer.	304	* a command pointer, and an optional data pointer.
305	*/	305	*/
306	static int	306	static int
307	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)	307	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
308	{	308	{
309	int err = 0;	309	int err = 0;
310	uint xfertyp;	310	uint xfertyp;
311	uint irqstat;	311	uint irqstat;
312	struct fsl_esdhc_cfg *cfg = mmc->priv;	312	struct fsl_esdhc_cfg *cfg = mmc->priv;
313	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	313	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
314		314
315	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111	315	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
316	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)	316	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
317	return 0;	317	return 0;
318	#endif	318	#endif
319		319
320	esdhc_write32(&regs->irqstat, -1);	320	esdhc_write32(&regs->irqstat, -1);
321		321
322	sync();	322	sync();
323		323
324	/* Wait for the bus to be idle */	324	/* Wait for the bus to be idle */
325	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|	325	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|
326	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))	326	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
327	;	327	;
328		328
329	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)	329	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
330	;	330	;
331		331
332	/* Wait at least 8 SD clock cycles before the next command */	332	/* Wait at least 8 SD clock cycles before the next command */
333	/*	333	/*
334	* Note: This is way more than 8 cycles, but 1ms seems to	334	* Note: This is way more than 8 cycles, but 1ms seems to
335	* resolve timing issues with some cards	335	* resolve timing issues with some cards
336	*/	336	*/
337	udelay(1000);	337	udelay(1000);
338		338
339	/* Set up for a data transfer if we have one */	339	/* Set up for a data transfer if we have one */
340	if (data) {	340	if (data) {
341	err = esdhc_setup_data(mmc, data);	341	err = esdhc_setup_data(mmc, data);
342	if(err)	342	if(err)
343	return err;	343	return err;
344	}	344	}
345		345
346	/* Figure out the transfer arguments */	346	/* Figure out the transfer arguments */
347	xfertyp = esdhc_xfertyp(cmd, data);	347	xfertyp = esdhc_xfertyp(cmd, data);
348		348
349	/* Mask all irqs */	349	/* Mask all irqs */
350	esdhc_write32(&regs->irqsigen, 0);	350	esdhc_write32(&regs->irqsigen, 0);
351		351
352	/* Send the command */	352	/* Send the command */
353	esdhc_write32(&regs->cmdarg, cmd->cmdarg);	353	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
354	#if defined(CONFIG_FSL_USDHC)	354	#if defined(CONFIG_FSL_USDHC)
355	esdhc_write32(&regs->mixctrl,	355	esdhc_write32(&regs->mixctrl,
356	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) \| (xfertyp & 0x7F)	356	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) \| (xfertyp & 0x7F)
357	\| (mmc->ddr_mode ? XFERTYP_DDREN : 0));	357	\| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
358	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);	358	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
359	#else	359	#else
360	esdhc_write32(&regs->xfertyp, xfertyp);	360	esdhc_write32(&regs->xfertyp, xfertyp);
361	#endif	361	#endif
362		362
363	/* Wait for the command to complete */	363	/* Wait for the command to complete */
364	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC \| IRQSTAT_CTOE)))	364	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC \| IRQSTAT_CTOE)))
365	;	365	;
366		366
367	irqstat = esdhc_read32(&regs->irqstat);	367	irqstat = esdhc_read32(&regs->irqstat);
368		368
369	if (irqstat & CMD_ERR) {	369	if (irqstat & CMD_ERR) {
370	err = COMM_ERR;	370	err = COMM_ERR;
371	goto out;	371	goto out;
372	}	372	}
373		373
374	if (irqstat & IRQSTAT_CTOE) {	374	if (irqstat & IRQSTAT_CTOE) {
375	err = TIMEOUT;	375	err = TIMEOUT;
376	goto out;	376	goto out;
377	}	377	}
378		378
379	/* Switch voltage to 1.8V if CMD11 succeeded */	379	/* Switch voltage to 1.8V if CMD11 succeeded */
380	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {	380	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
381	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);	381	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
382		382
383	printf("Run CMD11 1.8V switch\n");	383	printf("Run CMD11 1.8V switch\n");
384	/* Sleep for 5 ms - max time for card to switch to 1.8V */	384	/* Sleep for 5 ms - max time for card to switch to 1.8V */
385	udelay(5000);	385	udelay(5000);
386	}	386	}
387		387
388	/* Workaround for ESDHC errata ENGcm03648 */	388	/* Workaround for ESDHC errata ENGcm03648 */
389	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {	389	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
390	int timeout = 2500;	390	int timeout = 2500;
391		391
392	/* Poll on DATA0 line for cmd with busy signal for 250 ms */	392	/* Poll on DATA0 line for cmd with busy signal for 250 ms */
393	while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &	393	while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
394	PRSSTAT_DAT0)) {	394	PRSSTAT_DAT0)) {
395	udelay(100);	395	udelay(100);
396	timeout--;	396	timeout--;
397	}	397	}
398		398
399	if (timeout <= 0) {	399	if (timeout <= 0) {
400	printf("Timeout waiting for DAT0 to go high!\n");	400	printf("Timeout waiting for DAT0 to go high!\n");
401	err = TIMEOUT;	401	err = TIMEOUT;
402	goto out;	402	goto out;
403	}	403	}
404	}	404	}
405		405
406	/* Copy the response to the response buffer */	406	/* Copy the response to the response buffer */
407	if (cmd->resp_type & MMC_RSP_136) {	407	if (cmd->resp_type & MMC_RSP_136) {
408	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;	408	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
409		409
410	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);	410	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
411	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);	411	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
412	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);	412	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
413	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);	413	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
414	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);	414	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);
415	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);	415	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);
416	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);	416	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);
417	cmd->response[3] = (cmdrsp0 << 8);	417	cmd->response[3] = (cmdrsp0 << 8);
418	} else	418	} else
419	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);	419	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
420		420
421	/* Wait until all of the blocks are transferred */	421	/* Wait until all of the blocks are transferred */
422	if (data) {	422	if (data) {
423	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO	423	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
424	esdhc_pio_read_write(mmc, data);	424	esdhc_pio_read_write(mmc, data);
425	#else	425	#else
426	do {	426	do {
427	irqstat = esdhc_read32(&regs->irqstat);	427	irqstat = esdhc_read32(&regs->irqstat);
428		428
429	if (irqstat & IRQSTAT_DTOE) {	429	if (irqstat & IRQSTAT_DTOE) {
430	err = TIMEOUT;	430	err = TIMEOUT;
431	goto out;	431	goto out;
432	}	432	}
433		433
434	if (irqstat & DATA_ERR) {	434	if (irqstat & DATA_ERR) {
435	err = COMM_ERR;	435	err = COMM_ERR;
436	goto out;	436	goto out;
437	}	437	}
438	} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);	438	} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
439		439
440	if (data->flags & MMC_DATA_READ)	440	if (data->flags & MMC_DATA_READ)
441	check_and_invalidate_dcache_range(cmd, data);	441	check_and_invalidate_dcache_range(cmd, data);
442	#endif	442	#endif
443	}	443	}
444		444
445	out:	445	out:
446	/* Reset CMD and DATA portions on error */	446	/* Reset CMD and DATA portions on error */
447	if (err) {	447	if (err) {
448	esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) \|	448	esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) \|
449	SYSCTL_RSTC);	449	SYSCTL_RSTC);
450	while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)	450	while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
451	;	451	;
452		452
453	if (data) {	453	if (data) {
454	esdhc_write32(&regs->sysctl,	454	esdhc_write32(&regs->sysctl,
455	esdhc_read32(&regs->sysctl) \|	455	esdhc_read32(&regs->sysctl) \|
456	SYSCTL_RSTD);	456	SYSCTL_RSTD);
457	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))	457	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
458	;	458	;
459	}	459	}
460		460
461	/* If this was CMD11, then notify that power cycle is needed */	461	/* If this was CMD11, then notify that power cycle is needed */
462	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)	462	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
463	printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");	463	printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
464	}	464	}
465		465
466	esdhc_write32(&regs->irqstat, -1);	466	esdhc_write32(&regs->irqstat, -1);
467		467
468	return err;	468	return err;
469	}	469	}
470		470
471	static void set_sysctl(struct mmc *mmc, uint clock)	471	static void set_sysctl(struct mmc *mmc, uint clock)
472	{	472	{
473	int div, pre_div;	473	int div, pre_div;
474	struct fsl_esdhc_cfg *cfg = mmc->priv;	474	struct fsl_esdhc_cfg *cfg = mmc->priv;
475	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	475	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
476	int sdhc_clk = cfg->sdhc_clk;	476	int sdhc_clk = cfg->sdhc_clk;
477	uint clk;	477	uint clk;
478		478
479	if (clock < mmc->cfg->f_min)	479	if (clock < mmc->cfg->f_min)
480	clock = mmc->cfg->f_min;	480	clock = mmc->cfg->f_min;
481		481
482	if (sdhc_clk / 16 > clock) {	482	if (sdhc_clk / 16 > clock) {
483	for (pre_div = 2; pre_div < 256; pre_div *= 2)	483	for (pre_div = 2; pre_div < 256; pre_div *= 2)
484	if ((sdhc_clk / pre_div) <= (clock * 16))	484	if ((sdhc_clk / pre_div) <= (clock * 16))
485	break;	485	break;
486	} else	486	} else
487	pre_div = 2;	487	pre_div = 2;
488		488
489	for (div = 1; div <= 16; div++)	489	for (div = 1; div <= 16; div++)
490	if ((sdhc_clk / (div * pre_div)) <= clock)	490	if ((sdhc_clk / (div * pre_div)) <= clock)
491	break;	491	break;
492		492
493	pre_div >>= mmc->ddr_mode ? 2 : 1;	493	pre_div >>= mmc->ddr_mode ? 2 : 1;
494	div -= 1;	494	div -= 1;
495		495
496	clk = (pre_div << 8) \| (div << 4);	496	clk = (pre_div << 8) \| (div << 4);
497		497
498	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);	498	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
499		499
500	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);	500	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
501		501
502	udelay(10000);	502	udelay(10000);
503		503
504	clk = SYSCTL_PEREN \| SYSCTL_CKEN;	504	clk = SYSCTL_PEREN \| SYSCTL_CKEN;
505		505
506	esdhc_setbits32(&regs->sysctl, clk);	506	esdhc_setbits32(&regs->sysctl, clk);
507	}	507	}
508		508
509	static void esdhc_set_ios(struct mmc *mmc)	509	static void esdhc_set_ios(struct mmc *mmc)
510	{	510	{
511	struct fsl_esdhc_cfg *cfg = mmc->priv;	511	struct fsl_esdhc_cfg *cfg = mmc->priv;
512	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	512	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
513		513
514	/* Set the clock speed */	514	/* Set the clock speed */
515	set_sysctl(mmc, mmc->clock);	515	set_sysctl(mmc, mmc->clock);
516		516
517	/* Set the bus width */	517	/* Set the bus width */
518	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);	518	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);
519		519
520	if (mmc->bus_width == 4)	520	if (mmc->bus_width == 4)
521	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);	521	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
522	else if (mmc->bus_width == 8)	522	else if (mmc->bus_width == 8)
523	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);	523	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
524		524
525	}	525	}
526		526
527	static int esdhc_init(struct mmc *mmc)	527	static int esdhc_init(struct mmc *mmc)
528	{	528	{
529	struct fsl_esdhc_cfg *cfg = mmc->priv;	529	struct fsl_esdhc_cfg *cfg = mmc->priv;
530	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	530	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
531	int timeout = 1000;	531	int timeout = 1000;
532		532
533	/* Reset the entire host controller */	533	/* Reset the entire host controller */
534	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);	534	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
535		535
536	/* Wait until the controller is available */	536	/* Wait until the controller is available */
537	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)	537	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
538	udelay(1000);	538	udelay(1000);
539		539
540	#ifndef ARCH_MXC	540	#ifndef ARCH_MXC
541	/* Enable cache snooping */	541	/* Enable cache snooping */
542	esdhc_write32(&regs->scr, 0x00000040);	542	esdhc_write32(&regs->scr, 0x00000040);
543	#endif	543	#endif
544		544
545	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);	545	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);
546		546
547	/* Set the initial clock speed */	547	/* Set the initial clock speed */
548	mmc_set_clock(mmc, 400000);	548	mmc_set_clock(mmc, 400000);
549		549
550	/* Disable the BRR and BWR bits in IRQSTAT */	550	/* Disable the BRR and BWR bits in IRQSTAT */
551	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);	551	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);
552		552
553	/* Put the PROCTL reg back to the default */	553	/* Put the PROCTL reg back to the default */
554	esdhc_write32(&regs->proctl, PROCTL_INIT);	554	esdhc_write32(&regs->proctl, PROCTL_INIT);
555		555
556	/* Set timout to the maximum value */	556	/* Set timout to the maximum value */
557	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);	557	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
558		558
559	#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT	559	#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
560	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);	560	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
561	#endif	561	#endif
562		562
563	return 0;	563	return 0;
564	}	564	}
565		565
566	static int esdhc_getcd(struct mmc *mmc)	566	static int esdhc_getcd(struct mmc *mmc)
567	{	567	{
568	struct fsl_esdhc_cfg *cfg = mmc->priv;	568	struct fsl_esdhc_cfg *cfg = mmc->priv;
569	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;	569	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
570	int timeout = 1000;	570	int timeout = 1000;
571		571
572	#ifdef CONFIG_ESDHC_DETECT_QUIRK	572	#ifdef CONFIG_ESDHC_DETECT_QUIRK
573	if (CONFIG_ESDHC_DETECT_QUIRK)	573	if (CONFIG_ESDHC_DETECT_QUIRK)
574	return 1;	574	return 1;
575	#endif	575	#endif
576	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)	576	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
577	udelay(1000);	577	udelay(1000);
578		578
579	return timeout > 0;	579	return timeout > 0;
580	}	580	}
581		581
582	static void esdhc_reset(struct fsl_esdhc *regs)	582	static void esdhc_reset(struct fsl_esdhc *regs)
583	{	583	{
584	unsigned long timeout = 100; /* wait max 100 ms */	584	unsigned long timeout = 100; /* wait max 100 ms */
585		585
586	/* reset the controller */	586	/* reset the controller */
587	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);	587	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
588		588
589	/* hardware clears the bit when it is done */	589	/* hardware clears the bit when it is done */
590	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)	590	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
591	udelay(1000);	591	udelay(1000);
592	if (!timeout)	592	if (!timeout)
593	printf("MMC/SD: Reset never completed.\n");	593	printf("MMC/SD: Reset never completed.\n");
594	}	594	}
595		595
596	static const struct mmc_ops esdhc_ops = {	596	static const struct mmc_ops esdhc_ops = {
597	.send_cmd = esdhc_send_cmd,	597	.send_cmd = esdhc_send_cmd,
598	.set_ios = esdhc_set_ios,	598	.set_ios = esdhc_set_ios,
599	.init = esdhc_init,	599	.init = esdhc_init,
600	.getcd = esdhc_getcd,	600	.getcd = esdhc_getcd,
601	};	601	};
602		602
603	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)	603	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
604	{	604	{
605	struct fsl_esdhc *regs;	605	struct fsl_esdhc *regs;
606	struct mmc *mmc;	606	struct mmc *mmc;
607	u32 caps, voltage_caps;	607	u32 caps, voltage_caps;
608		608
609	if (!cfg)	609	if (!cfg)
610	return -1;	610	return -1;
611		611
612	regs = (struct fsl_esdhc *)cfg->esdhc_base;	612	regs = (struct fsl_esdhc *)cfg->esdhc_base;
613		613
614	/* First reset the eSDHC controller */	614	/* First reset the eSDHC controller */
615	esdhc_reset(regs);	615	esdhc_reset(regs);
616		616
617	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN \| SYSCTL_HCKEN	617	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN \| SYSCTL_HCKEN
618	\| SYSCTL_IPGEN \| SYSCTL_CKEN);	618	\| SYSCTL_IPGEN \| SYSCTL_CKEN);
619		619
620	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);	620	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
621	memset(&cfg->cfg, 0, sizeof(cfg->cfg));	621	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
622		622
623	voltage_caps = 0;	623	voltage_caps = 0;
624	caps = esdhc_read32(&regs->hostcapblt);	624	caps = esdhc_read32(&regs->hostcapblt);
625		625
626	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135	626	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
627	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS \|	627	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS \|
628	ESDHC_HOSTCAPBLT_VS18 \| ESDHC_HOSTCAPBLT_VS30);	628	ESDHC_HOSTCAPBLT_VS18 \| ESDHC_HOSTCAPBLT_VS30);
629	#endif	629	#endif
630		630
631	/* T4240 host controller capabilities register should have VS33 bit */	631	/* T4240 host controller capabilities register should have VS33 bit */
632	#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33	632	#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
633	caps = caps \| ESDHC_HOSTCAPBLT_VS33;	633	caps = caps \| ESDHC_HOSTCAPBLT_VS33;
634	#endif	634	#endif
635		635
636	if (caps & ESDHC_HOSTCAPBLT_VS18)	636	if (caps & ESDHC_HOSTCAPBLT_VS18)
637	voltage_caps \|= MMC_VDD_165_195;	637	voltage_caps \|= MMC_VDD_165_195;
638	if (caps & ESDHC_HOSTCAPBLT_VS30)	638	if (caps & ESDHC_HOSTCAPBLT_VS30)
639	voltage_caps \|= MMC_VDD_29_30 \| MMC_VDD_30_31;	639	voltage_caps \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
640	if (caps & ESDHC_HOSTCAPBLT_VS33)	640	if (caps & ESDHC_HOSTCAPBLT_VS33)
641	voltage_caps \|= MMC_VDD_32_33 \| MMC_VDD_33_34;	641	voltage_caps \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
642		642
643	cfg->cfg.name = "FSL_SDHC";	643	cfg->cfg.name = "FSL_SDHC";
644	cfg->cfg.ops = &esdhc_ops;	644	cfg->cfg.ops = &esdhc_ops;
645	#ifdef CONFIG_SYS_SD_VOLTAGE	645	#ifdef CONFIG_SYS_SD_VOLTAGE
646	cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;	646	cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
647	#else	647	#else
648	cfg->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;	648	cfg->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
649	#endif	649	#endif
650	if ((cfg->cfg.voltages & voltage_caps) == 0) {	650	if ((cfg->cfg.voltages & voltage_caps) == 0) {
651	printf("voltage not supported by controller\n");	651	printf("voltage not supported by controller\n");
652	return -1;	652	return -1;
653	}	653	}
654		654
655	cfg->cfg.host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT \| MMC_MODE_HC;	655	cfg->cfg.host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT;
656	#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE	656	#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
657	cfg->cfg.host_caps \|= MMC_MODE_DDR_52MHz;	657	cfg->cfg.host_caps \|= MMC_MODE_DDR_52MHz;
658	#endif	658	#endif
659		659
660	if (cfg->max_bus_width > 0) {	660	if (cfg->max_bus_width > 0) {
661	if (cfg->max_bus_width < 8)	661	if (cfg->max_bus_width < 8)
662	cfg->cfg.host_caps &= ~MMC_MODE_8BIT;	662	cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
663	if (cfg->max_bus_width < 4)	663	if (cfg->max_bus_width < 4)
664	cfg->cfg.host_caps &= ~MMC_MODE_4BIT;	664	cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
665	}	665	}
666		666
667	if (caps & ESDHC_HOSTCAPBLT_HSS)	667	if (caps & ESDHC_HOSTCAPBLT_HSS)
668	cfg->cfg.host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;	668	cfg->cfg.host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
669		669
670	#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK	670	#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
671	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)	671	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
672	cfg->cfg.host_caps &= ~MMC_MODE_8BIT;	672	cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
673	#endif	673	#endif
674		674
675	cfg->cfg.f_min = 400000;	675	cfg->cfg.f_min = 400000;
676	cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);	676	cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
677		677
678	cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;	678	cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
679		679
680	mmc = mmc_create(&cfg->cfg, cfg);	680	mmc = mmc_create(&cfg->cfg, cfg);
681	if (mmc == NULL)	681	if (mmc == NULL)
682	return -1;	682	return -1;
683		683
684	return 0;	684	return 0;
685	}	685	}
686		686
687	int fsl_esdhc_mmc_init(bd_t *bis)	687	int fsl_esdhc_mmc_init(bd_t *bis)
688	{	688	{
689	struct fsl_esdhc_cfg *cfg;	689	struct fsl_esdhc_cfg *cfg;
690		690
691	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);	691	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
692	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;	692	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
693	cfg->sdhc_clk = gd->arch.sdhc_clk;	693	cfg->sdhc_clk = gd->arch.sdhc_clk;
694	return fsl_esdhc_initialize(bis, cfg);	694	return fsl_esdhc_initialize(bis, cfg);
695	}	695	}
696		696
697	#ifdef CONFIG_OF_LIBFDT	697	#ifdef CONFIG_OF_LIBFDT
698	void fdt_fixup_esdhc(void blob, bd_t bd)	698	void fdt_fixup_esdhc(void blob, bd_t bd)
699	{	699	{
700	const char *compat = "fsl,esdhc";	700	const char *compat = "fsl,esdhc";
701		701
702	#ifdef CONFIG_FSL_ESDHC_PIN_MUX	702	#ifdef CONFIG_FSL_ESDHC_PIN_MUX
703	if (!hwconfig("esdhc")) {	703	if (!hwconfig("esdhc")) {
704	do_fixup_by_compat(blob, compat, "status", "disabled",	704	do_fixup_by_compat(blob, compat, "status", "disabled",
705	8 + 1, 1);	705	8 + 1, 1);
706	return;	706	return;
707	}	707	}
708	#endif	708	#endif
709		709
710	do_fixup_by_compat_u32(blob, compat, "clock-frequency",	710	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
711	gd->arch.sdhc_clk, 1);	711	gd->arch.sdhc_clk, 1);
712		712
713	do_fixup_by_compat(blob, compat, "status", "okay",	713	do_fixup_by_compat(blob, compat, "status", "okay",
714	4 + 1, 1);	714	4 + 1, 1);
715	}	715	}
716	#endif	716	#endif
717		717

drivers/mmc/kona_sdhci.c

Diff comments View file @ 5a20397

 /*
  * Copyright 2013 Broadcom Corporation.
  *
  * SPDX-License-Identifier:      GPL-2.0+
  */
 #include <common.h>
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/errno.h>
 #include <asm/kona-common/clk.h>
 #define SDHCI_CORECTRL_OFFSET		0x00008000
 #define SDHCI_CORECTRL_EN		0x01
 #define SDHCI_CORECTRL_RESET		0x02
 #define SDHCI_CORESTAT_OFFSET		0x00008004
 #define SDHCI_CORESTAT_CD_SW		0x01
 #define SDHCI_COREIMR_OFFSET		0x00008008
 #define SDHCI_COREIMR_IP		0x01
 static int init_kona_mmc_core(struct sdhci_host *host)
 {
 	unsigned int mask;
 	unsigned int timeout;
 	if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
 		printf("%s: sd host controller reset error\n", __func__);
 		return 1;
 	}
 	/* For kona a hardware reset before anything else. */
 	mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET;
 	sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
 	/* Wait max 100 ms */
 	timeout = 1000;
 	do {
 		if (timeout == 0) {
 			printf("%s: reset timeout error\n", __func__);
 			return 1;
 		}
 		timeout--;
 		udelay(100);
 	} while (0 ==
 		 (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) &
 		  SDHCI_CORECTRL_RESET));
 	/* Clear the reset bit. */
 	mask = mask & ~SDHCI_CORECTRL_RESET;
 	sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
 	/* Enable AHB clock */
 	mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET);
 	sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET);
 	/* Enable interrupts */
 	sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET);
 	/* Make sure Card is detected in controller */
 	mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET);
 	sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET);
 	/* Wait max 100 ms */
 	timeout = 1000;
 	while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 		if (timeout == 0) {
 			printf("%s: CARD DETECT timeout error\n", __func__);
 			return 1;
 		}
 		timeout--;
 		udelay(100);
 	}
 	return 0;
 }
 int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
 {
 	int ret = 0;
 	u32 max_clk;
 	void *reg_base;
 	struct sdhci_host *host = NULL;
 	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
 	if (!host) {
 		printf("%s: sdhci host malloc fail!\n", __func__);
 		return -ENOMEM;
 	}
 	switch (dev_index) {
 	case 0:
 		reg_base = (void *)CONFIG_SYS_SDIO_BASE0;
 		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK,
 				      &max_clk);
 		break;
 	case 1:
 		reg_base = (void *)CONFIG_SYS_SDIO_BASE1;
 		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK,
 				      &max_clk);
 		break;
 	case 2:
 		reg_base = (void *)CONFIG_SYS_SDIO_BASE2;
 		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK,
 				      &max_clk);
 		break;
 	case 3:
 		reg_base = (void *)CONFIG_SYS_SDIO_BASE3;
 		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK,
 				      &max_clk);
 		break;
 	default:
 		printf("%s: sdio dev index %d not supported\n",
 		       __func__, dev_index);
 		ret = -EINVAL;
 	}
 	if (ret) {
 		free(host);
 		return ret;
 	}
 	host->name = "kona-sdhci";
 	host->ioaddr = reg_base;
 	host->quirks = quirks;
-	host->host_caps = MMC_MODE_HC;
 	if (init_kona_mmc_core(host)) {
 		free(host);
 		return -EINVAL;
 	}
 	if (quirks & SDHCI_QUIRK_REG32_RW)
 		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 	else
 		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 	add_sdhci(host, max_clk, min_clk);
 	return ret;
 }

drivers/mmc/mmc.c

Diff comments View file @ 5a20397

 /*
  * Copyright 2008, Freescale Semiconductor, Inc
  * Andy Fleming
  *
  * Based vaguely on the Linux code
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
 #include <common.h>
 #include <command.h>
 #include <errno.h>
 #include <mmc.h>
 #include <part.h>
 #include <malloc.h>
 #include <linux/list.h>
 #include <div64.h>
 #include "mmc_private.h"
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
 }
 int mmc_getwp(struct mmc *mmc)
 {
 	int wp;
 	wp = board_mmc_getwp(mmc);
 	if (wp < 0) {
 		if (mmc->cfg->ops->getwp)
 			wp = mmc->cfg->ops->getwp(mmc);
 		else
 			wp = 0;
 	}
 	return wp;
 }
 __weak int board_mmc_getcd(struct mmc *mmc)
 {
 	return -1;
 }
 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
 	int ret;
 #ifdef CONFIG_MMC_TRACE
 	int i;
 	u8 *ptr;
 	printf("CMD_SEND:%d\n", cmd->cmdidx);
 	printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
 	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 	switch (cmd->resp_type) {
 		case MMC_RSP_NONE:
 			printf("\t\tMMC_RSP_NONE\n");
 			break;
 		case MMC_RSP_R1:
 			printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
 				cmd->response[0]);
 			break;
 		case MMC_RSP_R1b:
 			printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
 				cmd->response[0]);
 			break;
 		case MMC_RSP_R2:
 			printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
 				cmd->response[0]);
 			printf("\t\t          \t\t 0x%08X \n",
 				cmd->response[1]);
 			printf("\t\t          \t\t 0x%08X \n",
 				cmd->response[2]);
 			printf("\t\t          \t\t 0x%08X \n",
 				cmd->response[3]);
 			printf("\n");
 			printf("\t\t\t\t\tDUMPING DATA\n");
 			for (i = 0; i < 4; i++) {
 				int j;
 				printf("\t\t\t\t\t%03d - ", i*4);
 				ptr = (u8 *)&cmd->response[i];
 				ptr += 3;
 				for (j = 0; j < 4; j++)
 					printf("%02X ", *ptr--);
 				printf("\n");
 			}
 			break;
 		case MMC_RSP_R3:
 			printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
 				cmd->response[0]);
 			break;
 		default:
 			printf("\t\tERROR MMC rsp not supported\n");
 			break;
 	}
 #else
 	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 #endif
 	return ret;
 }
 int mmc_send_status(struct mmc *mmc, int timeout)
 {
 	struct mmc_cmd cmd;
 	int err, retries = 5;
 #ifdef CONFIG_MMC_TRACE
 	int status;
 #endif
 	cmd.cmdidx = MMC_CMD_SEND_STATUS;
 	cmd.resp_type = MMC_RSP_R1;
 	if (!mmc_host_is_spi(mmc))
 		cmd.cmdarg = mmc->rca << 16;
 	while (1) {
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (!err) {
 			if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
 			    (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
 			     MMC_STATE_PRG)
 				break;
 			else if (cmd.response[0] & MMC_STATUS_MASK) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 				printf("Status Error: 0x%08X\n",
 					cmd.response[0]);
 #endif
 				return COMM_ERR;
 			}
 		} else if (--retries < 0)
 			return err;
 		if (timeout-- <= 0)
 			break;
 		udelay(1000);
 	}
 #ifdef CONFIG_MMC_TRACE
 	status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
 	printf("CURR STATE:%d\n", status);
 #endif
 	if (timeout <= 0) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("Timeout waiting card ready\n");
 #endif
 		return TIMEOUT;
 	}
 	if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
 		return SWITCH_ERR;
 	return 0;
 }
 int mmc_set_blocklen(struct mmc *mmc, int len)
 {
 	struct mmc_cmd cmd;
 	if (mmc->ddr_mode)
 		return 0;
 	cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = len;
 	return mmc_send_cmd(mmc, &cmd, NULL);
 }
 struct mmc *find_mmc_device(int dev_num)
 {
 	struct mmc *m;
 	struct list_head *entry;
 	list_for_each(entry, &mmc_devices) {
 		m = list_entry(entry, struct mmc, link);
 		if (m->block_dev.dev == dev_num)
 			return m;
 	}
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 	printf("MMC Device %d not found\n", dev_num);
 #endif
 	return NULL;
 }
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 			   lbaint_t blkcnt)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
 	if (blkcnt > 1)
 		cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 	else
 		cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
 	if (mmc->high_capacity)
 		cmd.cmdarg = start;
 	else
 		cmd.cmdarg = start * mmc->read_bl_len;
 	cmd.resp_type = MMC_RSP_R1;
 	data.dest = dst;
 	data.blocks = blkcnt;
 	data.blocksize = mmc->read_bl_len;
 	data.flags = MMC_DATA_READ;
 	if (mmc_send_cmd(mmc, &cmd, &data))
 		return 0;
 	if (blkcnt > 1) {
 		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 		cmd.cmdarg = 0;
 		cmd.resp_type = MMC_RSP_R1b;
 		if (mmc_send_cmd(mmc, &cmd, NULL)) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 			printf("mmc fail to send stop cmd\n");
 #endif
 			return 0;
 		}
 	}
 	return blkcnt;
 }
 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
 {
 	lbaint_t cur, blocks_todo = blkcnt;
 	if (blkcnt == 0)
 		return 0;
 	struct mmc *mmc = find_mmc_device(dev_num);
 	if (!mmc)
 		return 0;
 	if ((start + blkcnt) > mmc->block_dev.lba) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 			start + blkcnt, mmc->block_dev.lba);
 #endif
 		return 0;
 	}
 	if (mmc_set_blocklen(mmc, mmc->read_bl_len))
 		return 0;
 	do {
 		cur = (blocks_todo > mmc->cfg->b_max) ?
 			mmc->cfg->b_max : blocks_todo;
 		if(mmc_read_blocks(mmc, dst, start, cur) != cur)
 			return 0;
 		blocks_todo -= cur;
 		start += cur;
 		dst += cur * mmc->read_bl_len;
 	} while (blocks_todo > 0);
 	return blkcnt;
 }
 static int mmc_go_idle(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int err;
 	udelay(1000);
 	cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 	cmd.cmdarg = 0;
 	cmd.resp_type = MMC_RSP_NONE;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err)
 		return err;
 	udelay(2000);
 	return 0;
 }
 static int sd_send_op_cond(struct mmc *mmc)
 {
 	int timeout = 1000;
 	int err;
 	struct mmc_cmd cmd;
 	while (1) {
 		cmd.cmdidx = MMC_CMD_APP_CMD;
 		cmd.resp_type = MMC_RSP_R1;
 		cmd.cmdarg = 0;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 		cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
 		cmd.resp_type = MMC_RSP_R3;
 		/*
 		 * Most cards do not answer if some reserved bits
 		 * in the ocr are set. However, Some controller
 		 * can set bit 7 (reserved for low voltages), but
 		 * how to manage low voltages SD card is not yet
 		 * specified.
 		 */
 		cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
 			(mmc->cfg->voltages & 0xff8000);
 		if (mmc->version == SD_VERSION_2)
 			cmd.cmdarg |= OCR_HCS;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 		if (cmd.response[0] & OCR_BUSY)
 			break;
 		if (timeout-- <= 0)
 			return UNUSABLE_ERR;
 		udelay(1000);
 	}
 	if (mmc->version != SD_VERSION_2)
 		mmc->version = SD_VERSION_1_0;
 	if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 		cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 		cmd.resp_type = MMC_RSP_R3;
 		cmd.cmdarg = 0;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 	}
 	mmc->ocr = cmd.response[0];
 	mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 	mmc->rca = 0;
 	return 0;
 }
 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
 {
 	struct mmc_cmd cmd;
 	int err;
 	cmd.cmdidx = MMC_CMD_SEND_OP_COND;
 	cmd.resp_type = MMC_RSP_R3;
 	cmd.cmdarg = 0;
-	if (use_arg && !mmc_host_is_spi(mmc)) {
+	if (use_arg && !mmc_host_is_spi(mmc))
-		cmd.cmdarg =
+		cmd.cmdarg = OCR_HCS |
 			(mmc->cfg->voltages &
 			(mmc->ocr & OCR_VOLTAGE_MASK)) |
 			(mmc->ocr & OCR_ACCESS_MODE);
-		if (mmc->cfg->host_caps & MMC_MODE_HC)
-			cmd.cmdarg |= OCR_HCS;
-	}
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err)
 		return err;
 	mmc->ocr = cmd.response[0];
 	return 0;
 }
 static int mmc_send_op_cond(struct mmc *mmc)
 {
 	int err, i;
 	/* Some cards seem to need this */
 	mmc_go_idle(mmc);
  	/* Asking to the card its capabilities */
 	for (i = 0; i < 2; i++) {
 		err = mmc_send_op_cond_iter(mmc, i != 0);
 		if (err)
 			return err;
 		/* exit if not busy (flag seems to be inverted) */
 		if (mmc->ocr & OCR_BUSY)
 			break;
 	}
 	mmc->op_cond_pending = 1;
 	return 0;
 }
 static int mmc_complete_op_cond(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int timeout = 1000;
 	uint start;
 	int err;
 	mmc->op_cond_pending = 0;
 	if (!(mmc->ocr & OCR_BUSY)) {
 		start = get_timer(0);
 		while (1) {
 			err = mmc_send_op_cond_iter(mmc, 1);
 			if (err)
 				return err;
 			if (mmc->ocr & OCR_BUSY)
 				break;
 			if (get_timer(start) > timeout)
 				return UNUSABLE_ERR;
 			udelay(100);
 		}
 	}
 	if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 		cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 		cmd.resp_type = MMC_RSP_R3;
 		cmd.cmdarg = 0;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 		mmc->ocr = cmd.response[0];
 	}
 	mmc->version = MMC_VERSION_UNKNOWN;
 	mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 	mmc->rca = 1;
 	return 0;
 }
 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
 	int err;
 	/* Get the Card Status Register */
 	cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = 0;
 	data.dest = (char *)ext_csd;
 	data.blocks = 1;
 	data.blocksize = MMC_MAX_BLOCK_LEN;
 	data.flags = MMC_DATA_READ;
 	err = mmc_send_cmd(mmc, &cmd, &data);
 	return err;
 }
 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 {
 	struct mmc_cmd cmd;
 	int timeout = 1000;
 	int ret;
 	cmd.cmdidx = MMC_CMD_SWITCH;
 	cmd.resp_type = MMC_RSP_R1b;
 	cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 				 (index << 16) |
 				 (value << 8);
 	ret = mmc_send_cmd(mmc, &cmd, NULL);
 	/* Waiting for the ready status */
 	if (!ret)
 		ret = mmc_send_status(mmc, timeout);
 	return ret;
 }
 static int mmc_change_freq(struct mmc *mmc)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
 	char cardtype;
 	int err;
 	mmc->card_caps = 0;
 	if (mmc_host_is_spi(mmc))
 		return 0;
 	/* Only version 4 supports high-speed */
 	if (mmc->version < MMC_VERSION_4)
 		return 0;
 	mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 	err = mmc_send_ext_csd(mmc, ext_csd);
 	if (err)
 		return err;
 	cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
 	if (err)
 		return err == SWITCH_ERR ? 0 : err;
 	/* Now check to see that it worked */
 	err = mmc_send_ext_csd(mmc, ext_csd);
 	if (err)
 		return err;
 	/* No high-speed support */
 	if (!ext_csd[EXT_CSD_HS_TIMING])
 		return 0;
 	/* High Speed is set, there are two types: 52MHz and 26MHz */
 	if (cardtype & EXT_CSD_CARD_TYPE_52) {
 		if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
 			mmc->card_caps |= MMC_MODE_DDR_52MHz;
 		mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 	} else {
 		mmc->card_caps |= MMC_MODE_HS;
 	}
 	return 0;
 }
 static int mmc_set_capacity(struct mmc *mmc, int part_num)
 {
 	switch (part_num) {
 	case 0:
 		mmc->capacity = mmc->capacity_user;
 		break;
 	case 1:
 	case 2:
 		mmc->capacity = mmc->capacity_boot;
 		break;
 	case 3:
 		mmc->capacity = mmc->capacity_rpmb;
 		break;
 	case 4:
 	case 5:
 	case 6:
 	case 7:
 		mmc->capacity = mmc->capacity_gp[part_num - 4];
 		break;
 	default:
 		return -1;
 	}
 	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
 	return 0;
 }
 int mmc_select_hwpart(int dev_num, int hwpart)
 {
 	struct mmc *mmc = find_mmc_device(dev_num);
 	int ret;
 	if (!mmc)
 		return -ENODEV;
 	if (mmc->part_num == hwpart)
 		return 0;
 	if (mmc->part_config == MMCPART_NOAVAILABLE) {
 		printf("Card doesn't support part_switch\n");
 		return -EMEDIUMTYPE;
 	}
 	ret = mmc_switch_part(dev_num, hwpart);
 	if (ret)
 		return ret;
 	mmc->part_num = hwpart;
 	return 0;
 }
 int mmc_switch_part(int dev_num, unsigned int part_num)
 {
 	struct mmc *mmc = find_mmc_device(dev_num);
 	int ret;
 	if (!mmc)
 		return -1;
 	ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
 			 (mmc->part_config & ~PART_ACCESS_MASK)
 			 | (part_num & PART_ACCESS_MASK));
 	/*
 	 * Set the capacity if the switch succeeded or was intended
 	 * to return to representing the raw device.
 	 */
 	if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
 		ret = mmc_set_capacity(mmc, part_num);
 	return ret;
 }
 int mmc_hwpart_config(struct mmc *mmc,
 		      const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode)
 {
 	u8 part_attrs = 0;
 	u32 enh_size_mult;
 	u32 enh_start_addr;
 	u32 gp_size_mult[4];
 	u32 max_enh_size_mult;
 	u32 tot_enh_size_mult = 0;
 	u8 wr_rel_set;
 	int i, pidx, err;
 	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
 	if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
 		return -EINVAL;
 	if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
 		printf("eMMC >= 4.4 required for enhanced user data area\n");
 		return -EMEDIUMTYPE;
 	}
 	if (!(mmc->part_support & PART_SUPPORT)) {
 		printf("Card does not support partitioning\n");
 		return -EMEDIUMTYPE;
 	}
 	if (!mmc->hc_wp_grp_size) {
 		printf("Card does not define HC WP group size\n");
 		return -EMEDIUMTYPE;
 	}
 	/* check partition alignment and total enhanced size */
 	if (conf->user.enh_size) {
 		if (conf->user.enh_size % mmc->hc_wp_grp_size ||
 		    conf->user.enh_start % mmc->hc_wp_grp_size) {
 			printf("User data enhanced area not HC WP group "
 			       "size aligned\n");
 			return -EINVAL;
 		}
 		part_attrs |= EXT_CSD_ENH_USR;
 		enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
 		if (mmc->high_capacity) {
 			enh_start_addr = conf->user.enh_start;
 		} else {
 			enh_start_addr = (conf->user.enh_start << 9);
 		}
 	} else {
 		enh_size_mult = 0;
 		enh_start_addr = 0;
 	}
 	tot_enh_size_mult += enh_size_mult;
 	for (pidx = 0; pidx < 4; pidx++) {
 		if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
 			printf("GP%i partition not HC WP group size "
 			       "aligned\n", pidx+1);
 			return -EINVAL;
 		}
 		gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
 		if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
 			part_attrs |= EXT_CSD_ENH_GP(pidx);
 			tot_enh_size_mult += gp_size_mult[pidx];
 		}
 	}
 	if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
 		printf("Card does not support enhanced attribute\n");
 		return -EMEDIUMTYPE;
 	}
 	err = mmc_send_ext_csd(mmc, ext_csd);
 	if (err)
 		return err;
 	max_enh_size_mult =
 		(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
 		(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
 		ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
 	if (tot_enh_size_mult > max_enh_size_mult) {
 		printf("Total enhanced size exceeds maximum (%u > %u)\n",
 		       tot_enh_size_mult, max_enh_size_mult);
 		return -EMEDIUMTYPE;
 	}
 	/* The default value of EXT_CSD_WR_REL_SET is device
 	 * dependent, the values can only be changed if the
 	 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
 	 * changed only once and before partitioning is completed. */
 	wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
 	if (conf->user.wr_rel_change) {
 		if (conf->user.wr_rel_set)
 			wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
 		else
 			wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
 	}
 	for (pidx = 0; pidx < 4; pidx++) {
 		if (conf->gp_part[pidx].wr_rel_change) {
 			if (conf->gp_part[pidx].wr_rel_set)
 				wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
 			else
 				wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
 		}
 	}
 	if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
 	    !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
 		puts("Card does not support host controlled partition write "
 		     "reliability settings\n");
 		return -EMEDIUMTYPE;
 	}
 	if (ext_csd[EXT_CSD_PARTITION_SETTING] &
 	    EXT_CSD_PARTITION_SETTING_COMPLETED) {
 		printf("Card already partitioned\n");
 		return -EPERM;
 	}
 	if (mode == MMC_HWPART_CONF_CHECK)
 		return 0;
 	/* Partitioning requires high-capacity size definitions */
 	if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
 		err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				 EXT_CSD_ERASE_GROUP_DEF, 1);
 		if (err)
 			return err;
 		ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
 		/* update erase group size to be high-capacity */
 		mmc->erase_grp_size =
 			ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
 	}
 	/* all OK, write the configuration */
 	for (i = 0; i < 4; i++) {
 		err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				 EXT_CSD_ENH_START_ADDR+i,
 				 (enh_start_addr >> (i*8)) & 0xFF);
 		if (err)
 			return err;
 	}
 	for (i = 0; i < 3; i++) {
 		err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				 EXT_CSD_ENH_SIZE_MULT+i,
 				 (enh_size_mult >> (i*8)) & 0xFF);
 		if (err)
 			return err;
 	}
 	for (pidx = 0; pidx < 4; pidx++) {
 		for (i = 0; i < 3; i++) {
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 					 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
 					 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
 			if (err)
 				return err;
 		}
 	}
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 			 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
 	if (err)
 		return err;
 	if (mode == MMC_HWPART_CONF_SET)
 		return 0;
 	/* The WR_REL_SET is a write-once register but shall be
 	 * written before setting PART_SETTING_COMPLETED. As it is
 	 * write-once we can only write it when completing the
 	 * partitioning. */
 	if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
 		err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				 EXT_CSD_WR_REL_SET, wr_rel_set);
 		if (err)
 			return err;
 	}
 	/* Setting PART_SETTING_COMPLETED confirms the partition
 	 * configuration but it only becomes effective after power
 	 * cycle, so we do not adjust the partition related settings
 	 * in the mmc struct. */
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 			 EXT_CSD_PARTITION_SETTING,
 			 EXT_CSD_PARTITION_SETTING_COMPLETED);
 	if (err)
 		return err;
 	return 0;
 }
 int mmc_getcd(struct mmc *mmc)
 {
 	int cd;
 	cd = board_mmc_getcd(mmc);
 	if (cd < 0) {
 		if (mmc->cfg->ops->getcd)
 			cd = mmc->cfg->ops->getcd(mmc);
 		else
 			cd = 1;
 	}
 	return cd;
 }
 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
 	/* Switch the frequency */
 	cmd.cmdidx = SD_CMD_SWITCH_FUNC;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = (mode << 31) | 0xffffff;
 	cmd.cmdarg &= ~(0xf << (group * 4));
 	cmd.cmdarg |= value << (group * 4);
 	data.dest = (char *)resp;
 	data.blocksize = 64;
 	data.blocks = 1;
 	data.flags = MMC_DATA_READ;
 	return mmc_send_cmd(mmc, &cmd, &data);
 }
 static int sd_change_freq(struct mmc *mmc)
 {
 	int err;
 	struct mmc_cmd cmd;
 	ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
 	ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
 	struct mmc_data data;
 	int timeout;
 	mmc->card_caps = 0;
 	if (mmc_host_is_spi(mmc))
 		return 0;
 	/* Read the SCR to find out if this card supports higher speeds */
 	cmd.cmdidx = MMC_CMD_APP_CMD;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = mmc->rca << 16;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err)
 		return err;
 	cmd.cmdidx = SD_CMD_APP_SEND_SCR;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = 0;
 	timeout = 3;
 retry_scr:
 	data.dest = (char *)scr;
 	data.blocksize = 8;
 	data.blocks = 1;
 	data.flags = MMC_DATA_READ;
 	err = mmc_send_cmd(mmc, &cmd, &data);
 	if (err) {
 		if (timeout--)
 			goto retry_scr;
 		return err;
 	}
 	mmc->scr[0] = __be32_to_cpu(scr[0]);
 	mmc->scr[1] = __be32_to_cpu(scr[1]);
 	switch ((mmc->scr[0] >> 24) & 0xf) {
 		case 0:
 			mmc->version = SD_VERSION_1_0;
 			break;
 		case 1:
 			mmc->version = SD_VERSION_1_10;
 			break;
 		case 2:
 			mmc->version = SD_VERSION_2;
 			if ((mmc->scr[0] >> 15) & 0x1)
 				mmc->version = SD_VERSION_3;
 			break;
 		default:
 			mmc->version = SD_VERSION_1_0;
 			break;
 	}
 	if (mmc->scr[0] & SD_DATA_4BIT)
 		mmc->card_caps |= MMC_MODE_4BIT;
 	/* Version 1.0 doesn't support switching */
 	if (mmc->version == SD_VERSION_1_0)
 		return 0;
 	timeout = 4;
 	while (timeout--) {
 		err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
 				(u8 *)switch_status);
 		if (err)
 			return err;
 		/* The high-speed function is busy.  Try again */
 		if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
 			break;
 	}
 	/* If high-speed isn't supported, we return */
 	if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
 		return 0;
 	/*
 	 * If the host doesn't support SD_HIGHSPEED, do not switch card to
 	 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
 	 * This can avoid furthur problem when the card runs in different
 	 * mode between the host.
 	 */
 	if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
 		(mmc->cfg->host_caps & MMC_MODE_HS)))
 		return 0;
 	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
 	if (err)
 		return err;
 	if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
 		mmc->card_caps |= MMC_MODE_HS;
 	return 0;
 }
 /* frequency bases */
 /* divided by 10 to be nice to platforms without floating point */
 static const int fbase[] = {
 	10000,
 	100000,
 	1000000,
 	10000000,
 };
 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
  * to platforms without floating point.
  */
 static const int multipliers[] = {
 	0,	/* reserved */
 	10,
 	12,
 	13,
 	15,
 	20,
 	25,
 	30,
 	35,
 	40,
 	45,
 	50,
 	55,
 	60,
 	70,
 	80,
 };
 static void mmc_set_ios(struct mmc *mmc)
 {
 	if (mmc->cfg->ops->set_ios)
 		mmc->cfg->ops->set_ios(mmc);
 }
 void mmc_set_clock(struct mmc *mmc, uint clock)
 {
 	if (clock > mmc->cfg->f_max)
 		clock = mmc->cfg->f_max;
 	if (clock < mmc->cfg->f_min)
 		clock = mmc->cfg->f_min;
 	mmc->clock = clock;
 	mmc_set_ios(mmc);
 }
 static void mmc_set_bus_width(struct mmc *mmc, uint width)
 {
 	mmc->bus_width = width;
 	mmc_set_ios(mmc);
 }
 static int mmc_startup(struct mmc *mmc)
 {
 	int err, i;
 	uint mult, freq;
 	u64 cmult, csize, capacity;
 	struct mmc_cmd cmd;
 	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
 	ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 	int timeout = 1000;
 	bool has_parts = false;
 	bool part_completed;
 #ifdef CONFIG_MMC_SPI_CRC_ON
 	if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
 		cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
 		cmd.resp_type = MMC_RSP_R1;
 		cmd.cmdarg = 1;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 	}
 #endif
 	/* Put the Card in Identify Mode */
 	cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
 		MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
 	cmd.resp_type = MMC_RSP_R2;
 	cmd.cmdarg = 0;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err)
 		return err;
 	memcpy(mmc->cid, cmd.response, 16);
 	/*
 	 * For MMC cards, set the Relative Address.
 	 * For SD cards, get the Relatvie Address.
 	 * This also puts the cards into Standby State
 	 */
 	if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
 		cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
 		cmd.cmdarg = mmc->rca << 16;
 		cmd.resp_type = MMC_RSP_R6;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 		if (IS_SD(mmc))
 			mmc->rca = (cmd.response[0] >> 16) & 0xffff;
 	}
 	/* Get the Card-Specific Data */
 	cmd.cmdidx = MMC_CMD_SEND_CSD;
 	cmd.resp_type = MMC_RSP_R2;
 	cmd.cmdarg = mmc->rca << 16;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	/* Waiting for the ready status */
 	mmc_send_status(mmc, timeout);
 	if (err)
 		return err;
 	mmc->csd[0] = cmd.response[0];
 	mmc->csd[1] = cmd.response[1];
 	mmc->csd[2] = cmd.response[2];
 	mmc->csd[3] = cmd.response[3];
 	if (mmc->version == MMC_VERSION_UNKNOWN) {
 		int version = (cmd.response[0] >> 26) & 0xf;
 		switch (version) {
 			case 0:
 				mmc->version = MMC_VERSION_1_2;
 				break;
 			case 1:
 				mmc->version = MMC_VERSION_1_4;
 				break;
 			case 2:
 				mmc->version = MMC_VERSION_2_2;
 				break;
 			case 3:
 				mmc->version = MMC_VERSION_3;
 				break;
 			case 4:
 				mmc->version = MMC_VERSION_4;
 				break;
 			default:
 				mmc->version = MMC_VERSION_1_2;
 				break;
 		}
 	}
 	/* divide frequency by 10, since the mults are 10x bigger */
 	freq = fbase[(cmd.response[0] & 0x7)];
 	mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
 	mmc->tran_speed = freq * mult;
 	mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
 	mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
 	if (IS_SD(mmc))
 		mmc->write_bl_len = mmc->read_bl_len;
 	else
 		mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
 	if (mmc->high_capacity) {
 		csize = (mmc->csd[1] & 0x3f) << 16
 			| (mmc->csd[2] & 0xffff0000) >> 16;
 		cmult = 8;
 	} else {
 		csize = (mmc->csd[1] & 0x3ff) << 2
 			| (mmc->csd[2] & 0xc0000000) >> 30;
 		cmult = (mmc->csd[2] & 0x00038000) >> 15;
 	}
 	mmc->capacity_user = (csize + 1) << (cmult + 2);
 	mmc->capacity_user *= mmc->read_bl_len;
 	mmc->capacity_boot = 0;
 	mmc->capacity_rpmb = 0;
 	for (i = 0; i < 4; i++)
 		mmc->capacity_gp[i] = 0;
 	if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
 		mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
 	if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
 		mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
 	if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
 		cmd.cmdidx = MMC_CMD_SET_DSR;
 		cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
 		cmd.resp_type = MMC_RSP_NONE;
 		if (mmc_send_cmd(mmc, &cmd, NULL))
 			printf("MMC: SET_DSR failed\n");
 	}
 	/* Select the card, and put it into Transfer Mode */
 	if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
 		cmd.cmdidx = MMC_CMD_SELECT_CARD;
 		cmd.resp_type = MMC_RSP_R1;
 		cmd.cmdarg = mmc->rca << 16;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 		if (err)
 			return err;
 	}
 	/*
 	 * For SD, its erase group is always one sector
 	 */
 	mmc->erase_grp_size = 1;
 	mmc->part_config = MMCPART_NOAVAILABLE;
 	if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
 		/* check  ext_csd version and capacity */
 		err = mmc_send_ext_csd(mmc, ext_csd);
 		if (err)
 			return err;
 		if (ext_csd[EXT_CSD_REV] >= 2) {
 			/*
 			 * According to the JEDEC Standard, the value of
 			 * ext_csd's capacity is valid if the value is more
 			 * than 2GB
 			 */
 			capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
 					| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
 					| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
 					| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
 			capacity *= MMC_MAX_BLOCK_LEN;
 			if ((capacity >> 20) > 2 * 1024)
 				mmc->capacity_user = capacity;
 		}
 		switch (ext_csd[EXT_CSD_REV]) {
 		case 1:
 			mmc->version = MMC_VERSION_4_1;
 			break;
 		case 2:
 			mmc->version = MMC_VERSION_4_2;
 			break;
 		case 3:
 			mmc->version = MMC_VERSION_4_3;
 			break;
 		case 5:
 			mmc->version = MMC_VERSION_4_41;
 			break;
 		case 6:
 			mmc->version = MMC_VERSION_4_5;
 			break;
 		case 7:
 			mmc->version = MMC_VERSION_5_0;
 			break;
 		}
 		/* The partition data may be non-zero but it is only
 		 * effective if PARTITION_SETTING_COMPLETED is set in
 		 * EXT_CSD, so ignore any data if this bit is not set,
 		 * except for enabling the high-capacity group size
 		 * definition (see below). */
 		part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
 				    EXT_CSD_PARTITION_SETTING_COMPLETED);
 		/* store the partition info of emmc */
 		mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
 		if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
 		    ext_csd[EXT_CSD_BOOT_MULT])
 			mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
 		if (part_completed &&
 		    (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
 			mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
 		mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
 		mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
 		for (i = 0; i < 4; i++) {
 			int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
 			uint mult = (ext_csd[idx + 2] << 16) +
 				(ext_csd[idx + 1] << 8) + ext_csd[idx];
 			if (mult)
 				has_parts = true;
 			if (!part_completed)
 				continue;
 			mmc->capacity_gp[i] = mult;
 			mmc->capacity_gp[i] *=
 				ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
 			mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
 			mmc->capacity_gp[i] <<= 19;
 		}
 		if (part_completed) {
 			mmc->enh_user_size =
 				(ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
 				(ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
 				ext_csd[EXT_CSD_ENH_SIZE_MULT];
 			mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
 			mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
 			mmc->enh_user_size <<= 19;
 			mmc->enh_user_start =
 				(ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
 				(ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
 				(ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
 				ext_csd[EXT_CSD_ENH_START_ADDR];
 			if (mmc->high_capacity)
 				mmc->enh_user_start <<= 9;
 		}
 		/*
 		 * Host needs to enable ERASE_GRP_DEF bit if device is
 		 * partitioned. This bit will be lost every time after a reset
 		 * or power off. This will affect erase size.
 		 */
 		if (part_completed)
 			has_parts = true;
 		if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
 		    (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
 			has_parts = true;
 		if (has_parts) {
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				EXT_CSD_ERASE_GROUP_DEF, 1);
 			if (err)
 				return err;
 			else
 				ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
 		}
 		if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
 			/* Read out group size from ext_csd */
 			mmc->erase_grp_size =
 				ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
 			/*
 			 * if high capacity and partition setting completed
 			 * SEC_COUNT is valid even if it is smaller than 2 GiB
 			 * JEDEC Standard JESD84-B45, 6.2.4
 			 */
 			if (mmc->high_capacity && part_completed) {
 				capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
 					(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
 					(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
 					(ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
 				capacity *= MMC_MAX_BLOCK_LEN;
 				mmc->capacity_user = capacity;
 			}
 		} else {
 			/* Calculate the group size from the csd value. */
 			int erase_gsz, erase_gmul;
 			erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
 			erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
 			mmc->erase_grp_size = (erase_gsz + 1)
 				* (erase_gmul + 1);
 		}
 		mmc->hc_wp_grp_size = 1024
 			* ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
 			* ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
 		mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
 	}
 	err = mmc_set_capacity(mmc, mmc->part_num);
 	if (err)
 		return err;
 	if (IS_SD(mmc))
 		err = sd_change_freq(mmc);
 	else
 		err = mmc_change_freq(mmc);
 	if (err)
 		return err;
 	/* Restrict card's capabilities by what the host can do */
 	mmc->card_caps &= mmc->cfg->host_caps;
 	if (IS_SD(mmc)) {
 		if (mmc->card_caps & MMC_MODE_4BIT) {
 			cmd.cmdidx = MMC_CMD_APP_CMD;
 			cmd.resp_type = MMC_RSP_R1;
 			cmd.cmdarg = mmc->rca << 16;
 			err = mmc_send_cmd(mmc, &cmd, NULL);
 			if (err)
 				return err;
 			cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
 			cmd.resp_type = MMC_RSP_R1;
 			cmd.cmdarg = 2;
 			err = mmc_send_cmd(mmc, &cmd, NULL);
 			if (err)
 				return err;
 			mmc_set_bus_width(mmc, 4);
 		}
 		if (mmc->card_caps & MMC_MODE_HS)
 			mmc->tran_speed = 50000000;
 		else
 			mmc->tran_speed = 25000000;
 	} else if (mmc->version >= MMC_VERSION_4) {
 		/* Only version 4 of MMC supports wider bus widths */
 		int idx;
 		/* An array of possible bus widths in order of preference */
 		static unsigned ext_csd_bits[] = {
 			EXT_CSD_DDR_BUS_WIDTH_8,
 			EXT_CSD_DDR_BUS_WIDTH_4,
 			EXT_CSD_BUS_WIDTH_8,
 			EXT_CSD_BUS_WIDTH_4,
 			EXT_CSD_BUS_WIDTH_1,
 		};
 		/* An array to map CSD bus widths to host cap bits */
 		static unsigned ext_to_hostcaps[] = {
 			[EXT_CSD_DDR_BUS_WIDTH_4] =
 				MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
 			[EXT_CSD_DDR_BUS_WIDTH_8] =
 				MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
 			[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
 			[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
 		};
 		/* An array to map chosen bus width to an integer */
 		static unsigned widths[] = {
 			8, 4, 8, 4, 1,
 		};
 		for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
 			unsigned int extw = ext_csd_bits[idx];
 			unsigned int caps = ext_to_hostcaps[extw];
 			/*
 			 * If the bus width is still not changed,
 			 * don't try to set the default again.
 			 * Otherwise, recover from switch attempts
 			 * by switching to 1-bit bus width.
 			 */
 			if (extw == EXT_CSD_BUS_WIDTH_1 &&
 					mmc->bus_width == 1) {
 				err = 0;
 				break;
 			}
 			/*
 			 * Check to make sure the card and controller support
 			 * these capabilities
 			 */
 			if ((mmc->card_caps & caps) != caps)
 				continue;
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 					EXT_CSD_BUS_WIDTH, extw);
 			if (err)
 				continue;
 			mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
 			mmc_set_bus_width(mmc, widths[idx]);
 			err = mmc_send_ext_csd(mmc, test_csd);
 			if (err)
 				continue;
 			/* Only compare read only fields */
 			if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
 				== test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
 			    ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
 				== test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
 			    ext_csd[EXT_CSD_REV]
 				== test_csd[EXT_CSD_REV] &&
 			    ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
 				== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
 			    memcmp(&ext_csd[EXT_CSD_SEC_CNT],
 				   &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
 				break;
 			else
 				err = SWITCH_ERR;
 		}
 		if (err)
 			return err;
 		if (mmc->card_caps & MMC_MODE_HS) {
 			if (mmc->card_caps & MMC_MODE_HS_52MHz)
 				mmc->tran_speed = 52000000;
 			else
 				mmc->tran_speed = 26000000;
 		}
 	}
 	mmc_set_clock(mmc, mmc->tran_speed);
 	/* Fix the block length for DDR mode */
 	if (mmc->ddr_mode) {
 		mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
 		mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
 	}
 	/* fill in device description */
 	mmc->block_dev.lun = 0;
 	mmc->block_dev.type = 0;
 	mmc->block_dev.blksz = mmc->read_bl_len;
 	mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
 	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 	sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
 		mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
 		(mmc->cid[3] >> 16) & 0xffff);
 	sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
 		(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
 		(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
 		(mmc->cid[2] >> 24) & 0xff);
 	sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
 		(mmc->cid[2] >> 16) & 0xf);
 #else
 	mmc->block_dev.vendor[0] = 0;
 	mmc->block_dev.product[0] = 0;
 	mmc->block_dev.revision[0] = 0;
 #endif
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
 	init_part(&mmc->block_dev);
 #endif
 	return 0;
 }
 static int mmc_send_if_cond(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int err;
 	cmd.cmdidx = SD_CMD_SEND_IF_COND;
 	/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
 	cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
 	cmd.resp_type = MMC_RSP_R7;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err)
 		return err;
 	if ((cmd.response[0] & 0xff) != 0xaa)
 		return UNUSABLE_ERR;
 	else
 		mmc->version = SD_VERSION_2;
 	return 0;
 }
 /* not used any more */
 int __deprecated mmc_register(struct mmc *mmc)
 {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 	printf("%s is deprecated! use mmc_create() instead.\n", __func__);
 #endif
 	return -1;
 }
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
 	struct mmc *mmc;
 	/* quick validation */
 	if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
 			cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
 		return NULL;
 	mmc = calloc(1, sizeof(*mmc));
 	if (mmc == NULL)
 		return NULL;
 	mmc->cfg = cfg;
 	mmc->priv = priv;
 	/* the following chunk was mmc_register() */
 	/* Setup dsr related values */
 	mmc->dsr_imp = 0;
 	mmc->dsr = 0xffffffff;
 	/* Setup the universal parts of the block interface just once */
 	mmc->block_dev.if_type = IF_TYPE_MMC;
 	mmc->block_dev.dev = cur_dev_num++;
 	mmc->block_dev.removable = 1;
 	mmc->block_dev.block_read = mmc_bread;
 	mmc->block_dev.block_write = mmc_bwrite;
 	mmc->block_dev.block_erase = mmc_berase;
 	/* setup initial part type */
 	mmc->block_dev.part_type = mmc->cfg->part_type;
 	INIT_LIST_HEAD(&mmc->link);
 	list_add_tail(&mmc->link, &mmc_devices);
 	return mmc;
 }
 void mmc_destroy(struct mmc *mmc)
 {
 	/* only freeing memory for now */
 	free(mmc);
 }
 #ifdef CONFIG_PARTITIONS
 block_dev_desc_t *mmc_get_dev(int dev)
 {
 	struct mmc *mmc = find_mmc_device(dev);
 	if (!mmc || mmc_init(mmc))
 		return NULL;
 	return &mmc->block_dev;
 }
 #endif
 /* board-specific MMC power initializations. */
 __weak void board_mmc_power_init(void)
 {
 }
 int mmc_start_init(struct mmc *mmc)
 {
 	int err;
 	/* we pretend there's no card when init is NULL */
 	if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
 		mmc->has_init = 0;
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: no card present\n");
 #endif
 		return NO_CARD_ERR;
 	}
 	if (mmc->has_init)
 		return 0;
 	board_mmc_power_init();
 	/* made sure it's not NULL earlier */
 	err = mmc->cfg->ops->init(mmc);
 	if (err)
 		return err;
 	mmc->ddr_mode = 0;
 	mmc_set_bus_width(mmc, 1);
 	mmc_set_clock(mmc, 1);
 	/* Reset the Card */
 	err = mmc_go_idle(mmc);
 	if (err)
 		return err;
 	/* The internal partition reset to user partition(0) at every CMD0*/
 	mmc->part_num = 0;
 	/* Test for SD version 2 */
 	err = mmc_send_if_cond(mmc);
 	/* Now try to get the SD card's operating condition */
 	err = sd_send_op_cond(mmc);
 	/* If the command timed out, we check for an MMC card */
 	if (err == TIMEOUT) {
 		err = mmc_send_op_cond(mmc);
 		if (err) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 			printf("Card did not respond to voltage select!\n");
 #endif
 			return UNUSABLE_ERR;
 		}
 	}
 	if (!err)
 		mmc->init_in_progress = 1;
 	return err;
 }
 static int mmc_complete_init(struct mmc *mmc)
 {
 	int err = 0;
 	mmc->init_in_progress = 0;
 	if (mmc->op_cond_pending)
 		err = mmc_complete_op_cond(mmc);
 	if (!err)
 		err = mmc_startup(mmc);
 	if (err)
 		mmc->has_init = 0;
 	else
 		mmc->has_init = 1;
 	return err;
 }
 int mmc_init(struct mmc *mmc)
 {
 	int err = 0;
 	unsigned start;
 	if (mmc->has_init)
 		return 0;
 	start = get_timer(0);
 	if (!mmc->init_in_progress)
 		err = mmc_start_init(mmc);
 	if (!err)
 		err = mmc_complete_init(mmc);
 	debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
 	return err;
 }
 int mmc_set_dsr(struct mmc *mmc, u16 val)
 {
 	mmc->dsr = val;
 	return 0;
 }
 /* CPU-specific MMC initializations */
 __weak int cpu_mmc_init(bd_t *bis)
 {
 	return -1;
 }
 /* board-specific MMC initializations. */
 __weak int board_mmc_init(bd_t *bis)
 {
 	return -1;
 }
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 void print_mmc_devices(char separator)
 {
 	struct mmc *m;
 	struct list_head *entry;
 	char *mmc_type;
 	list_for_each(entry, &mmc_devices) {
 		m = list_entry(entry, struct mmc, link);
 		if (m->has_init)
 			mmc_type = IS_SD(m) ? "SD" : "eMMC";
 		else
 			mmc_type = NULL;
 		printf("%s: %d", m->cfg->name, m->block_dev.dev);
 		if (mmc_type)
 			printf(" (%s)", mmc_type);
 		if (entry->next != &mmc_devices) {
 			printf("%c", separator);
 			if (separator != '\n')
 				puts (" ");
 		}
 	}
 	printf("\n");
 }
 #else
 void print_mmc_devices(char separator) { }
 #endif
 int get_mmc_num(void)
 {
 	return cur_dev_num;
 }
 void mmc_set_preinit(struct mmc *mmc, int preinit)
 {
 	mmc->preinit = preinit;
 }
 static void do_preinit(void)
 {
 	struct mmc *m;
 	struct list_head *entry;
 	list_for_each(entry, &mmc_devices) {
 		m = list_entry(entry, struct mmc, link);
 		if (m->preinit)
 			mmc_start_init(m);
 	}
 }
 int mmc_initialize(bd_t *bis)
 {
 	INIT_LIST_HEAD (&mmc_devices);
 	cur_dev_num = 0;
 	if (board_mmc_init(bis) < 0)
 		cpu_mmc_init(bis);
 #ifndef CONFIG_SPL_BUILD
 	print_mmc_devices(',');
 #endif
 	do_preinit();
 	return 0;
 }
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 /*
  * This function changes the size of boot partition and the size of rpmb
  * partition present on EMMC devices.
  *
  * Input Parameters:
  * struct *mmc: pointer for the mmc device strcuture
  * bootsize: size of boot partition
  * rpmbsize: size of rpmb partition
  *
  * Returns 0 on success.
  */
 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 				unsigned long rpmbsize)
 {
 	int err;
 	struct mmc_cmd cmd;
 	/* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
 	cmd.cmdidx = MMC_CMD_RES_MAN;
 	cmd.resp_type = MMC_RSP_R1b;
 	cmd.cmdarg = MMC_CMD62_ARG1;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err) {
 		debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
 		return err;
 	}
 	/* Boot partition changing mode */
 	cmd.cmdidx = MMC_CMD_RES_MAN;
 	cmd.resp_type = MMC_RSP_R1b;
 	cmd.cmdarg = MMC_CMD62_ARG2;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err) {
 		debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
 		return err;
 	}
 	/* boot partition size is multiple of 128KB */
 	bootsize = (bootsize * 1024) / 128;
 	/* Arg: boot partition size */
 	cmd.cmdidx = MMC_CMD_RES_MAN;
 	cmd.resp_type = MMC_RSP_R1b;
 	cmd.cmdarg = bootsize;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err) {
 		debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
 		return err;
 	}
 	/* RPMB partition size is multiple of 128KB */
 	rpmbsize = (rpmbsize * 1024) / 128;
 	/* Arg: RPMB partition size */
 	cmd.cmdidx = MMC_CMD_RES_MAN;
 	cmd.resp_type = MMC_RSP_R1b;
 	cmd.cmdarg = rpmbsize;
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 	if (err) {
 		debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
 		return err;
 	}
 	return 0;
 }
 /*
  * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
  * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
  * and BOOT_MODE.
  *
  * Returns 0 on success.
  */
 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
 {
 	int err;
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
 			 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
 			 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
 			 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
 	if (err)
 		return err;
 	return 0;
 }
 /*
  * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
  * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
  * PARTITION_ACCESS.
  *
  * Returns 0 on success.
  */
 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
 {
 	int err;
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
 			 EXT_CSD_BOOT_ACK(ack) |
 			 EXT_CSD_BOOT_PART_NUM(part_num) |
 			 EXT_CSD_PARTITION_ACCESS(access));
 	if (err)
 		return err;
 	return 0;
 }
 /*
  * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
  * for enable.  Note that this is a write-once field for non-zero values.
  *
  * Returns 0 on success.
  */
 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
 {
 	return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
 			  enable);
 }
 #endif

drivers/mmc/mvebu_mmc.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* Marvell MMC/SD/SDIO driver	2	* Marvell MMC/SD/SDIO driver
3	*	3	*
4	* (C) Copyright 2012-2014	4	* (C) Copyright 2012-2014
5	* Marvell Semiconductor <www.marvell.com>	5	* Marvell Semiconductor <www.marvell.com>
6	* Written-by: Maen Suleiman, Gerald Kerma	6	* Written-by: Maen Suleiman, Gerald Kerma
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <malloc.h>	12	#include <malloc.h>
13	#include <part.h>	13	#include <part.h>
14	#include <mmc.h>	14	#include <mmc.h>
15	#include <asm/io.h>	15	#include <asm/io.h>
16	#include <asm/arch/cpu.h>	16	#include <asm/arch/cpu.h>
17	#include <asm/arch/soc.h>	17	#include <asm/arch/soc.h>
18	#include <mvebu_mmc.h>	18	#include <mvebu_mmc.h>
19		19
20	DECLARE_GLOBAL_DATA_PTR;	20	DECLARE_GLOBAL_DATA_PTR;
21		21
22	#define DRIVER_NAME "MVEBU_MMC"	22	#define DRIVER_NAME "MVEBU_MMC"
23		23
24	#define MVEBU_TARGET_DRAM 0	24	#define MVEBU_TARGET_DRAM 0
25		25
26	#define TIMEOUT_DELAY 5CONFIG_SYS_HZ / wait 5 seconds */	26	#define TIMEOUT_DELAY 5CONFIG_SYS_HZ / wait 5 seconds */
27		27
28	static void mvebu_mmc_write(u32 offs, u32 val)	28	static void mvebu_mmc_write(u32 offs, u32 val)
29	{	29	{
30	writel(val, CONFIG_SYS_MMC_BASE + (offs));	30	writel(val, CONFIG_SYS_MMC_BASE + (offs));
31	}	31	}
32		32
33	static u32 mvebu_mmc_read(u32 offs)	33	static u32 mvebu_mmc_read(u32 offs)
34	{	34	{
35	return readl(CONFIG_SYS_MMC_BASE + (offs));	35	return readl(CONFIG_SYS_MMC_BASE + (offs));
36	}	36	}
37		37
38	static int mvebu_mmc_setup_data(struct mmc_data *data)	38	static int mvebu_mmc_setup_data(struct mmc_data *data)
39	{	39	{
40	u32 ctrl_reg;	40	u32 ctrl_reg;
41		41
42	debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,	42	debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
43	(data->flags & MMC_DATA_READ) ? "read" : "write",	43	(data->flags & MMC_DATA_READ) ? "read" : "write",
44	data->blocks, data->blocksize);	44	data->blocks, data->blocksize);
45		45
46	/* default to maximum timeout */	46	/* default to maximum timeout */
47	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);	47	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
48	ctrl_reg \|= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);	48	ctrl_reg \|= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
49	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);	49	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
50		50
51	if (data->flags & MMC_DATA_READ) {	51	if (data->flags & MMC_DATA_READ) {
52	mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);	52	mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
53	mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);	53	mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
54	} else {	54	} else {
55	mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);	55	mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
56	mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);	56	mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
57	}	57	}
58		58
59	mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);	59	mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
60	mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);	60	mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
61		61
62	return 0;	62	return 0;
63	}	63	}
64		64
65	static int mvebu_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,	65	static int mvebu_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
66	struct mmc_data *data)	66	struct mmc_data *data)
67	{	67	{
68	ulong start;	68	ulong start;
69	ushort waittype = 0;	69	ushort waittype = 0;
70	ushort resptype = 0;	70	ushort resptype = 0;
71	ushort xfertype = 0;	71	ushort xfertype = 0;
72	ushort resp_indx = 0;	72	ushort resp_indx = 0;
73		73
74	debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",	74	debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
75	DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);	75	DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
76		76
77	debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,	77	debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
78	cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));	78	cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
79		79
80	/*	80	/*
81	* Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE	81	* Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
82	* register is sometimes not set before a while when some	82	* register is sometimes not set before a while when some
83	* "unusual" data block sizes are used (such as with the SWITCH	83	* "unusual" data block sizes are used (such as with the SWITCH
84	* command), even despite the fact that the XFER_DONE interrupt	84	* command), even despite the fact that the XFER_DONE interrupt
85	* was raised. And if another data transfer starts before	85	* was raised. And if another data transfer starts before
86	* this bit comes to good sense (which eventually happens by	86	* this bit comes to good sense (which eventually happens by
87	* itself) then the new transfer simply fails with a timeout.	87	* itself) then the new transfer simply fails with a timeout.
88	*/	88	*/
89	if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {	89	if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
90	ushort hw_state, count = 0;	90	ushort hw_state, count = 0;
91		91
92	start = get_timer(0);	92	start = get_timer(0);
93	do {	93	do {
94	hw_state = mvebu_mmc_read(SDIO_HW_STATE);	94	hw_state = mvebu_mmc_read(SDIO_HW_STATE);
95	if ((get_timer(0) - start) > TIMEOUT_DELAY) {	95	if ((get_timer(0) - start) > TIMEOUT_DELAY) {
96	printf("%s : FIFO_EMPTY bit missing\n",	96	printf("%s : FIFO_EMPTY bit missing\n",
97	DRIVER_NAME);	97	DRIVER_NAME);
98	break;	98	break;
99	}	99	}
100	count++;	100	count++;
101	} while (!(hw_state & CMD_FIFO_EMPTY));	101	} while (!(hw_state & CMD_FIFO_EMPTY));
102	debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",	102	debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
103	DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));	103	DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
104	}	104	}
105		105
106	/* Clear status */	106	/* Clear status */
107	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);	107	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
108	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);	108	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
109		109
110	resptype = SDIO_CMD_INDEX(cmd->cmdidx);	110	resptype = SDIO_CMD_INDEX(cmd->cmdidx);
111		111
112	/* Analyzing resptype/xfertype/waittype for the command */	112	/* Analyzing resptype/xfertype/waittype for the command */
113	if (cmd->resp_type & MMC_RSP_BUSY)	113	if (cmd->resp_type & MMC_RSP_BUSY)
114	resptype \|= SDIO_CMD_RSP_48BUSY;	114	resptype \|= SDIO_CMD_RSP_48BUSY;
115	else if (cmd->resp_type & MMC_RSP_136)	115	else if (cmd->resp_type & MMC_RSP_136)
116	resptype \|= SDIO_CMD_RSP_136;	116	resptype \|= SDIO_CMD_RSP_136;
117	else if (cmd->resp_type & MMC_RSP_PRESENT)	117	else if (cmd->resp_type & MMC_RSP_PRESENT)
118	resptype \|= SDIO_CMD_RSP_48;	118	resptype \|= SDIO_CMD_RSP_48;
119	else	119	else
120	resptype \|= SDIO_CMD_RSP_NONE;	120	resptype \|= SDIO_CMD_RSP_NONE;
121		121
122	if (cmd->resp_type & MMC_RSP_CRC)	122	if (cmd->resp_type & MMC_RSP_CRC)
123	resptype \|= SDIO_CMD_CHECK_CMDCRC;	123	resptype \|= SDIO_CMD_CHECK_CMDCRC;
124		124
125	if (cmd->resp_type & MMC_RSP_OPCODE)	125	if (cmd->resp_type & MMC_RSP_OPCODE)
126	resptype \|= SDIO_CMD_INDX_CHECK;	126	resptype \|= SDIO_CMD_INDX_CHECK;
127		127
128	if (cmd->resp_type & MMC_RSP_PRESENT) {	128	if (cmd->resp_type & MMC_RSP_PRESENT) {
129	resptype \|= SDIO_UNEXPECTED_RESP;	129	resptype \|= SDIO_UNEXPECTED_RESP;
130	waittype \|= SDIO_NOR_UNEXP_RSP;	130	waittype \|= SDIO_NOR_UNEXP_RSP;
131	}	131	}
132		132
133	if (data) {	133	if (data) {
134	int err = mvebu_mmc_setup_data(data);	134	int err = mvebu_mmc_setup_data(data);
135		135
136	if (err) {	136	if (err) {
137	debug("%s: command DATA error :%x\n",	137	debug("%s: command DATA error :%x\n",
138	DRIVER_NAME, err);	138	DRIVER_NAME, err);
139	return err;	139	return err;
140	}	140	}
141		141
142	resptype \|= SDIO_CMD_DATA_PRESENT \| SDIO_CMD_CHECK_DATACRC16;	142	resptype \|= SDIO_CMD_DATA_PRESENT \| SDIO_CMD_CHECK_DATACRC16;
143	xfertype \|= SDIO_XFER_MODE_HW_WR_DATA_EN;	143	xfertype \|= SDIO_XFER_MODE_HW_WR_DATA_EN;
144	if (data->flags & MMC_DATA_READ) {	144	if (data->flags & MMC_DATA_READ) {
145	xfertype \|= SDIO_XFER_MODE_TO_HOST;	145	xfertype \|= SDIO_XFER_MODE_TO_HOST;
146	waittype = SDIO_NOR_DMA_INI;	146	waittype = SDIO_NOR_DMA_INI;
147	} else {	147	} else {
148	waittype \|= SDIO_NOR_XFER_DONE;	148	waittype \|= SDIO_NOR_XFER_DONE;
149	}	149	}
150	} else {	150	} else {
151	waittype \|= SDIO_NOR_CMD_DONE;	151	waittype \|= SDIO_NOR_CMD_DONE;
152	}	152	}
153		153
154	/* Setting cmd arguments */	154	/* Setting cmd arguments */
155	mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);	155	mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
156	mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);	156	mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
157		157
158	/* Setting Xfer mode */	158	/* Setting Xfer mode */
159	mvebu_mmc_write(SDIO_XFER_MODE, xfertype);	159	mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
160		160
161	/* Sending command */	161	/* Sending command */
162	mvebu_mmc_write(SDIO_CMD, resptype);	162	mvebu_mmc_write(SDIO_CMD, resptype);
163		163
164	start = get_timer(0);	164	start = get_timer(0);
165		165
166	while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {	166	while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
167	if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {	167	if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
168	debug("%s: error! cmdidx : %d, err reg: %04x\n",	168	debug("%s: error! cmdidx : %d, err reg: %04x\n",
169	DRIVER_NAME, cmd->cmdidx,	169	DRIVER_NAME, cmd->cmdidx,
170	mvebu_mmc_read(SDIO_ERR_INTR_STATUS));	170	mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
171	if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &	171	if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
172	(SDIO_ERR_CMD_TIMEOUT \| SDIO_ERR_DATA_TIMEOUT)) {	172	(SDIO_ERR_CMD_TIMEOUT \| SDIO_ERR_DATA_TIMEOUT)) {
173	debug("%s: command READ timed out\n",	173	debug("%s: command READ timed out\n",
174	DRIVER_NAME);	174	DRIVER_NAME);
175	return TIMEOUT;	175	return TIMEOUT;
176	}	176	}
177	debug("%s: command READ error\n", DRIVER_NAME);	177	debug("%s: command READ error\n", DRIVER_NAME);
178	return COMM_ERR;	178	return COMM_ERR;
179	}	179	}
180		180
181	if ((get_timer(0) - start) > TIMEOUT_DELAY) {	181	if ((get_timer(0) - start) > TIMEOUT_DELAY) {
182	debug("%s: command timed out\n", DRIVER_NAME);	182	debug("%s: command timed out\n", DRIVER_NAME);
183	return TIMEOUT;	183	return TIMEOUT;
184	}	184	}
185	}	185	}
186		186
187	/* Handling response */	187	/* Handling response */
188	if (cmd->resp_type & MMC_RSP_136) {	188	if (cmd->resp_type & MMC_RSP_136) {
189	uint response[8];	189	uint response[8];
190		190
191	for (resp_indx = 0; resp_indx < 8; resp_indx++)	191	for (resp_indx = 0; resp_indx < 8; resp_indx++)
192	response[resp_indx]	192	response[resp_indx]
193	= mvebu_mmc_read(SDIO_RSP(resp_indx));	193	= mvebu_mmc_read(SDIO_RSP(resp_indx));
194		194
195	cmd->response[0] = ((response[0] & 0x03ff) << 22) \|	195	cmd->response[0] = ((response[0] & 0x03ff) << 22) \|
196	((response[1] & 0xffff) << 6) \|	196	((response[1] & 0xffff) << 6) \|
197	((response[2] & 0xfc00) >> 10);	197	((response[2] & 0xfc00) >> 10);
198	cmd->response[1] = ((response[2] & 0x03ff) << 22) \|	198	cmd->response[1] = ((response[2] & 0x03ff) << 22) \|
199	((response[3] & 0xffff) << 6) \|	199	((response[3] & 0xffff) << 6) \|
200	((response[4] & 0xfc00) >> 10);	200	((response[4] & 0xfc00) >> 10);
201	cmd->response[2] = ((response[4] & 0x03ff) << 22) \|	201	cmd->response[2] = ((response[4] & 0x03ff) << 22) \|
202	((response[5] & 0xffff) << 6) \|	202	((response[5] & 0xffff) << 6) \|
203	((response[6] & 0xfc00) >> 10);	203	((response[6] & 0xfc00) >> 10);
204	cmd->response[3] = ((response[6] & 0x03ff) << 22) \|	204	cmd->response[3] = ((response[6] & 0x03ff) << 22) \|
205	((response[7] & 0x3fff) << 8);	205	((response[7] & 0x3fff) << 8);
206	} else if (cmd->resp_type & MMC_RSP_PRESENT) {	206	} else if (cmd->resp_type & MMC_RSP_PRESENT) {
207	uint response[3];	207	uint response[3];
208		208
209	for (resp_indx = 0; resp_indx < 3; resp_indx++)	209	for (resp_indx = 0; resp_indx < 3; resp_indx++)
210	response[resp_indx]	210	response[resp_indx]
211	= mvebu_mmc_read(SDIO_RSP(resp_indx));	211	= mvebu_mmc_read(SDIO_RSP(resp_indx));
212		212
213	cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) \|	213	cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) \|
214	((response[1] & 0xffff) << (14 - 8)) \|	214	((response[1] & 0xffff) << (14 - 8)) \|
215	((response[0] & 0x03ff) << (30 - 8));	215	((response[0] & 0x03ff) << (30 - 8));
216	cmd->response[1] = ((response[0] & 0xfc00) >> 10);	216	cmd->response[1] = ((response[0] & 0xfc00) >> 10);
217	cmd->response[2] = 0;	217	cmd->response[2] = 0;
218	cmd->response[3] = 0;	218	cmd->response[3] = 0;
219	} else {	219	} else {
220	cmd->response[0] = 0;	220	cmd->response[0] = 0;
221	cmd->response[1] = 0;	221	cmd->response[1] = 0;
222	cmd->response[2] = 0;	222	cmd->response[2] = 0;
223	cmd->response[3] = 0;	223	cmd->response[3] = 0;
224	}	224	}
225		225
226	debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);	226	debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
227	debug("[0x%x] ", cmd->response[0]);	227	debug("[0x%x] ", cmd->response[0]);
228	debug("[0x%x] ", cmd->response[1]);	228	debug("[0x%x] ", cmd->response[1]);
229	debug("[0x%x] ", cmd->response[2]);	229	debug("[0x%x] ", cmd->response[2]);
230	debug("[0x%x] ", cmd->response[3]);	230	debug("[0x%x] ", cmd->response[3]);
231	debug("\n");	231	debug("\n");
232		232
233	if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &	233	if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
234	(SDIO_ERR_CMD_TIMEOUT \| SDIO_ERR_DATA_TIMEOUT))	234	(SDIO_ERR_CMD_TIMEOUT \| SDIO_ERR_DATA_TIMEOUT))
235	return TIMEOUT;	235	return TIMEOUT;
236		236
237	return 0;	237	return 0;
238	}	238	}
239		239
240	static void mvebu_mmc_power_up(void)	240	static void mvebu_mmc_power_up(void)
241	{	241	{
242	debug("%s: power up\n", DRIVER_NAME);	242	debug("%s: power up\n", DRIVER_NAME);
243		243
244	/* disable interrupts */	244	/* disable interrupts */
245	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);	245	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
246	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);	246	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
247		247
248	/* SW reset */	248	/* SW reset */
249	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);	249	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
250		250
251	mvebu_mmc_write(SDIO_XFER_MODE, 0);	251	mvebu_mmc_write(SDIO_XFER_MODE, 0);
252		252
253	/* enable status */	253	/* enable status */
254	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);	254	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
255	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);	255	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
256		256
257	/* enable interrupts status */	257	/* enable interrupts status */
258	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);	258	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
259	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);	259	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
260	}	260	}
261		261
262	static void mvebu_mmc_set_clk(unsigned int clock)	262	static void mvebu_mmc_set_clk(unsigned int clock)
263	{	263	{
264	unsigned int m;	264	unsigned int m;
265		265
266	if (clock == 0) {	266	if (clock == 0) {
267	debug("%s: clock off\n", DRIVER_NAME);	267	debug("%s: clock off\n", DRIVER_NAME);
268	mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);	268	mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
269	mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);	269	mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
270	} else {	270	} else {
271	m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;	271	m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
272	if (m > MVEBU_MMC_BASE_DIV_MAX)	272	if (m > MVEBU_MMC_BASE_DIV_MAX)
273	m = MVEBU_MMC_BASE_DIV_MAX;	273	m = MVEBU_MMC_BASE_DIV_MAX;
274	mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);	274	mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
275	debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);	275	debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
276	}	276	}
277	}	277	}
278		278
279	static void mvebu_mmc_set_bus(unsigned int bus)	279	static void mvebu_mmc_set_bus(unsigned int bus)
280	{	280	{
281	u32 ctrl_reg = 0;	281	u32 ctrl_reg = 0;
282		282
283	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);	283	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
284	ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;	284	ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
285		285
286	switch (bus) {	286	switch (bus) {
287	case 4:	287	case 4:
288	ctrl_reg \|= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;	288	ctrl_reg \|= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
289	break;	289	break;
290	case 1:	290	case 1:
291	default:	291	default:
292	ctrl_reg \|= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;	292	ctrl_reg \|= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
293	}	293	}
294		294
295	/* default transfer mode */	295	/* default transfer mode */
296	ctrl_reg \|= SDIO_HOST_CTRL_BIG_ENDIAN;	296	ctrl_reg \|= SDIO_HOST_CTRL_BIG_ENDIAN;
297	ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;	297	ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
298		298
299	/* default to maximum timeout */	299	/* default to maximum timeout */
300	ctrl_reg \|= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);	300	ctrl_reg \|= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
301	ctrl_reg \|= SDIO_HOST_CTRL_TMOUT_EN;	301	ctrl_reg \|= SDIO_HOST_CTRL_TMOUT_EN;
302		302
303	ctrl_reg \|= SDIO_HOST_CTRL_PUSH_PULL_EN;	303	ctrl_reg \|= SDIO_HOST_CTRL_PUSH_PULL_EN;
304		304
305	ctrl_reg \|= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;	305	ctrl_reg \|= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
306		306
307	debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,	307	debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
308	(ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?	308	(ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
309	"push-pull" : "open-drain",	309	"push-pull" : "open-drain",
310	(ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?	310	(ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
311	"4bit-width" : "1bit-width",	311	"4bit-width" : "1bit-width",
312	(ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?	312	(ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
313	"high-speed" : "");	313	"high-speed" : "");
314		314
315	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);	315	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
316	}	316	}
317		317
318	static void mvebu_mmc_set_ios(struct mmc *mmc)	318	static void mvebu_mmc_set_ios(struct mmc *mmc)
319	{	319	{
320	debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,	320	debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
321	mmc->bus_width, mmc->clock);	321	mmc->bus_width, mmc->clock);
322	mvebu_mmc_set_bus(mmc->bus_width);	322	mvebu_mmc_set_bus(mmc->bus_width);
323	mvebu_mmc_set_clk(mmc->clock);	323	mvebu_mmc_set_clk(mmc->clock);
324	}	324	}
325		325
326	/*	326	/*
327	* Set window register.	327	* Set window register.
328	*/	328	*/
329	static void mvebu_window_setup(void)	329	static void mvebu_window_setup(void)
330	{	330	{
331	int i;	331	int i;
332		332
333	for (i = 0; i < 4; i++) {	333	for (i = 0; i < 4; i++) {
334	mvebu_mmc_write(WINDOW_CTRL(i), 0);	334	mvebu_mmc_write(WINDOW_CTRL(i), 0);
335	mvebu_mmc_write(WINDOW_BASE(i), 0);	335	mvebu_mmc_write(WINDOW_BASE(i), 0);
336	}	336	}
337	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {	337	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
338	u32 size, base, attrib;	338	u32 size, base, attrib;
339		339
340	/* Enable DRAM bank */	340	/* Enable DRAM bank */
341	switch (i) {	341	switch (i) {
342	case 0:	342	case 0:
343	attrib = KWCPU_ATTR_DRAM_CS0;	343	attrib = KWCPU_ATTR_DRAM_CS0;
344	break;	344	break;
345	case 1:	345	case 1:
346	attrib = KWCPU_ATTR_DRAM_CS1;	346	attrib = KWCPU_ATTR_DRAM_CS1;
347	break;	347	break;
348	case 2:	348	case 2:
349	attrib = KWCPU_ATTR_DRAM_CS2;	349	attrib = KWCPU_ATTR_DRAM_CS2;
350	break;	350	break;
351	case 3:	351	case 3:
352	attrib = KWCPU_ATTR_DRAM_CS3;	352	attrib = KWCPU_ATTR_DRAM_CS3;
353	break;	353	break;
354	default:	354	default:
355	/* invalide bank, disable access */	355	/* invalide bank, disable access */
356	attrib = 0;	356	attrib = 0;
357	break;	357	break;
358	}	358	}
359		359
360	size = gd->bd->bi_dram[i].size;	360	size = gd->bd->bi_dram[i].size;
361	base = gd->bd->bi_dram[i].start;	361	base = gd->bd->bi_dram[i].start;
362	if (size && attrib) {	362	if (size && attrib) {
363	mvebu_mmc_write(WINDOW_CTRL(i),	363	mvebu_mmc_write(WINDOW_CTRL(i),
364	MVCPU_WIN_CTRL_DATA(size,	364	MVCPU_WIN_CTRL_DATA(size,
365	MVEBU_TARGET_DRAM,	365	MVEBU_TARGET_DRAM,
366	attrib,	366	attrib,
367	MVCPU_WIN_ENABLE));	367	MVCPU_WIN_ENABLE));
368	} else {	368	} else {
369	mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);	369	mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
370	}	370	}
371	mvebu_mmc_write(WINDOW_BASE(i), base);	371	mvebu_mmc_write(WINDOW_BASE(i), base);
372	}	372	}
373	}	373	}
374		374
375	static int mvebu_mmc_initialize(struct mmc *mmc)	375	static int mvebu_mmc_initialize(struct mmc *mmc)
376	{	376	{
377	debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);	377	debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
378		378
379	/*	379	/*
380	* Setting host parameters	380	* Setting host parameters
381	* Initial Host Ctrl : Timeout : max , Normal Speed mode,	381	* Initial Host Ctrl : Timeout : max , Normal Speed mode,
382	* 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line	382	* 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
383	*/	383	*/
384	mvebu_mmc_write(SDIO_HOST_CTRL,	384	mvebu_mmc_write(SDIO_HOST_CTRL,
385	SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) \|	385	SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) \|
386	SDIO_HOST_CTRL_DATA_WIDTH_4_BITS \|	386	SDIO_HOST_CTRL_DATA_WIDTH_4_BITS \|
387	SDIO_HOST_CTRL_BIG_ENDIAN \|	387	SDIO_HOST_CTRL_BIG_ENDIAN \|
388	SDIO_HOST_CTRL_PUSH_PULL_EN \|	388	SDIO_HOST_CTRL_PUSH_PULL_EN \|
389	SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);	389	SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
390		390
391	mvebu_mmc_write(SDIO_CLK_CTRL, 0);	391	mvebu_mmc_write(SDIO_CLK_CTRL, 0);
392		392
393	/* enable status */	393	/* enable status */
394	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);	394	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
395	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);	395	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
396		396
397	/* disable interrupts */	397	/* disable interrupts */
398	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);	398	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
399	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);	399	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
400		400
401	mvebu_window_setup();	401	mvebu_window_setup();
402		402
403	/* SW reset */	403	/* SW reset */
404	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);	404	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
405		405
406	return 0;	406	return 0;
407	}	407	}
408		408
409	static const struct mmc_ops mvebu_mmc_ops = {	409	static const struct mmc_ops mvebu_mmc_ops = {
410	.send_cmd = mvebu_mmc_send_cmd,	410	.send_cmd = mvebu_mmc_send_cmd,
411	.set_ios = mvebu_mmc_set_ios,	411	.set_ios = mvebu_mmc_set_ios,
412	.init = mvebu_mmc_initialize,	412	.init = mvebu_mmc_initialize,
413	};	413	};
414		414
415	static struct mmc_config mvebu_mmc_cfg = {	415	static struct mmc_config mvebu_mmc_cfg = {
416	.name = DRIVER_NAME,	416	.name = DRIVER_NAME,
417	.ops = &mvebu_mmc_ops,	417	.ops = &mvebu_mmc_ops,
418	.f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,	418	.f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
419	.f_max = MVEBU_MMC_CLOCKRATE_MAX,	419	.f_max = MVEBU_MMC_CLOCKRATE_MAX,
420	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,	420	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
421	.host_caps = MMC_MODE_4BIT \| MMC_MODE_HS \| MMC_MODE_HC \|	421	.host_caps = MMC_MODE_4BIT \| MMC_MODE_HS \|
422	MMC_MODE_HS_52MHz,	422	MMC_MODE_HS_52MHz,
423	.part_type = PART_TYPE_DOS,	423	.part_type = PART_TYPE_DOS,
424	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,	424	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
425	};	425	};
426		426
427	int mvebu_mmc_init(bd_t *bis)	427	int mvebu_mmc_init(bd_t *bis)
428	{	428	{
429	struct mmc *mmc;	429	struct mmc *mmc;
430		430
431	mvebu_mmc_power_up();	431	mvebu_mmc_power_up();
432		432
433	mmc = mmc_create(&mvebu_mmc_cfg, bis);	433	mmc = mmc_create(&mvebu_mmc_cfg, bis);
434	if (mmc == NULL)	434	if (mmc == NULL)
435	return -1;	435	return -1;
436		436
437	return 0;	437	return 0;
438	}	438	}
439		439

drivers/mmc/mxsmmc.c

Diff comments View file @ 5a20397

 /*
  * Freescale i.MX28 SSP MMC driver
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
  *
  * Based on code from LTIB:
  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  * Terry Lv
  *
  * Copyright 2007, Freescale Semiconductor, Inc
  * Andy Fleming
  *
  * Based vaguely on the pxa mmc code:
  * (C) Copyright 2003
  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <malloc.h>
 #include <mmc.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/dma.h>
 #include <bouncebuf.h>
 struct mxsmmc_priv {
 	int			id;
 	struct mxs_ssp_regs	*regs;
 	uint32_t		buswidth;
 	int			(*mmc_is_wp)(int);
 	int			(*mmc_cd)(int);
 	struct mxs_dma_desc	*desc;
 	struct mmc_config	cfg;	/* mmc configuration */
 };
 #define	MXSMMC_MAX_TIMEOUT	10000
 #define MXSMMC_SMALL_TRANSFER	512
 static int mxsmmc_cd(struct mxsmmc_priv *priv)
 {
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	if (priv->mmc_cd)
 		return priv->mmc_cd(priv->id);
 	return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
 }
 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
 {
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	uint32_t *data_ptr;
 	int timeout = MXSMMC_MAX_TIMEOUT;
 	uint32_t reg;
 	uint32_t data_count = data->blocksize * data->blocks;
 	if (data->flags & MMC_DATA_READ) {
 		data_ptr = (uint32_t *)data->dest;
 		while (data_count && --timeout) {
 			reg = readl(&ssp_regs->hw_ssp_status);
 			if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
 				*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
 				data_count -= 4;
 				timeout = MXSMMC_MAX_TIMEOUT;
 			} else
 				udelay(1000);
 		}
 	} else {
 		data_ptr = (uint32_t *)data->src;
 		timeout *= 100;
 		while (data_count && --timeout) {
 			reg = readl(&ssp_regs->hw_ssp_status);
 			if (!(reg & SSP_STATUS_FIFO_FULL)) {
 				writel(*data_ptr++, &ssp_regs->hw_ssp_data);
 				data_count -= 4;
 				timeout = MXSMMC_MAX_TIMEOUT;
 			} else
 				udelay(1000);
 		}
 	}
 	return timeout ? 0 : COMM_ERR;
 }
 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
 {
 	uint32_t data_count = data->blocksize * data->blocks;
 	int dmach;
 	struct mxs_dma_desc *desc = priv->desc;
 	void *addr;
 	unsigned int flags;
 	struct bounce_buffer bbstate;
 	memset(desc, 0, sizeof(struct mxs_dma_desc));
 	desc->address = (dma_addr_t)desc;
 	if (data->flags & MMC_DATA_READ) {
 		priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 		addr = data->dest;
 		flags = GEN_BB_WRITE;
 	} else {
 		priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 		addr = (void *)data->src;
 		flags = GEN_BB_READ;
 	}
 	bounce_buffer_start(&bbstate, addr, data_count, flags);
 	priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
 	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 				(data_count << MXS_DMA_DESC_BYTES_OFFSET);
 	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
 	mxs_dma_desc_append(dmach, priv->desc);
 	if (mxs_dma_go(dmach)) {
 		bounce_buffer_stop(&bbstate);
 		return COMM_ERR;
 	}
 	bounce_buffer_stop(&bbstate);
 	return 0;
 }
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
  * a command pointer, and an optional data pointer.
  */
 static int
 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
 	struct mxsmmc_priv *priv = mmc->priv;
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	uint32_t reg;
 	int timeout;
 	uint32_t ctrl0;
 	int ret;
 	debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
 	/* Check bus busy */
 	timeout = MXSMMC_MAX_TIMEOUT;
 	while (--timeout) {
 		udelay(1000);
 		reg = readl(&ssp_regs->hw_ssp_status);
 		if (!(reg &
 			(SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
 			SSP_STATUS_CMD_BUSY))) {
 			break;
 		}
 	}
 	if (!timeout) {
 		printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
 		return TIMEOUT;
 	}
 	/* See if card is present */
 	if (!mxsmmc_cd(priv)) {
 		printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
 		return NO_CARD_ERR;
 	}
 	/* Start building CTRL0 contents */
 	ctrl0 = priv->buswidth;
 	/* Set up command */
 	if (!(cmd->resp_type & MMC_RSP_CRC))
 		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 	if (cmd->resp_type & MMC_RSP_PRESENT)	/* Need to get response */
 		ctrl0 |= SSP_CTRL0_GET_RESP;
 	if (cmd->resp_type & MMC_RSP_136)	/* It's a 136 bits response */
 		ctrl0 |= SSP_CTRL0_LONG_RESP;
 	if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
 		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 	else
 		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 	/* Command index */
 	reg = readl(&ssp_regs->hw_ssp_cmd0);
 	reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
 	reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		reg |= SSP_CMD0_APPEND_8CYC;
 	writel(reg, &ssp_regs->hw_ssp_cmd0);
 	/* Command argument */
 	writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
 	/* Set up data */
 	if (data) {
 		/* READ or WRITE */
 		if (data->flags & MMC_DATA_READ) {
 			ctrl0 |= SSP_CTRL0_READ;
 		} else if (priv->mmc_is_wp &&
 			priv->mmc_is_wp(mmc->block_dev.dev)) {
 			printf("MMC%d: Can not write a locked card!\n",
 				mmc->block_dev.dev);
 			return UNUSABLE_ERR;
 		}
 		ctrl0 |= SSP_CTRL0_DATA_XFER;
 		reg = data->blocksize * data->blocks;
 #if defined(CONFIG_MX23)
 		ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
 		clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
 			SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
 			((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
 			((ffs(data->blocksize) - 1) <<
 				SSP_CMD0_BLOCK_SIZE_OFFSET));
 #elif defined(CONFIG_MX28)
 		writel(reg, &ssp_regs->hw_ssp_xfer_size);
 		reg = ((data->blocks - 1) <<
 			SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
 			((ffs(data->blocksize) - 1) <<
 			SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
 		writel(reg, &ssp_regs->hw_ssp_block_size);
 #endif
 	}
 	/* Kick off the command */
 	ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
 	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
 	/* Wait for the command to complete */
 	timeout = MXSMMC_MAX_TIMEOUT;
 	while (--timeout) {
 		udelay(1000);
 		reg = readl(&ssp_regs->hw_ssp_status);
 		if (!(reg & SSP_STATUS_CMD_BUSY))
 			break;
 	}
 	if (!timeout) {
 		printf("MMC%d: Command %d busy\n",
 			mmc->block_dev.dev, cmd->cmdidx);
 		return TIMEOUT;
 	}
 	/* Check command timeout */
 	if (reg & SSP_STATUS_RESP_TIMEOUT) {
 		printf("MMC%d: Command %d timeout (status 0x%08x)\n",
 			mmc->block_dev.dev, cmd->cmdidx, reg);
 		return TIMEOUT;
 	}
 	/* Check command errors */
 	if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
 		printf("MMC%d: Command %d error (status 0x%08x)!\n",
 			mmc->block_dev.dev, cmd->cmdidx, reg);
 		return COMM_ERR;
 	}
 	/* Copy response to response buffer */
 	if (cmd->resp_type & MMC_RSP_136) {
 		cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
 		cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
 		cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
 		cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
 	} else
 		cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
 	/* Return if no data to process */
 	if (!data)
 		return 0;
 	if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
 		ret = mxsmmc_send_cmd_pio(priv, data);
 		if (ret) {
 			printf("MMC%d: Data timeout with command %d "
 				"(status 0x%08x)!\n",
 				mmc->block_dev.dev, cmd->cmdidx, reg);
 			return ret;
 		}
 	} else {
 		ret = mxsmmc_send_cmd_dma(priv, data);
 		if (ret) {
 			printf("MMC%d: DMA transfer failed\n",
 				mmc->block_dev.dev);
 			return ret;
 		}
 	}
 	/* Check data errors */
 	reg = readl(&ssp_regs->hw_ssp_status);
 	if (reg &
 		(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
 		SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
 		printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
 			mmc->block_dev.dev, cmd->cmdidx, reg);
 		return COMM_ERR;
 	}
 	return 0;
 }
 static void mxsmmc_set_ios(struct mmc *mmc)
 {
 	struct mxsmmc_priv *priv = mmc->priv;
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	/* Set the clock speed */
 	if (mmc->clock)
 		mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
 	switch (mmc->bus_width) {
 	case 1:
 		priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
 		break;
 	case 4:
 		priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
 		break;
 	case 8:
 		priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
 		break;
 	}
 	/* Set the bus width */
 	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
 			SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
 	debug("MMC%d: Set %d bits bus width\n",
 		mmc->block_dev.dev, mmc->bus_width);
 }
 static int mxsmmc_init(struct mmc *mmc)
 {
 	struct mxsmmc_priv *priv = mmc->priv;
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	/* Reset SSP */
 	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 	/* Reconfigure the SSP block for MMC operation */
 	writel(SSP_CTRL1_SSP_MODE_SD_MMC |
 		SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
 		SSP_CTRL1_DMA_ENABLE |
 		SSP_CTRL1_POLARITY |
 		SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
 		SSP_CTRL1_DATA_CRC_IRQ_EN |
 		SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
 		SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
 		SSP_CTRL1_RESP_ERR_IRQ_EN,
 		&ssp_regs->hw_ssp_ctrl1_set);
 	/* Set initial bit clock 400 KHz */
 	mxs_set_ssp_busclock(priv->id, 400);
 	/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
 	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
 	udelay(200);
 	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
 	return 0;
 }
 static const struct mmc_ops mxsmmc_ops = {
 	.send_cmd	= mxsmmc_send_cmd,
 	.set_ios	= mxsmmc_set_ios,
 	.init		= mxsmmc_init,
 };
 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 {
 	struct mmc *mmc = NULL;
 	struct mxsmmc_priv *priv = NULL;
 	int ret;
 	const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
 	if (!mxs_ssp_bus_id_valid(id))
 		return -ENODEV;
 	priv = malloc(sizeof(struct mxsmmc_priv));
 	if (!priv)
 		return -ENOMEM;
 	priv->desc = mxs_dma_desc_alloc();
 	if (!priv->desc) {
 		free(priv);
 		return -ENOMEM;
 	}
 	ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
 	if (ret)
 		return ret;
 	priv->mmc_is_wp = wp;
 	priv->mmc_cd = cd;
 	priv->id = id;
 	priv->regs = mxs_ssp_regs_by_bus(id);
 	priv->cfg.name = "MXS MMC";
 	priv->cfg.ops = &mxsmmc_ops;
 	priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
-			 MMC_MODE_HS_52MHz | MMC_MODE_HS |
+			 MMC_MODE_HS_52MHz | MMC_MODE_HS;
-			 MMC_MODE_HC;
 	/*
 	 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
 	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
 	 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
 	 * CLOCK_RATE could be any integer from 0 to 255.
 	 */
 	priv->cfg.f_min = 400000;
 	priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
 	priv->cfg.b_max = 0x20;
 	mmc = mmc_create(&priv->cfg, priv);
 	if (mmc == NULL) {
 		mxs_dma_desc_free(priv->desc);
 		free(priv);
 		return -ENOMEM;
 	}
 	return 0;
 }

drivers/mmc/omap_hsmmc.c

Diff comments View file @ 5a20397

 /*
  * (C) Copyright 2008
  * Texas Instruments, <www.ti.com>
  * Sukumar Ghorai <s-ghorai@ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation's version 2 of
  * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <config.h>
 #include <common.h>
 #include <malloc.h>
 #include <mmc.h>
 #include <part.h>
 #include <i2c.h>
 #include <twl4030.h>
 #include <twl6030.h>
 #include <palmas.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 /* simplify defines to OMAP_HSMMC_USE_GPIO */
 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
 #define OMAP_HSMMC_USE_GPIO
 #else
 #undef OMAP_HSMMC_USE_GPIO
 #endif
 /* common definitions for all OMAPs */
 #define SYSCTL_SRC	(1 << 25)
 #define SYSCTL_SRD	(1 << 26)
 struct omap_hsmmc_data {
 	struct hsmmc *base_addr;
 	struct mmc_config cfg;
 #ifdef OMAP_HSMMC_USE_GPIO
 	int cd_gpio;
 	int wp_gpio;
 #endif
 };
 /* If we fail after 1 second wait, something is really bad */
 #define MAX_RETRY_MS	1000
 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 			unsigned int siz);
 #ifdef OMAP_HSMMC_USE_GPIO
 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 {
 	int ret;
 #ifndef CONFIG_DM_GPIO
 	if (!gpio_is_valid(gpio))
 		return -1;
 #endif
 	ret = gpio_request(gpio, label);
 	if (ret)
 		return ret;
 	ret = gpio_direction_input(gpio);
 	if (ret)
 		return ret;
 	return gpio;
 }
 #endif
 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 static void omap4_vmmc_pbias_config(struct mmc *mmc)
 {
 	u32 value = 0;
 	value = readl((*ctrl)->control_pbiaslite);
 	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 	writel(value, (*ctrl)->control_pbiaslite);
 	/* set VMMC to 3V */
 	twl6030_power_mmc_init();
 	value = readl((*ctrl)->control_pbiaslite);
 	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 	writel(value, (*ctrl)->control_pbiaslite);
 }
 #endif
 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 static void omap5_pbias_config(struct mmc *mmc)
 {
 	u32 value = 0;
 	value = readl((*ctrl)->control_pbias);
 	value &= ~SDCARD_PWRDNZ;
 	writel(value, (*ctrl)->control_pbias);
 	udelay(10); /* wait 10 us */
 	value &= ~SDCARD_BIAS_PWRDNZ;
 	writel(value, (*ctrl)->control_pbias);
 	palmas_mmc1_poweron_ldo();
 	value = readl((*ctrl)->control_pbias);
 	value |= SDCARD_BIAS_PWRDNZ;
 	writel(value, (*ctrl)->control_pbias);
 	udelay(150); /* wait 150 us */
 	value |= SDCARD_PWRDNZ;
 	writel(value, (*ctrl)->control_pbias);
 	udelay(150); /* wait 150 us */
 }
 #endif
 static unsigned char mmc_board_init(struct mmc *mmc)
 {
 #if defined(CONFIG_OMAP34XX)
 	t2_t *t2_base = (t2_t *)T2_BASE;
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 	u32 pbias_lite;
 	pbias_lite = readl(&t2_base->pbias_lite);
 	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 	/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 	pbias_lite &= ~PBIASLITEVMODE0;
 #endif
 	writel(pbias_lite, &t2_base->pbias_lite);
 	writel(pbias_lite | PBIASLITEPWRDNZ1 |
 		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 		&t2_base->pbias_lite);
 	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 		&t2_base->devconf0);
 	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 		&t2_base->devconf1);
 	/* Change from default of 52MHz to 26MHz if necessary */
 	if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
 		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 			&t2_base->ctl_prog_io1);
 	writel(readl(&prcm_base->fclken1_core) |
 		EN_MMC1 | EN_MMC2 | EN_MMC3,
 		&prcm_base->fclken1_core);
 	writel(readl(&prcm_base->iclken1_core) |
 		EN_MMC1 | EN_MMC2 | EN_MMC3,
 		&prcm_base->iclken1_core);
 #endif
 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 	/* PBIAS config needed for MMC1 only */
 	if (mmc->block_dev.dev == 0)
 		omap4_vmmc_pbias_config(mmc);
 #endif
 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 	if (mmc->block_dev.dev == 0)
 		omap5_pbias_config(mmc);
 #endif
 	return 0;
 }
 void mmc_init_stream(struct hsmmc *mmc_base)
 {
 	ulong start;
 	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 	writel(MMC_CMD0, &mmc_base->cmd);
 	start = get_timer(0);
 	while (!(readl(&mmc_base->stat) & CC_MASK)) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for cc!\n", __func__);
 			return;
 		}
 	}
 	writel(CC_MASK, &mmc_base->stat)
 		;
 	writel(MMC_CMD0, &mmc_base->cmd)
 		;
 	start = get_timer(0);
 	while (!(readl(&mmc_base->stat) & CC_MASK)) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for cc2!\n", __func__);
 			return;
 		}
 	}
 	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 }
 static int omap_hsmmc_init_setup(struct mmc *mmc)
 {
 	struct hsmmc *mmc_base;
 	unsigned int reg_val;
 	unsigned int dsor;
 	ulong start;
 	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 	mmc_board_init(mmc);
 	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 		&mmc_base->sysconfig);
 	start = get_timer(0);
 	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for cc2!\n", __func__);
 			return TIMEOUT;
 		}
 	}
 	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 	start = get_timer(0);
 	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for softresetall!\n",
 				__func__);
 			return TIMEOUT;
 		}
 	}
 	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 		&mmc_base->capa);
 	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 	dsor = 240;
 	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 	start = get_timer(0);
 	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for ics!\n", __func__);
 			return TIMEOUT;
 		}
 	}
 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 		&mmc_base->ie);
 	mmc_init_stream(mmc_base);
 	return 0;
 }
 /*
  * MMC controller internal finite state machine reset
  *
  * Used to reset command or data internal state machines, using respectively
  * SRC or SRD bit of SYSCTL register
  */
 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 {
 	ulong start;
 	mmc_reg_out(&mmc_base->sysctl, bit, bit);
 	/*
 	 * CMD(DAT) lines reset procedures are slightly different
 	 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 	 * According to OMAP3 TRM:
 	 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 	 * returns to 0x0.
 	 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 	 * procedure steps must be as follows:
 	 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 	 *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 	 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 	 * 3. Wait until the SRC (SRD) bit returns to 0x0
 	 *    (reset procedure is completed).
 	 */
 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 	defined(CONFIG_AM33XX)
 	if (!(readl(&mmc_base->sysctl) & bit)) {
 		start = get_timer(0);
 		while (!(readl(&mmc_base->sysctl) & bit)) {
 			if (get_timer(0) - start > MAX_RETRY_MS)
 				return;
 		}
 	}
 #endif
 	start = get_timer(0);
 	while ((readl(&mmc_base->sysctl) & bit) != 0) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for sysctl %x to clear\n",
 				__func__, bit);
 			return;
 		}
 	}
 }
 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data)
 {
 	struct hsmmc *mmc_base;
 	unsigned int flags, mmc_stat;
 	ulong start;
 	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 	start = get_timer(0);
 	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting on cmd inhibit to clear\n",
 					__func__);
 			return TIMEOUT;
 		}
 	}
 	writel(0xFFFFFFFF, &mmc_base->stat);
 	start = get_timer(0);
 	while (readl(&mmc_base->stat)) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for STAT (%x) to clear\n",
 				__func__, readl(&mmc_base->stat));
 			return TIMEOUT;
 		}
 	}
 	/*
 	 * CMDREG
 	 * CMDIDX[13:8]	: Command index
 	 * DATAPRNT[5]	: Data Present Select
 	 * ENCMDIDX[4]	: Command Index Check Enable
 	 * ENCMDCRC[3]	: Command CRC Check Enable
 	 * RSPTYP[1:0]
 	 *	00 = No Response
 	 *	01 = Length 136
 	 *	10 = Length 48
 	 *	11 = Length 48 Check busy after response
 	 */
 	/* Delay added before checking the status of frq change
 	 * retry not supported by mmc.c(core file)
 	 */
 	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 		udelay(50000); /* wait 50 ms */
 	if (!(cmd->resp_type & MMC_RSP_PRESENT))
 		flags = 0;
 	else if (cmd->resp_type & MMC_RSP_136)
 		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 	else if (cmd->resp_type & MMC_RSP_BUSY)
 		flags = RSP_TYPE_LGHT48B;
 	else
 		flags = RSP_TYPE_LGHT48;
 	/* enable default flags */
 	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 	if (cmd->resp_type & MMC_RSP_CRC)
 		flags |= CCCE_CHECK;
 	if (cmd->resp_type & MMC_RSP_OPCODE)
 		flags |= CICE_CHECK;
 	if (data) {
 		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 			data->blocksize = 512;
 			writel(data->blocksize | (data->blocks << 16),
 							&mmc_base->blk);
 		} else
 			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 		if (data->flags & MMC_DATA_READ)
 			flags |= (DP_DATA | DDIR_READ);
 		else
 			flags |= (DP_DATA | DDIR_WRITE);
 	}
 	writel(cmd->cmdarg, &mmc_base->arg);
 	udelay(20);		/* To fix "No status update" error on eMMC */
 	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 	start = get_timer(0);
 	do {
 		mmc_stat = readl(&mmc_base->stat);
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s : timeout: No status update\n", __func__);
 			return TIMEOUT;
 		}
 	} while (!mmc_stat);
 	if ((mmc_stat & IE_CTO) != 0) {
 		mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 		return TIMEOUT;
 	} else if ((mmc_stat & ERRI_MASK) != 0)
 		return -1;
 	if (mmc_stat & CC_MASK) {
 		writel(CC_MASK, &mmc_base->stat);
 		if (cmd->resp_type & MMC_RSP_PRESENT) {
 			if (cmd->resp_type & MMC_RSP_136) {
 				/* response type 2 */
 				cmd->response[3] = readl(&mmc_base->rsp10);
 				cmd->response[2] = readl(&mmc_base->rsp32);
 				cmd->response[1] = readl(&mmc_base->rsp54);
 				cmd->response[0] = readl(&mmc_base->rsp76);
 			} else
 				/* response types 1, 1b, 3, 4, 5, 6 */
 				cmd->response[0] = readl(&mmc_base->rsp10);
 		}
 	}
 	if (data && (data->flags & MMC_DATA_READ)) {
 		mmc_read_data(mmc_base,	data->dest,
 				data->blocksize * data->blocks);
 	} else if (data && (data->flags & MMC_DATA_WRITE)) {
 		mmc_write_data(mmc_base, data->src,
 				data->blocksize * data->blocks);
 	}
 	return 0;
 }
 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 {
 	unsigned int *output_buf = (unsigned int *)buf;
 	unsigned int mmc_stat;
 	unsigned int count;
 	/*
 	 * Start Polled Read
 	 */
 	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 	count /= 4;
 	while (size) {
 		ulong start = get_timer(0);
 		do {
 			mmc_stat = readl(&mmc_base->stat);
 			if (get_timer(0) - start > MAX_RETRY_MS) {
 				printf("%s: timedout waiting for status!\n",
 						__func__);
 				return TIMEOUT;
 			}
 		} while (mmc_stat == 0);
 		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 		if ((mmc_stat & ERRI_MASK) != 0)
 			return 1;
 		if (mmc_stat & BRR_MASK) {
 			unsigned int k;
 			writel(readl(&mmc_base->stat) | BRR_MASK,
 				&mmc_base->stat);
 			for (k = 0; k < count; k++) {
 				*output_buf = readl(&mmc_base->data);
 				output_buf++;
 			}
 			size -= (count*4);
 		}
 		if (mmc_stat & BWR_MASK)
 			writel(readl(&mmc_base->stat) | BWR_MASK,
 				&mmc_base->stat);
 		if (mmc_stat & TC_MASK) {
 			writel(readl(&mmc_base->stat) | TC_MASK,
 				&mmc_base->stat);
 			break;
 		}
 	}
 	return 0;
 }
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 				unsigned int size)
 {
 	unsigned int *input_buf = (unsigned int *)buf;
 	unsigned int mmc_stat;
 	unsigned int count;
 	/*
 	 * Start Polled Write
 	 */
 	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 	count /= 4;
 	while (size) {
 		ulong start = get_timer(0);
 		do {
 			mmc_stat = readl(&mmc_base->stat);
 			if (get_timer(0) - start > MAX_RETRY_MS) {
 				printf("%s: timedout waiting for status!\n",
 						__func__);
 				return TIMEOUT;
 			}
 		} while (mmc_stat == 0);
 		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 		if ((mmc_stat & ERRI_MASK) != 0)
 			return 1;
 		if (mmc_stat & BWR_MASK) {
 			unsigned int k;
 			writel(readl(&mmc_base->stat) | BWR_MASK,
 					&mmc_base->stat);
 			for (k = 0; k < count; k++) {
 				writel(*input_buf, &mmc_base->data);
 				input_buf++;
 			}
 			size -= (count*4);
 		}
 		if (mmc_stat & BRR_MASK)
 			writel(readl(&mmc_base->stat) | BRR_MASK,
 				&mmc_base->stat);
 		if (mmc_stat & TC_MASK) {
 			writel(readl(&mmc_base->stat) | TC_MASK,
 				&mmc_base->stat);
 			break;
 		}
 	}
 	return 0;
 }
 static void omap_hsmmc_set_ios(struct mmc *mmc)
 {
 	struct hsmmc *mmc_base;
 	unsigned int dsor = 0;
 	ulong start;
 	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 	/* configue bus width */
 	switch (mmc->bus_width) {
 	case 8:
 		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 			&mmc_base->con);
 		break;
 	case 4:
 		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 			&mmc_base->con);
 		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 			&mmc_base->hctl);
 		break;
 	case 1:
 	default:
 		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 			&mmc_base->con);
 		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 			&mmc_base->hctl);
 		break;
 	}
 	/* configure clock with 96Mhz system clock.
 	 */
 	if (mmc->clock != 0) {
 		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 			dsor++;
 	}
 	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 	start = get_timer(0);
 	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
 			printf("%s: timedout waiting for ics!\n", __func__);
 			return;
 		}
 	}
 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 }
 #ifdef OMAP_HSMMC_USE_GPIO
 static int omap_hsmmc_getcd(struct mmc *mmc)
 {
 	struct omap_hsmmc_data *priv_data = mmc->priv;
 	int cd_gpio;
 	/* if no CD return as 1 */
 	cd_gpio = priv_data->cd_gpio;
 	if (cd_gpio < 0)
 		return 1;
 	/* NOTE: assumes card detect signal is active-low */
 	return !gpio_get_value(cd_gpio);
 }
 static int omap_hsmmc_getwp(struct mmc *mmc)
 {
 	struct omap_hsmmc_data *priv_data = mmc->priv;
 	int wp_gpio;
 	/* if no WP return as 0 */
 	wp_gpio = priv_data->wp_gpio;
 	if (wp_gpio < 0)
 		return 0;
 	/* NOTE: assumes write protect signal is active-high */
 	return gpio_get_value(wp_gpio);
 }
 #endif
 static const struct mmc_ops omap_hsmmc_ops = {
 	.send_cmd	= omap_hsmmc_send_cmd,
 	.set_ios	= omap_hsmmc_set_ios,
 	.init		= omap_hsmmc_init_setup,
 #ifdef OMAP_HSMMC_USE_GPIO
 	.getcd		= omap_hsmmc_getcd,
 	.getwp		= omap_hsmmc_getwp,
 #endif
 };
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		int wp_gpio)
 {
 	struct mmc *mmc;
 	struct omap_hsmmc_data *priv_data;
 	struct mmc_config *cfg;
 	uint host_caps_val;
 	priv_data = malloc(sizeof(*priv_data));
 	if (priv_data == NULL)
 		return -1;
-	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
-			     MMC_MODE_HC;
 	switch (dev_index) {
 	case 0:
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 		break;
 #ifdef OMAP_HSMMC2_BASE
 	case 1:
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
      defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
 		defined(CONFIG_HSMMC2_8BIT)
 		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 		host_caps_val |= MMC_MODE_8BIT;
 #endif
 		break;
 #endif
 #ifdef OMAP_HSMMC3_BASE
 	case 2:
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
 		/* Enable 8-bit interface for eMMC on DRA7XX */
 		host_caps_val |= MMC_MODE_8BIT;
 #endif
 		break;
 #endif
 	default:
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 		return 1;
 	}
 #ifdef OMAP_HSMMC_USE_GPIO
 	/* on error gpio values are set to -1, which is what we want */
 	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 	priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 #endif
 	cfg = &priv_data->cfg;
 	cfg->name = "OMAP SD/MMC";
 	cfg->ops = &omap_hsmmc_ops;
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	cfg->host_caps = host_caps_val & ~host_caps_mask;
 	cfg->f_min = 400000;
 	if (f_max != 0)
 		cfg->f_max = f_max;
 	else {
 		if (cfg->host_caps & MMC_MODE_HS) {
 			if (cfg->host_caps & MMC_MODE_HS_52MHz)
 				cfg->f_max = 52000000;
 			else
 				cfg->f_max = 26000000;
 		} else
 			cfg->f_max = 20000000;
 	}
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 #if defined(CONFIG_OMAP34XX)
 	/*
 	 * Silicon revs 2.1 and older do not support multiblock transfers.
 	 */
 	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 		cfg->b_max = 1;
 #endif
 	mmc = mmc_create(cfg, priv_data);
 	if (mmc == NULL)
 		return -1;
 	return 0;
 }

drivers/mmc/s3c_sdi.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* S3C24xx SD/MMC driver	2	* S3C24xx SD/MMC driver
3	*	3	*
4	* Based on OpenMoko S3C24xx driver by Harald Welte <laforge@openmoko.org>	4	* Based on OpenMoko S3C24xx driver by Harald Welte <laforge@openmoko.org>
5	*	5	*
6	* Copyright (C) 2014 Marek Vasut <marex@denx.de>	6	* Copyright (C) 2014 Marek Vasut <marex@denx.de>
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <malloc.h>	12	#include <malloc.h>
13	#include <mmc.h>	13	#include <mmc.h>
14	#include <errno.h>	14	#include <errno.h>
15	#include <asm/arch/s3c24x0_cpu.h>	15	#include <asm/arch/s3c24x0_cpu.h>
16	#include <asm/io.h>	16	#include <asm/io.h>
17	#include <asm/unaligned.h>	17	#include <asm/unaligned.h>
18		18
19	#define S3C2440_SDICON_SDRESET (1 << 8)	19	#define S3C2440_SDICON_SDRESET (1 << 8)
20	#define S3C2410_SDICON_FIFORESET (1 << 1)	20	#define S3C2410_SDICON_FIFORESET (1 << 1)
21	#define S3C2410_SDICON_CLOCKTYPE (1 << 0)	21	#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
22		22
23	#define S3C2410_SDICMDCON_LONGRSP (1 << 10)	23	#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
24	#define S3C2410_SDICMDCON_WAITRSP (1 << 9)	24	#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
25	#define S3C2410_SDICMDCON_CMDSTART (1 << 8)	25	#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
26	#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)	26	#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
27	#define S3C2410_SDICMDCON_INDEX 0x3f	27	#define S3C2410_SDICMDCON_INDEX 0x3f
28		28
29	#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)	29	#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
30	#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)	30	#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
31	#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)	31	#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
32	#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)	32	#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
33		33
34	#define S3C2440_SDIDCON_DS_WORD (2 << 22)	34	#define S3C2440_SDIDCON_DS_WORD (2 << 22)
35	#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)	35	#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
36	#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)	36	#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
37	#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)	37	#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
38	#define S3C2410_SDIDCON_WIDEBUS (1 << 16)	38	#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
39	#define S3C2440_SDIDCON_DATSTART (1 << 14)	39	#define S3C2440_SDIDCON_DATSTART (1 << 14)
40	#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)	40	#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
41	#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)	41	#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
42	#define S3C2410_SDIDCON_BLKNUM 0x7ff	42	#define S3C2410_SDIDCON_BLKNUM 0x7ff
43		43
44	#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)	44	#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
45	#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)	45	#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
46	#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)	46	#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
47	#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)	47	#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
48	#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)	48	#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
49		49
50	#define S3C2410_SDIFSTA_TFHALF (1 << 11)	50	#define S3C2410_SDIFSTA_TFHALF (1 << 11)
51	#define S3C2410_SDIFSTA_COUNTMASK 0x7f	51	#define S3C2410_SDIFSTA_COUNTMASK 0x7f
52		52
53	/*	53	/*
54	* WARNING: We only support one SD IP block.	54	* WARNING: We only support one SD IP block.
55	* NOTE: It's not likely there will ever exist an S3C24xx with two,	55	* NOTE: It's not likely there will ever exist an S3C24xx with two,
56	* at least not in this universe all right.	56	* at least not in this universe all right.
57	*/	57	*/
58	static int wide_bus;	58	static int wide_bus;
59		59
60	static int	60	static int
61	s3cmmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)	61	s3cmmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
62	{	62	{
63	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();	63	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
64	uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta;	64	uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta;
65	uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT;	65	uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT;
66	unsigned int timeout = 100000;	66	unsigned int timeout = 100000;
67	int ret = 0, xfer_len, data_offset = 0;	67	int ret = 0, xfer_len, data_offset = 0;
68	const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL \|	68	const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL \|
69	S3C2410_SDIDSTA_CRCFAIL \| S3C2410_SDIDSTA_RXCRCFAIL \|	69	S3C2410_SDIDSTA_CRCFAIL \| S3C2410_SDIDSTA_RXCRCFAIL \|
70	S3C2410_SDIDSTA_DATATIMEOUT;	70	S3C2410_SDIDSTA_DATATIMEOUT;
71		71
72		72
73	writel(0xffffffff, &sdi_regs->sdicsta);	73	writel(0xffffffff, &sdi_regs->sdicsta);
74	writel(0xffffffff, &sdi_regs->sdidsta);	74	writel(0xffffffff, &sdi_regs->sdidsta);
75	writel(0xffffffff, &sdi_regs->sdifsta);	75	writel(0xffffffff, &sdi_regs->sdifsta);
76		76
77	/* Set up data transfer (if applicable). */	77	/* Set up data transfer (if applicable). */
78	if (data) {	78	if (data) {
79	writel(data->blocksize, &sdi_regs->sdibsize);	79	writel(data->blocksize, &sdi_regs->sdibsize);
80		80
81	sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM;	81	sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM;
82	sdidcon \|= S3C2410_SDIDCON_BLOCKMODE;	82	sdidcon \|= S3C2410_SDIDCON_BLOCKMODE;
83	#if defined(CONFIG_S3C2440)	83	#if defined(CONFIG_S3C2440)
84	sdidcon \|= S3C2440_SDIDCON_DS_WORD \| S3C2440_SDIDCON_DATSTART;	84	sdidcon \|= S3C2440_SDIDCON_DS_WORD \| S3C2440_SDIDCON_DATSTART;
85	#endif	85	#endif
86	if (wide_bus)	86	if (wide_bus)
87	sdidcon \|= S3C2410_SDIDCON_WIDEBUS;	87	sdidcon \|= S3C2410_SDIDCON_WIDEBUS;
88		88
89	if (data->flags & MMC_DATA_READ) {	89	if (data->flags & MMC_DATA_READ) {
90	sdidcon \|= S3C2410_SDIDCON_RXAFTERCMD;	90	sdidcon \|= S3C2410_SDIDCON_RXAFTERCMD;
91	sdidcon \|= S3C2410_SDIDCON_XFER_RXSTART;	91	sdidcon \|= S3C2410_SDIDCON_XFER_RXSTART;
92	} else {	92	} else {
93	sdidcon \|= S3C2410_SDIDCON_TXAFTERRESP;	93	sdidcon \|= S3C2410_SDIDCON_TXAFTERRESP;
94	sdidcon \|= S3C2410_SDIDCON_XFER_TXSTART;	94	sdidcon \|= S3C2410_SDIDCON_XFER_TXSTART;
95	}	95	}
96		96
97	writel(sdidcon, &sdi_regs->sdidcon);	97	writel(sdidcon, &sdi_regs->sdidcon);
98	}	98	}
99		99
100	/* Write CMD arg. */	100	/* Write CMD arg. */
101	writel(cmd->cmdarg, &sdi_regs->sdicarg);	101	writel(cmd->cmdarg, &sdi_regs->sdicarg);
102		102
103	/* Write CMD index. */	103	/* Write CMD index. */
104	sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX;	104	sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX;
105	sdiccon \|= S3C2410_SDICMDCON_SENDERHOST;	105	sdiccon \|= S3C2410_SDICMDCON_SENDERHOST;
106	sdiccon \|= S3C2410_SDICMDCON_CMDSTART;	106	sdiccon \|= S3C2410_SDICMDCON_CMDSTART;
107		107
108	/* Command with short response. */	108	/* Command with short response. */
109	if (cmd->resp_type & MMC_RSP_PRESENT) {	109	if (cmd->resp_type & MMC_RSP_PRESENT) {
110	sdiccon \|= S3C2410_SDICMDCON_WAITRSP;	110	sdiccon \|= S3C2410_SDICMDCON_WAITRSP;
111	sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN;	111	sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN;
112	}	112	}
113		113
114	/* Command with long response. */	114	/* Command with long response. */
115	if (cmd->resp_type & MMC_RSP_136)	115	if (cmd->resp_type & MMC_RSP_136)
116	sdiccon \|= S3C2410_SDICMDCON_LONGRSP;	116	sdiccon \|= S3C2410_SDICMDCON_LONGRSP;
117		117
118	/* Start the command. */	118	/* Start the command. */
119	writel(sdiccon, &sdi_regs->sdiccon);	119	writel(sdiccon, &sdi_regs->sdiccon);
120		120
121	/* Wait for the command to complete or for response. */	121	/* Wait for the command to complete or for response. */
122	for (timeout = 100000; timeout; timeout--) {	122	for (timeout = 100000; timeout; timeout--) {
123	sdicsta = readl(&sdi_regs->sdicsta);	123	sdicsta = readl(&sdi_regs->sdicsta);
124	if (sdicsta & sdicsta_wait_bit)	124	if (sdicsta & sdicsta_wait_bit)
125	break;	125	break;
126		126
127	if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT)	127	if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT)
128	timeout = 1;	128	timeout = 1;
129	}	129	}
130		130
131	/* Clean the status bits. */	131	/* Clean the status bits. */
132	setbits_le32(&sdi_regs->sdicsta, 0xf << 9);	132	setbits_le32(&sdi_regs->sdicsta, 0xf << 9);
133		133
134	if (!timeout) {	134	if (!timeout) {
135	puts("S3C SDI: Command timed out!\n");	135	puts("S3C SDI: Command timed out!\n");
136	ret = TIMEOUT;	136	ret = TIMEOUT;
137	goto error;	137	goto error;
138	}	138	}
139		139
140	/* Read out the response. */	140	/* Read out the response. */
141	if (cmd->resp_type & MMC_RSP_136) {	141	if (cmd->resp_type & MMC_RSP_136) {
142	cmd->response[0] = readl(&sdi_regs->sdirsp0);	142	cmd->response[0] = readl(&sdi_regs->sdirsp0);
143	cmd->response[1] = readl(&sdi_regs->sdirsp1);	143	cmd->response[1] = readl(&sdi_regs->sdirsp1);
144	cmd->response[2] = readl(&sdi_regs->sdirsp2);	144	cmd->response[2] = readl(&sdi_regs->sdirsp2);
145	cmd->response[3] = readl(&sdi_regs->sdirsp3);	145	cmd->response[3] = readl(&sdi_regs->sdirsp3);
146	} else {	146	} else {
147	cmd->response[0] = readl(&sdi_regs->sdirsp0);	147	cmd->response[0] = readl(&sdi_regs->sdirsp0);
148	}	148	}
149		149
150	/* If there are no data, we're done. */	150	/* If there are no data, we're done. */
151	if (!data)	151	if (!data)
152	return 0;	152	return 0;
153		153
154	xfer_len = data->blocksize * data->blocks;	154	xfer_len = data->blocksize * data->blocks;
155		155
156	while (xfer_len > 0) {	156	while (xfer_len > 0) {
157	sdidsta = readl(&sdi_regs->sdidsta);	157	sdidsta = readl(&sdi_regs->sdidsta);
158	sdifsta = readl(&sdi_regs->sdifsta);	158	sdifsta = readl(&sdi_regs->sdifsta);
159		159
160	if (sdidsta & sdidsta_err_mask) {	160	if (sdidsta & sdidsta_err_mask) {
161	printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta);	161	printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta);
162	ret = -EIO;	162	ret = -EIO;
163	goto error;	163	goto error;
164	}	164	}
165		165
166	if (data->flags & MMC_DATA_READ) {	166	if (data->flags & MMC_DATA_READ) {
167	if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4)	167	if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4)
168	continue;	168	continue;
169	sdidat = readl(&sdi_regs->sdidat);	169	sdidat = readl(&sdi_regs->sdidat);
170	put_unaligned_le32(sdidat, data->dest + data_offset);	170	put_unaligned_le32(sdidat, data->dest + data_offset);
171	} else { /* Write */	171	} else { /* Write */
172	/* TX FIFO half full. */	172	/* TX FIFO half full. */
173	if (!(sdifsta & S3C2410_SDIFSTA_TFHALF))	173	if (!(sdifsta & S3C2410_SDIFSTA_TFHALF))
174	continue;	174	continue;
175		175
176	/* TX FIFO is below 32b full, write. */	176	/* TX FIFO is below 32b full, write. */
177	sdidat = get_unaligned_le32(data->src + data_offset);	177	sdidat = get_unaligned_le32(data->src + data_offset);
178	writel(sdidat, &sdi_regs->sdidat);	178	writel(sdidat, &sdi_regs->sdidat);
179	}	179	}
180	data_offset += 4;	180	data_offset += 4;
181	xfer_len -= 4;	181	xfer_len -= 4;
182	}	182	}
183		183
184	/* Wait for the command to complete or for response. */	184	/* Wait for the command to complete or for response. */
185	for (timeout = 100000; timeout; timeout--) {	185	for (timeout = 100000; timeout; timeout--) {
186	sdidsta = readl(&sdi_regs->sdidsta);	186	sdidsta = readl(&sdi_regs->sdidsta);
187	if (sdidsta & S3C2410_SDIDSTA_XFERFINISH)	187	if (sdidsta & S3C2410_SDIDSTA_XFERFINISH)
188	break;	188	break;
189		189
190	if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT)	190	if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT)
191	timeout = 1;	191	timeout = 1;
192	}	192	}
193		193
194	/* Clear status bits. */	194	/* Clear status bits. */
195	writel(0x6f8, &sdi_regs->sdidsta);	195	writel(0x6f8, &sdi_regs->sdidsta);
196		196
197	if (!timeout) {	197	if (!timeout) {
198	puts("S3C SDI: Command timed out!\n");	198	puts("S3C SDI: Command timed out!\n");
199	ret = TIMEOUT;	199	ret = TIMEOUT;
200	goto error;	200	goto error;
201	}	201	}
202		202
203	writel(0, &sdi_regs->sdidcon);	203	writel(0, &sdi_regs->sdidcon);
204		204
205	return 0;	205	return 0;
206	error:	206	error:
207	return ret;	207	return ret;
208	}	208	}
209		209
210	static void s3cmmc_set_ios(struct mmc *mmc)	210	static void s3cmmc_set_ios(struct mmc *mmc)
211	{	211	{
212	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();	212	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
213	uint32_t divider = 0;	213	uint32_t divider = 0;
214		214
215	wide_bus = (mmc->bus_width == 4);	215	wide_bus = (mmc->bus_width == 4);
216		216
217	if (!mmc->clock)	217	if (!mmc->clock)
218	return;	218	return;
219		219
220	divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);	220	divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);
221	if (divider)	221	if (divider)
222	divider--;	222	divider--;
223		223
224	writel(divider, &sdi_regs->sdipre);	224	writel(divider, &sdi_regs->sdipre);
225	mdelay(125);	225	mdelay(125);
226	}	226	}
227		227
228	static int s3cmmc_init(struct mmc *mmc)	228	static int s3cmmc_init(struct mmc *mmc)
229	{	229	{
230	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();	230	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
231	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();	231	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
232		232
233	/* Start the clock. */	233	/* Start the clock. */
234	setbits_le32(&clk_power->clkcon, 1 << 9);	234	setbits_le32(&clk_power->clkcon, 1 << 9);
235		235
236	#if defined(CONFIG_S3C2440)	236	#if defined(CONFIG_S3C2440)
237	writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon);	237	writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon);
238	mdelay(10);	238	mdelay(10);
239	writel(0x7fffff, &sdi_regs->sdidtimer);	239	writel(0x7fffff, &sdi_regs->sdidtimer);
240	#else	240	#else
241	writel(0xffff, &sdi_regs->sdidtimer);	241	writel(0xffff, &sdi_regs->sdidtimer);
242	#endif	242	#endif
243	writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize);	243	writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize);
244	writel(0x0, &sdi_regs->sdiimsk);	244	writel(0x0, &sdi_regs->sdiimsk);
245		245
246	writel(S3C2410_SDICON_FIFORESET \| S3C2410_SDICON_CLOCKTYPE,	246	writel(S3C2410_SDICON_FIFORESET \| S3C2410_SDICON_CLOCKTYPE,
247	&sdi_regs->sdicon);	247	&sdi_regs->sdicon);
248		248
249	mdelay(125);	249	mdelay(125);
250		250
251	return 0;	251	return 0;
252	}	252	}
253		253
254	struct s3cmmc_priv {	254	struct s3cmmc_priv {
255	struct mmc_config cfg;	255	struct mmc_config cfg;
256	int (getcd)(struct mmc );	256	int (getcd)(struct mmc );
257	int (getwp)(struct mmc );	257	int (getwp)(struct mmc );
258	};	258	};
259		259
260	static int s3cmmc_getcd(struct mmc *mmc)	260	static int s3cmmc_getcd(struct mmc *mmc)
261	{	261	{
262	struct s3cmmc_priv *priv = mmc->priv;	262	struct s3cmmc_priv *priv = mmc->priv;
263	if (priv->getcd)	263	if (priv->getcd)
264	return priv->getcd(mmc);	264	return priv->getcd(mmc);
265	else	265	else
266	return 0;	266	return 0;
267	}	267	}
268		268
269	static int s3cmmc_getwp(struct mmc *mmc)	269	static int s3cmmc_getwp(struct mmc *mmc)
270	{	270	{
271	struct s3cmmc_priv *priv = mmc->priv;	271	struct s3cmmc_priv *priv = mmc->priv;
272	if (priv->getwp)	272	if (priv->getwp)
273	return priv->getwp(mmc);	273	return priv->getwp(mmc);
274	else	274	else
275	return 0;	275	return 0;
276	}	276	}
277		277
278	static const struct mmc_ops s3cmmc_ops = {	278	static const struct mmc_ops s3cmmc_ops = {
279	.send_cmd = s3cmmc_send_cmd,	279	.send_cmd = s3cmmc_send_cmd,
280	.set_ios = s3cmmc_set_ios,	280	.set_ios = s3cmmc_set_ios,
281	.init = s3cmmc_init,	281	.init = s3cmmc_init,
282	.getcd = s3cmmc_getcd,	282	.getcd = s3cmmc_getcd,
283	.getwp = s3cmmc_getwp,	283	.getwp = s3cmmc_getwp,
284	};	284	};
285		285
286	int s3cmmc_initialize(bd_t bis, int (getcd)(struct mmc *),	286	int s3cmmc_initialize(bd_t bis, int (getcd)(struct mmc *),
287	int (getwp)(struct mmc ))	287	int (getwp)(struct mmc ))
288	{	288	{
289	struct s3cmmc_priv *priv;	289	struct s3cmmc_priv *priv;
290	struct mmc *mmc;	290	struct mmc *mmc;
291	struct mmc_config *cfg;	291	struct mmc_config *cfg;
292		292
293	priv = calloc(1, sizeof(*priv));	293	priv = calloc(1, sizeof(*priv));
294	if (!priv)	294	if (!priv)
295	return -ENOMEM;	295	return -ENOMEM;
296	cfg = &priv->cfg;	296	cfg = &priv->cfg;
297		297
298	cfg->name = "S3C MMC";	298	cfg->name = "S3C MMC";
299	cfg->ops = &s3cmmc_ops;	299	cfg->ops = &s3cmmc_ops;
300	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;	300	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
301	cfg->host_caps = MMC_MODE_4BIT \| MMC_MODE_HC \| MMC_MODE_HS;	301	cfg->host_caps = MMC_MODE_4BIT \| MMC_MODE_HS;
302	cfg->f_min = 400000;	302	cfg->f_min = 400000;
303	cfg->f_max = get_PCLK() / 2;	303	cfg->f_max = get_PCLK() / 2;
304	cfg->b_max = 0x80;	304	cfg->b_max = 0x80;
305		305
306	#if defined(CONFIG_S3C2410)	306	#if defined(CONFIG_S3C2410)
307	/*	307	/*
308	* S3C2410 has some bug that prevents reliable	308	* S3C2410 has some bug that prevents reliable
309	* operation at higher speed	309	* operation at higher speed
310	*/	310	*/
311	cfg->f_max /= 2;	311	cfg->f_max /= 2;
312	#endif	312	#endif
313		313
314	mmc = mmc_create(cfg, priv);	314	mmc = mmc_create(cfg, priv);
315	if (!mmc) {	315	if (!mmc) {
316	free(priv);	316	free(priv);
317	return -ENOMEM;	317	return -ENOMEM;
318	}	318	}
319		319
320	return 0;	320	return 0;
321	}	321	}
322		322

drivers/mmc/s5p_sdhci.c

Diff comments View file @ 5a20397

 /*
  * (C) Copyright 2012 SAMSUNG Electronics
  * Jaehoon Chung <jh80.chung@samsung.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <malloc.h>
 #include <sdhci.h>
 #include <fdtdec.h>
 #include <libfdt.h>
 #include <asm/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/clk.h>
 #include <errno.h>
 #include <asm/arch/pinmux.h>
 static char *S5P_NAME = "SAMSUNG SDHCI";
 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
 {
 	unsigned long val, ctrl;
 	/*
 	 * SELCLKPADDS[17:16]
 	 * 00 = 2mA
 	 * 01 = 4mA
 	 * 10 = 7mA
 	 * 11 = 9mA
 	 */
 	sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
 	val = sdhci_readl(host, SDHCI_CONTROL2);
 	val &= SDHCI_CTRL2_SELBASECLK_MASK(3);
 	val |=	SDHCI_CTRL2_ENSTAASYNCCLR |
 		SDHCI_CTRL2_ENCMDCNFMSK |
 		SDHCI_CTRL2_ENFBCLKRX |
 		SDHCI_CTRL2_ENCLKOUTHOLD;
 	sdhci_writel(host, val, SDHCI_CONTROL2);
 	/*
 	 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
 	 * FCSel[1:0] : Rx Feedback Clock Delay Control
 	 *	Inverter delay means10ns delay if SDCLK 50MHz setting
 	 *	01 = Delay1 (basic delay)
 	 *	11 = Delay2 (basic delay + 2ns)
 	 *	00 = Delay3 (inverter delay)
 	 *	10 = Delay4 (inverter delay + 2ns)
 	 */
 	val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
 	sdhci_writel(host, val, SDHCI_CONTROL3);
 	/*
 	 * SELBASECLK[5:4]
 	 * 00/01 = HCLK
 	 * 10 = EPLL
 	 * 11 = XTI or XEXTCLK
 	 */
 	ctrl = sdhci_readl(host, SDHCI_CONTROL2);
 	ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
 	ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
 	sdhci_writel(host, ctrl, SDHCI_CONTROL2);
 }
 static int s5p_sdhci_core_init(struct sdhci_host *host)
 {
 	host->name = S5P_NAME;
 	host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
 		SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
 		SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
 	host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 	host->set_control_reg = &s5p_sdhci_set_control_reg;
 	host->set_clock = set_mmc_clk;
-	host->host_caps = MMC_MODE_HC;
 	if (host->bus_width == 8)
 		host->host_caps |= MMC_MODE_8BIT;
 	return add_sdhci(host, 52000000, 400000);
 }
 int s5p_sdhci_init(u32 regbase, int index, int bus_width)
 {
 	struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
 	if (!host) {
 		printf("sdhci__host malloc fail!\n");
 		return 1;
 	}
 	host->ioaddr = (void *)regbase;
 	host->index = index;
 	host->bus_width = bus_width;
 	return s5p_sdhci_core_init(host);
 }
 #ifdef CONFIG_OF_CONTROL
 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
 static int do_sdhci_init(struct sdhci_host *host)
 {
 	int dev_id, flag;
 	int err = 0;
 	flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
 	dev_id = host->index + PERIPH_ID_SDMMC0;
 	if (dm_gpio_is_valid(&host->pwr_gpio)) {
 		dm_gpio_set_value(&host->pwr_gpio, 1);
 		err = exynos_pinmux_config(dev_id, flag);
 		if (err) {
 			debug("MMC not configured\n");
 			return err;
 		}
 	}
 	if (dm_gpio_is_valid(&host->cd_gpio)) {
 		if (dm_gpio_get_value(&host->cd_gpio))
 			return -ENODEV;
 		err = exynos_pinmux_config(dev_id, flag);
 		if (err) {
 			printf("external SD not configured\n");
 			return err;
 		}
 	}
 	return s5p_sdhci_core_init(host);
 }
 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
 {
 	int bus_width, dev_id;
 	unsigned int base;
 	/* Get device id */
 	dev_id = pinmux_decode_periph_id(blob, node);
 	if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
 		debug("MMC: Can't get device id\n");
 		return -1;
 	}
 	host->index = dev_id - PERIPH_ID_SDMMC0;
 	/* Get bus width */
 	bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
 	if (bus_width <= 0) {
 		debug("MMC: Can't get bus-width\n");
 		return -1;
 	}
 	host->bus_width = bus_width;
 	/* Get the base address from the device node */
 	base = fdtdec_get_addr(blob, node, "reg");
 	if (!base) {
 		debug("MMC: Can't get base address\n");
 		return -1;
 	}
 	host->ioaddr = (void *)base;
 	gpio_request_by_name_nodev(blob, node, "pwr-gpios", 0, &host->pwr_gpio,
 				   GPIOD_IS_OUT);
 	gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio,
 				   GPIOD_IS_IN);
 	return 0;
 }
 static int process_nodes(const void *blob, int node_list[], int count)
 {
 	struct sdhci_host *host;
 	int i, node;
 	debug("%s: count = %d\n", __func__, count);
 	/* build sdhci_host[] for each controller */
 	for (i = 0; i < count; i++) {
 		node = node_list[i];
 		if (node <= 0)
 			continue;
 		host = &sdhci_host[i];
 		if (sdhci_get_config(blob, node, host)) {
 			printf("%s: failed to decode dev %d\n",	__func__, i);
 			return -1;
 		}
 		do_sdhci_init(host);
 	}
 	return 0;
 }
 int exynos_mmc_init(const void *blob)
 {
 	int count;
 	int node_list[SDHCI_MAX_HOSTS];
 	count = fdtdec_find_aliases_for_id(blob, "mmc",
 			COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
 			SDHCI_MAX_HOSTS);
 	process_nodes(blob, node_list, count);
 	return 1;
 }
 #endif

drivers/mmc/sh_mmcif.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* MMCIF driver.	2	* MMCIF driver.
3	*	3	*
4	* Copyright (C) 2011 Renesas Solutions Corp.	4	* Copyright (C) 2011 Renesas Solutions Corp.
5	*	5	*
6	* This program is free software; you can redistribute it and/or modify	6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by	7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License.	8	* the Free Software Foundation; either version 2 of the License.
9	*/	9	*/
10		10
11	#include <config.h>	11	#include <config.h>
12	#include <common.h>	12	#include <common.h>
13	#include <watchdog.h>	13	#include <watchdog.h>
14	#include <command.h>	14	#include <command.h>
15	#include <mmc.h>	15	#include <mmc.h>
16	#include <malloc.h>	16	#include <malloc.h>
17	#include <asm/errno.h>	17	#include <asm/errno.h>
18	#include <asm/io.h>	18	#include <asm/io.h>
19	#include "sh_mmcif.h"	19	#include "sh_mmcif.h"
20		20
21	#define DRIVER_NAME "sh_mmcif"	21	#define DRIVER_NAME "sh_mmcif"
22		22
23	static int sh_mmcif_intr(void *dev_id)	23	static int sh_mmcif_intr(void *dev_id)
24	{	24	{
25	struct sh_mmcif_host *host = dev_id;	25	struct sh_mmcif_host *host = dev_id;
26	u32 state = 0;	26	u32 state = 0;
27		27
28	state = sh_mmcif_read(&host->regs->ce_int);	28	state = sh_mmcif_read(&host->regs->ce_int);
29	state &= sh_mmcif_read(&host->regs->ce_int_mask);	29	state &= sh_mmcif_read(&host->regs->ce_int_mask);
30		30
31	if (state & INT_RBSYE) {	31	if (state & INT_RBSYE) {
32	sh_mmcif_write(~(INT_RBSYE \| INT_CRSPE), &host->regs->ce_int);	32	sh_mmcif_write(~(INT_RBSYE \| INT_CRSPE), &host->regs->ce_int);
33	sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);	33	sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
34	goto end;	34	goto end;
35	} else if (state & INT_CRSPE) {	35	} else if (state & INT_CRSPE) {
36	sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);	36	sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
37	sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);	37	sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
38	/* one more interrupt (INT_RBSYE) */	38	/* one more interrupt (INT_RBSYE) */
39	if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)	39	if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
40	return -EAGAIN;	40	return -EAGAIN;
41	goto end;	41	goto end;
42	} else if (state & INT_BUFREN) {	42	} else if (state & INT_BUFREN) {
43	sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);	43	sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
44	sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);	44	sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
45	goto end;	45	goto end;
46	} else if (state & INT_BUFWEN) {	46	} else if (state & INT_BUFWEN) {
47	sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);	47	sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
48	sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);	48	sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
49	goto end;	49	goto end;
50	} else if (state & INT_CMD12DRE) {	50	} else if (state & INT_CMD12DRE) {
51	sh_mmcif_write(~(INT_CMD12DRE \| INT_CMD12RBE \| INT_CMD12CRE \|	51	sh_mmcif_write(~(INT_CMD12DRE \| INT_CMD12RBE \| INT_CMD12CRE \|
52	INT_BUFRE), &host->regs->ce_int);	52	INT_BUFRE), &host->regs->ce_int);
53	sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);	53	sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
54	goto end;	54	goto end;
55	} else if (state & INT_BUFRE) {	55	} else if (state & INT_BUFRE) {
56	sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);	56	sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
57	sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);	57	sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
58	goto end;	58	goto end;
59	} else if (state & INT_DTRANE) {	59	} else if (state & INT_DTRANE) {
60	sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);	60	sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
61	sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);	61	sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
62	goto end;	62	goto end;
63	} else if (state & INT_CMD12RBE) {	63	} else if (state & INT_CMD12RBE) {
64	sh_mmcif_write(~(INT_CMD12RBE \| INT_CMD12CRE),	64	sh_mmcif_write(~(INT_CMD12RBE \| INT_CMD12CRE),
65	&host->regs->ce_int);	65	&host->regs->ce_int);
66	sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);	66	sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
67	goto end;	67	goto end;
68	} else if (state & INT_ERR_STS) {	68	} else if (state & INT_ERR_STS) {
69	/* err interrupts */	69	/* err interrupts */
70	sh_mmcif_write(~state, &host->regs->ce_int);	70	sh_mmcif_write(~state, &host->regs->ce_int);
71	sh_mmcif_bitclr(state, &host->regs->ce_int_mask);	71	sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
72	goto err;	72	goto err;
73	} else	73	} else
74	return -EAGAIN;	74	return -EAGAIN;
75		75
76	err:	76	err:
77	host->sd_error = 1;	77	host->sd_error = 1;
78	debug("%s: int err state = %08x\n", DRIVER_NAME, state);	78	debug("%s: int err state = %08x\n", DRIVER_NAME, state);
79	end:	79	end:
80	host->wait_int = 1;	80	host->wait_int = 1;
81	return 0;	81	return 0;
82	}	82	}
83		83
84	static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)	84	static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
85	{	85	{
86	int timeout = 10000000;	86	int timeout = 10000000;
87		87
88	while (1) {	88	while (1) {
89	timeout--;	89	timeout--;
90	if (timeout < 0) {	90	if (timeout < 0) {
91	printf("timeout\n");	91	printf("timeout\n");
92	return 0;	92	return 0;
93	}	93	}
94		94
95	if (!sh_mmcif_intr(host))	95	if (!sh_mmcif_intr(host))
96	break;	96	break;
97		97
98	udelay(1); /* 1 usec */	98	udelay(1); /* 1 usec */
99	}	99	}
100		100
101	return 1; /* Return value: NOT 0 = complete waiting */	101	return 1; /* Return value: NOT 0 = complete waiting */
102	}	102	}
103		103
104	static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)	104	static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
105	{	105	{
106	sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);	106	sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
107	sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);	107	sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
108		108
109	if (!clk)	109	if (!clk)
110	return;	110	return;
111		111
112	if (clk == CLKDEV_EMMC_DATA)	112	if (clk == CLKDEV_EMMC_DATA)
113	sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);	113	sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
114	else	114	else
115	sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,	115	sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
116	clk) - 1) - 1) << 16,	116	clk) - 1) - 1) << 16,
117	&host->regs->ce_clk_ctrl);	117	&host->regs->ce_clk_ctrl);
118	sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);	118	sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
119	}	119	}
120		120
121	static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)	121	static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
122	{	122	{
123	u32 tmp;	123	u32 tmp;
124		124
125	tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE \|	125	tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE \|
126	CLK_CLEAR);	126	CLK_CLEAR);
127		127
128	sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);	128	sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
129	sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);	129	sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
130	sh_mmcif_bitset(tmp \| SRSPTO_256 \| SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29,	130	sh_mmcif_bitset(tmp \| SRSPTO_256 \| SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29,
131	&host->regs->ce_clk_ctrl);	131	&host->regs->ce_clk_ctrl);
132	/* byte swap on */	132	/* byte swap on */
133	sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);	133	sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
134	}	134	}
135		135
136	static int sh_mmcif_error_manage(struct sh_mmcif_host *host)	136	static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
137	{	137	{
138	u32 state1, state2;	138	u32 state1, state2;
139	int ret, timeout = 10000000;	139	int ret, timeout = 10000000;
140		140
141	host->sd_error = 0;	141	host->sd_error = 0;
142	host->wait_int = 0;	142	host->wait_int = 0;
143		143
144	state1 = sh_mmcif_read(&host->regs->ce_host_sts1);	144	state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
145	state2 = sh_mmcif_read(&host->regs->ce_host_sts2);	145	state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
146	debug("%s: ERR HOST_STS1 = %08x\n", \	146	debug("%s: ERR HOST_STS1 = %08x\n", \
147	DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));	147	DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
148	debug("%s: ERR HOST_STS2 = %08x\n", \	148	debug("%s: ERR HOST_STS2 = %08x\n", \
149	DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));	149	DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
150		150
151	if (state1 & STS1_CMDSEQ) {	151	if (state1 & STS1_CMDSEQ) {
152	debug("%s: Forced end of command sequence\n", DRIVER_NAME);	152	debug("%s: Forced end of command sequence\n", DRIVER_NAME);
153	sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);	153	sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
154	sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);	154	sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
155	while (1) {	155	while (1) {
156	timeout--;	156	timeout--;
157	if (timeout < 0) {	157	if (timeout < 0) {
158	printf(DRIVER_NAME": Forceed end of " \	158	printf(DRIVER_NAME": Forceed end of " \
159	"command sequence timeout err\n");	159	"command sequence timeout err\n");
160	return -EILSEQ;	160	return -EILSEQ;
161	}	161	}
162	if (!(sh_mmcif_read(&host->regs->ce_host_sts1)	162	if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
163	& STS1_CMDSEQ))	163	& STS1_CMDSEQ))
164	break;	164	break;
165	}	165	}
166	sh_mmcif_sync_reset(host);	166	sh_mmcif_sync_reset(host);
167	return -EILSEQ;	167	return -EILSEQ;
168	}	168	}
169		169
170	if (state2 & STS2_CRC_ERR)	170	if (state2 & STS2_CRC_ERR)
171	ret = -EILSEQ;	171	ret = -EILSEQ;
172	else if (state2 & STS2_TIMEOUT_ERR)	172	else if (state2 & STS2_TIMEOUT_ERR)
173	ret = TIMEOUT;	173	ret = TIMEOUT;
174	else	174	else
175	ret = -EILSEQ;	175	ret = -EILSEQ;
176	return ret;	176	return ret;
177	}	177	}
178		178
179	static int sh_mmcif_single_read(struct sh_mmcif_host *host,	179	static int sh_mmcif_single_read(struct sh_mmcif_host *host,
180	struct mmc_data *data)	180	struct mmc_data *data)
181	{	181	{
182	long time;	182	long time;
183	u32 blocksize, i;	183	u32 blocksize, i;
184	unsigned long p = (unsigned long )data->dest;	184	unsigned long p = (unsigned long )data->dest;
185		185
186	if ((unsigned long)p & 0x00000001) {	186	if ((unsigned long)p & 0x00000001) {
187	printf("%s: The data pointer is unaligned.", __func__);	187	printf("%s: The data pointer is unaligned.", __func__);
188	return -EIO;	188	return -EIO;
189	}	189	}
190		190
191	host->wait_int = 0;	191	host->wait_int = 0;
192		192
193	/* buf read enable */	193	/* buf read enable */
194	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);	194	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
195	time = mmcif_wait_interrupt_flag(host);	195	time = mmcif_wait_interrupt_flag(host);
196	if (time == 0 \|\| host->sd_error != 0)	196	if (time == 0 \|\| host->sd_error != 0)
197	return sh_mmcif_error_manage(host);	197	return sh_mmcif_error_manage(host);
198		198
199	host->wait_int = 0;	199	host->wait_int = 0;
200	blocksize = (BLOCK_SIZE_MASK &	200	blocksize = (BLOCK_SIZE_MASK &
201	sh_mmcif_read(&host->regs->ce_block_set)) + 3;	201	sh_mmcif_read(&host->regs->ce_block_set)) + 3;
202	for (i = 0; i < blocksize / 4; i++)	202	for (i = 0; i < blocksize / 4; i++)
203	*p++ = sh_mmcif_read(&host->regs->ce_data);	203	*p++ = sh_mmcif_read(&host->regs->ce_data);
204		204
205	/* buffer read end */	205	/* buffer read end */
206	sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);	206	sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
207	time = mmcif_wait_interrupt_flag(host);	207	time = mmcif_wait_interrupt_flag(host);
208	if (time == 0 \|\| host->sd_error != 0)	208	if (time == 0 \|\| host->sd_error != 0)
209	return sh_mmcif_error_manage(host);	209	return sh_mmcif_error_manage(host);
210		210
211	host->wait_int = 0;	211	host->wait_int = 0;
212	return 0;	212	return 0;
213	}	213	}
214		214
215	static int sh_mmcif_multi_read(struct sh_mmcif_host *host,	215	static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
216	struct mmc_data *data)	216	struct mmc_data *data)
217	{	217	{
218	long time;	218	long time;
219	u32 blocksize, i, j;	219	u32 blocksize, i, j;
220	unsigned long p = (unsigned long )data->dest;	220	unsigned long p = (unsigned long )data->dest;
221		221
222	if ((unsigned long)p & 0x00000001) {	222	if ((unsigned long)p & 0x00000001) {
223	printf("%s: The data pointer is unaligned.", __func__);	223	printf("%s: The data pointer is unaligned.", __func__);
224	return -EIO;	224	return -EIO;
225	}	225	}
226		226
227	host->wait_int = 0;	227	host->wait_int = 0;
228	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);	228	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
229	for (j = 0; j < data->blocks; j++) {	229	for (j = 0; j < data->blocks; j++) {
230	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);	230	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
231	time = mmcif_wait_interrupt_flag(host);	231	time = mmcif_wait_interrupt_flag(host);
232	if (time == 0 \|\| host->sd_error != 0)	232	if (time == 0 \|\| host->sd_error != 0)
233	return sh_mmcif_error_manage(host);	233	return sh_mmcif_error_manage(host);
234		234
235	host->wait_int = 0;	235	host->wait_int = 0;
236	for (i = 0; i < blocksize / 4; i++)	236	for (i = 0; i < blocksize / 4; i++)
237	*p++ = sh_mmcif_read(&host->regs->ce_data);	237	*p++ = sh_mmcif_read(&host->regs->ce_data);
238		238
239	WATCHDOG_RESET();	239	WATCHDOG_RESET();
240	}	240	}
241	return 0;	241	return 0;
242	}	242	}
243		243
244	static int sh_mmcif_single_write(struct sh_mmcif_host *host,	244	static int sh_mmcif_single_write(struct sh_mmcif_host *host,
245	struct mmc_data *data)	245	struct mmc_data *data)
246	{	246	{
247	long time;	247	long time;
248	u32 blocksize, i;	248	u32 blocksize, i;
249	const unsigned long p = (unsigned long )data->dest;	249	const unsigned long p = (unsigned long )data->dest;
250		250
251	if ((unsigned long)p & 0x00000001) {	251	if ((unsigned long)p & 0x00000001) {
252	printf("%s: The data pointer is unaligned.", __func__);	252	printf("%s: The data pointer is unaligned.", __func__);
253	return -EIO;	253	return -EIO;
254	}	254	}
255		255
256	host->wait_int = 0;	256	host->wait_int = 0;
257	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);	257	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
258		258
259	time = mmcif_wait_interrupt_flag(host);	259	time = mmcif_wait_interrupt_flag(host);
260	if (time == 0 \|\| host->sd_error != 0)	260	if (time == 0 \|\| host->sd_error != 0)
261	return sh_mmcif_error_manage(host);	261	return sh_mmcif_error_manage(host);
262		262
263	host->wait_int = 0;	263	host->wait_int = 0;
264	blocksize = (BLOCK_SIZE_MASK &	264	blocksize = (BLOCK_SIZE_MASK &
265	sh_mmcif_read(&host->regs->ce_block_set)) + 3;	265	sh_mmcif_read(&host->regs->ce_block_set)) + 3;
266	for (i = 0; i < blocksize / 4; i++)	266	for (i = 0; i < blocksize / 4; i++)
267	sh_mmcif_write(*p++, &host->regs->ce_data);	267	sh_mmcif_write(*p++, &host->regs->ce_data);
268		268
269	/* buffer write end */	269	/* buffer write end */
270	sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);	270	sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
271		271
272	time = mmcif_wait_interrupt_flag(host);	272	time = mmcif_wait_interrupt_flag(host);
273	if (time == 0 \|\| host->sd_error != 0)	273	if (time == 0 \|\| host->sd_error != 0)
274	return sh_mmcif_error_manage(host);	274	return sh_mmcif_error_manage(host);
275		275
276	host->wait_int = 0;	276	host->wait_int = 0;
277	return 0;	277	return 0;
278	}	278	}
279		279
280	static int sh_mmcif_multi_write(struct sh_mmcif_host *host,	280	static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
281	struct mmc_data *data)	281	struct mmc_data *data)
282	{	282	{
283	long time;	283	long time;
284	u32 i, j, blocksize;	284	u32 i, j, blocksize;
285	const unsigned long p = (unsigned long )data->dest;	285	const unsigned long p = (unsigned long )data->dest;
286		286
287	if ((unsigned long)p & 0x00000001) {	287	if ((unsigned long)p & 0x00000001) {
288	printf("%s: The data pointer is unaligned.", __func__);	288	printf("%s: The data pointer is unaligned.", __func__);
289	return -EIO;	289	return -EIO;
290	}	290	}
291		291
292	host->wait_int = 0;	292	host->wait_int = 0;
293	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);	293	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
294	for (j = 0; j < data->blocks; j++) {	294	for (j = 0; j < data->blocks; j++) {
295	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);	295	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
296		296
297	time = mmcif_wait_interrupt_flag(host);	297	time = mmcif_wait_interrupt_flag(host);
298		298
299	if (time == 0 \|\| host->sd_error != 0)	299	if (time == 0 \|\| host->sd_error != 0)
300	return sh_mmcif_error_manage(host);	300	return sh_mmcif_error_manage(host);
301		301
302	host->wait_int = 0;	302	host->wait_int = 0;
303	for (i = 0; i < blocksize / 4; i++)	303	for (i = 0; i < blocksize / 4; i++)
304	sh_mmcif_write(*p++, &host->regs->ce_data);	304	sh_mmcif_write(*p++, &host->regs->ce_data);
305		305
306	WATCHDOG_RESET();	306	WATCHDOG_RESET();
307	}	307	}
308	return 0;	308	return 0;
309	}	309	}
310		310
311	static void sh_mmcif_get_response(struct sh_mmcif_host *host,	311	static void sh_mmcif_get_response(struct sh_mmcif_host *host,
312	struct mmc_cmd *cmd)	312	struct mmc_cmd *cmd)
313	{	313	{
314	if (cmd->resp_type & MMC_RSP_136) {	314	if (cmd->resp_type & MMC_RSP_136) {
315	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);	315	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
316	cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);	316	cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
317	cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);	317	cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
318	cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);	318	cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
319	debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],	319	debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
320	cmd->response[1], cmd->response[2], cmd->response[3]);	320	cmd->response[1], cmd->response[2], cmd->response[3]);
321	} else {	321	} else {
322	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);	322	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
323	}	323	}
324	}	324	}
325		325
326	static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,	326	static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
327	struct mmc_cmd *cmd)	327	struct mmc_cmd *cmd)
328	{	328	{
329	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);	329	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
330	}	330	}
331		331
332	static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,	332	static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
333	struct mmc_data data, struct mmc_cmd cmd)	333	struct mmc_data data, struct mmc_cmd cmd)
334	{	334	{
335	u32 tmp = 0;	335	u32 tmp = 0;
336	u32 opc = cmd->cmdidx;	336	u32 opc = cmd->cmdidx;
337		337
338	/* Response Type check */	338	/* Response Type check */
339	switch (cmd->resp_type) {	339	switch (cmd->resp_type) {
340	case MMC_RSP_NONE:	340	case MMC_RSP_NONE:
341	tmp \|= CMD_SET_RTYP_NO;	341	tmp \|= CMD_SET_RTYP_NO;
342	break;	342	break;
343	case MMC_RSP_R1:	343	case MMC_RSP_R1:
344	case MMC_RSP_R1b:	344	case MMC_RSP_R1b:
345	case MMC_RSP_R3:	345	case MMC_RSP_R3:
346	tmp \|= CMD_SET_RTYP_6B;	346	tmp \|= CMD_SET_RTYP_6B;
347	break;	347	break;
348	case MMC_RSP_R2:	348	case MMC_RSP_R2:
349	tmp \|= CMD_SET_RTYP_17B;	349	tmp \|= CMD_SET_RTYP_17B;
350	break;	350	break;
351	default:	351	default:
352	printf(DRIVER_NAME": Not support type response.\n");	352	printf(DRIVER_NAME": Not support type response.\n");
353	break;	353	break;
354	}	354	}
355		355
356	/* RBSY */	356	/* RBSY */
357	if (opc == MMC_CMD_SWITCH)	357	if (opc == MMC_CMD_SWITCH)
358	tmp \|= CMD_SET_RBSY;	358	tmp \|= CMD_SET_RBSY;
359		359
360	/* WDAT / DATW */	360	/* WDAT / DATW */
361	if (host->data) {	361	if (host->data) {
362	tmp \|= CMD_SET_WDAT;	362	tmp \|= CMD_SET_WDAT;
363	switch (host->bus_width) {	363	switch (host->bus_width) {
364	case MMC_BUS_WIDTH_1:	364	case MMC_BUS_WIDTH_1:
365	tmp \|= CMD_SET_DATW_1;	365	tmp \|= CMD_SET_DATW_1;
366	break;	366	break;
367	case MMC_BUS_WIDTH_4:	367	case MMC_BUS_WIDTH_4:
368	tmp \|= CMD_SET_DATW_4;	368	tmp \|= CMD_SET_DATW_4;
369	break;	369	break;
370	case MMC_BUS_WIDTH_8:	370	case MMC_BUS_WIDTH_8:
371	tmp \|= CMD_SET_DATW_8;	371	tmp \|= CMD_SET_DATW_8;
372	break;	372	break;
373	default:	373	default:
374	printf(DRIVER_NAME": Not support bus width.\n");	374	printf(DRIVER_NAME": Not support bus width.\n");
375	break;	375	break;
376	}	376	}
377	}	377	}
378	/* DWEN */	378	/* DWEN */
379	if (opc == MMC_CMD_WRITE_SINGLE_BLOCK \|\|	379	if (opc == MMC_CMD_WRITE_SINGLE_BLOCK \|\|
380	opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)	380	opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
381	tmp \|= CMD_SET_DWEN;	381	tmp \|= CMD_SET_DWEN;
382	/* CMLTE/CMD12EN */	382	/* CMLTE/CMD12EN */
383	if (opc == MMC_CMD_READ_MULTIPLE_BLOCK \|\|	383	if (opc == MMC_CMD_READ_MULTIPLE_BLOCK \|\|
384	opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {	384	opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
385	tmp \|= CMD_SET_CMLTE \| CMD_SET_CMD12EN;	385	tmp \|= CMD_SET_CMLTE \| CMD_SET_CMD12EN;
386	sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);	386	sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
387	}	387	}
388	/* RIDXC[1:0] check bits */	388	/* RIDXC[1:0] check bits */
389	if (opc == MMC_CMD_SEND_OP_COND \|\| opc == MMC_CMD_ALL_SEND_CID \|\|	389	if (opc == MMC_CMD_SEND_OP_COND \|\| opc == MMC_CMD_ALL_SEND_CID \|\|
390	opc == MMC_CMD_SEND_CSD \|\| opc == MMC_CMD_SEND_CID)	390	opc == MMC_CMD_SEND_CSD \|\| opc == MMC_CMD_SEND_CID)
391	tmp \|= CMD_SET_RIDXC_BITS;	391	tmp \|= CMD_SET_RIDXC_BITS;
392	/* RCRC7C[1:0] check bits */	392	/* RCRC7C[1:0] check bits */
393	if (opc == MMC_CMD_SEND_OP_COND)	393	if (opc == MMC_CMD_SEND_OP_COND)
394	tmp \|= CMD_SET_CRC7C_BITS;	394	tmp \|= CMD_SET_CRC7C_BITS;
395	/* RCRC7C[1:0] internal CRC7 */	395	/* RCRC7C[1:0] internal CRC7 */
396	if (opc == MMC_CMD_ALL_SEND_CID \|\|	396	if (opc == MMC_CMD_ALL_SEND_CID \|\|
397	opc == MMC_CMD_SEND_CSD \|\| opc == MMC_CMD_SEND_CID)	397	opc == MMC_CMD_SEND_CSD \|\| opc == MMC_CMD_SEND_CID)
398	tmp \|= CMD_SET_CRC7C_INTERNAL;	398	tmp \|= CMD_SET_CRC7C_INTERNAL;
399		399
400	return opc = ((opc << 24) \| tmp);	400	return opc = ((opc << 24) \| tmp);
401	}	401	}
402		402
403	static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,	403	static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
404	struct mmc_data *data, u16 opc)	404	struct mmc_data *data, u16 opc)
405	{	405	{
406	u32 ret;	406	u32 ret;
407		407
408	switch (opc) {	408	switch (opc) {
409	case MMC_CMD_READ_MULTIPLE_BLOCK:	409	case MMC_CMD_READ_MULTIPLE_BLOCK:
410	ret = sh_mmcif_multi_read(host, data);	410	ret = sh_mmcif_multi_read(host, data);
411	break;	411	break;
412	case MMC_CMD_WRITE_MULTIPLE_BLOCK:	412	case MMC_CMD_WRITE_MULTIPLE_BLOCK:
413	ret = sh_mmcif_multi_write(host, data);	413	ret = sh_mmcif_multi_write(host, data);
414	break;	414	break;
415	case MMC_CMD_WRITE_SINGLE_BLOCK:	415	case MMC_CMD_WRITE_SINGLE_BLOCK:
416	ret = sh_mmcif_single_write(host, data);	416	ret = sh_mmcif_single_write(host, data);
417	break;	417	break;
418	case MMC_CMD_READ_SINGLE_BLOCK:	418	case MMC_CMD_READ_SINGLE_BLOCK:
419	case MMC_CMD_SEND_EXT_CSD:	419	case MMC_CMD_SEND_EXT_CSD:
420	ret = sh_mmcif_single_read(host, data);	420	ret = sh_mmcif_single_read(host, data);
421	break;	421	break;
422	default:	422	default:
423	printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);	423	printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
424	ret = -EINVAL;	424	ret = -EINVAL;
425	break;	425	break;
426	}	426	}
427	return ret;	427	return ret;
428	}	428	}
429		429
430	static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,	430	static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
431	struct mmc_data data, struct mmc_cmd cmd)	431	struct mmc_data data, struct mmc_cmd cmd)
432	{	432	{
433	long time;	433	long time;
434	int ret = 0, mask = 0;	434	int ret = 0, mask = 0;
435	u32 opc = cmd->cmdidx;	435	u32 opc = cmd->cmdidx;
436		436
437	if (opc == MMC_CMD_STOP_TRANSMISSION) {	437	if (opc == MMC_CMD_STOP_TRANSMISSION) {
438	/* MMCIF sends the STOP command automatically */	438	/* MMCIF sends the STOP command automatically */
439	if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)	439	if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
440	sh_mmcif_bitset(MASK_MCMD12DRE,	440	sh_mmcif_bitset(MASK_MCMD12DRE,
441	&host->regs->ce_int_mask);	441	&host->regs->ce_int_mask);
442	else	442	else
443	sh_mmcif_bitset(MASK_MCMD12RBE,	443	sh_mmcif_bitset(MASK_MCMD12RBE,
444	&host->regs->ce_int_mask);	444	&host->regs->ce_int_mask);
445		445
446	time = mmcif_wait_interrupt_flag(host);	446	time = mmcif_wait_interrupt_flag(host);
447	if (time == 0 \|\| host->sd_error != 0)	447	if (time == 0 \|\| host->sd_error != 0)
448	return sh_mmcif_error_manage(host);	448	return sh_mmcif_error_manage(host);
449		449
450	sh_mmcif_get_cmd12response(host, cmd);	450	sh_mmcif_get_cmd12response(host, cmd);
451	return 0;	451	return 0;
452	}	452	}
453	if (opc == MMC_CMD_SWITCH)	453	if (opc == MMC_CMD_SWITCH)
454	mask = MASK_MRBSYE;	454	mask = MASK_MRBSYE;
455	else	455	else
456	mask = MASK_MCRSPE;	456	mask = MASK_MCRSPE;
457		457
458	mask \|= MASK_MCMDVIO \| MASK_MBUFVIO \| MASK_MWDATERR \|	458	mask \|= MASK_MCMDVIO \| MASK_MBUFVIO \| MASK_MWDATERR \|
459	MASK_MRDATERR \| MASK_MRIDXERR \| MASK_MRSPERR \|	459	MASK_MRDATERR \| MASK_MRIDXERR \| MASK_MRSPERR \|
460	MASK_MCCSTO \| MASK_MCRCSTO \| MASK_MWDATTO \|	460	MASK_MCCSTO \| MASK_MCRCSTO \| MASK_MWDATTO \|
461	MASK_MRDATTO \| MASK_MRBSYTO \| MASK_MRSPTO;	461	MASK_MRDATTO \| MASK_MRBSYTO \| MASK_MRSPTO;
462		462
463	if (host->data) {	463	if (host->data) {
464	sh_mmcif_write(0, &host->regs->ce_block_set);	464	sh_mmcif_write(0, &host->regs->ce_block_set);
465	sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);	465	sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
466	}	466	}
467	opc = sh_mmcif_set_cmd(host, data, cmd);	467	opc = sh_mmcif_set_cmd(host, data, cmd);
468		468
469	sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);	469	sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
470	sh_mmcif_write(mask, &host->regs->ce_int_mask);	470	sh_mmcif_write(mask, &host->regs->ce_int_mask);
471		471
472	debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);	472	debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
473	/* set arg */	473	/* set arg */
474	sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);	474	sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
475	host->wait_int = 0;	475	host->wait_int = 0;
476	/* set cmd */	476	/* set cmd */
477	sh_mmcif_write(opc, &host->regs->ce_cmd_set);	477	sh_mmcif_write(opc, &host->regs->ce_cmd_set);
478		478
479	time = mmcif_wait_interrupt_flag(host);	479	time = mmcif_wait_interrupt_flag(host);
480	if (time == 0)	480	if (time == 0)
481	return sh_mmcif_error_manage(host);	481	return sh_mmcif_error_manage(host);
482		482
483	if (host->sd_error) {	483	if (host->sd_error) {
484	switch (cmd->cmdidx) {	484	switch (cmd->cmdidx) {
485	case MMC_CMD_ALL_SEND_CID:	485	case MMC_CMD_ALL_SEND_CID:
486	case MMC_CMD_SELECT_CARD:	486	case MMC_CMD_SELECT_CARD:
487	case MMC_CMD_APP_CMD:	487	case MMC_CMD_APP_CMD:
488	ret = TIMEOUT;	488	ret = TIMEOUT;
489	break;	489	break;
490	default:	490	default:
491	printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);	491	printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
492	ret = sh_mmcif_error_manage(host);	492	ret = sh_mmcif_error_manage(host);
493	break;	493	break;
494	}	494	}
495	host->sd_error = 0;	495	host->sd_error = 0;
496	host->wait_int = 0;	496	host->wait_int = 0;
497	return ret;	497	return ret;
498	}	498	}
499		499
500	/* if no response */	500	/* if no response */
501	if (!(opc & 0x00C00000))	501	if (!(opc & 0x00C00000))
502	return 0;	502	return 0;
503		503
504	if (host->wait_int == 1) {	504	if (host->wait_int == 1) {
505	sh_mmcif_get_response(host, cmd);	505	sh_mmcif_get_response(host, cmd);
506	host->wait_int = 0;	506	host->wait_int = 0;
507	}	507	}
508	if (host->data)	508	if (host->data)
509	ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);	509	ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
510	host->last_cmd = cmd->cmdidx;	510	host->last_cmd = cmd->cmdidx;
511		511
512	return ret;	512	return ret;
513	}	513	}
514		514
515	static int sh_mmcif_request(struct mmc mmc, struct mmc_cmd cmd,	515	static int sh_mmcif_request(struct mmc mmc, struct mmc_cmd cmd,
516	struct mmc_data *data)	516	struct mmc_data *data)
517	{	517	{
518	struct sh_mmcif_host *host = mmc->priv;	518	struct sh_mmcif_host *host = mmc->priv;
519	int ret;	519	int ret;
520		520
521	WATCHDOG_RESET();	521	WATCHDOG_RESET();
522		522
523	switch (cmd->cmdidx) {	523	switch (cmd->cmdidx) {
524	case MMC_CMD_APP_CMD:	524	case MMC_CMD_APP_CMD:
525	return TIMEOUT;	525	return TIMEOUT;
526	case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */	526	case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
527	if (data)	527	if (data)
528	/* ext_csd */	528	/* ext_csd */
529	break;	529	break;
530	else	530	else
531	/* send_if_cond cmd (not support) */	531	/* send_if_cond cmd (not support) */
532	return TIMEOUT;	532	return TIMEOUT;
533	default:	533	default:
534	break;	534	break;
535	}	535	}
536	host->sd_error = 0;	536	host->sd_error = 0;
537	host->data = data;	537	host->data = data;
538	ret = sh_mmcif_start_cmd(host, data, cmd);	538	ret = sh_mmcif_start_cmd(host, data, cmd);
539	host->data = NULL;	539	host->data = NULL;
540		540
541	return ret;	541	return ret;
542	}	542	}
543		543
544	static void sh_mmcif_set_ios(struct mmc *mmc)	544	static void sh_mmcif_set_ios(struct mmc *mmc)
545	{	545	{
546	struct sh_mmcif_host *host = mmc->priv;	546	struct sh_mmcif_host *host = mmc->priv;
547		547
548	if (mmc->clock)	548	if (mmc->clock)
549	sh_mmcif_clock_control(host, mmc->clock);	549	sh_mmcif_clock_control(host, mmc->clock);
550		550
551	if (mmc->bus_width == 8)	551	if (mmc->bus_width == 8)
552	host->bus_width = MMC_BUS_WIDTH_8;	552	host->bus_width = MMC_BUS_WIDTH_8;
553	else if (mmc->bus_width == 4)	553	else if (mmc->bus_width == 4)
554	host->bus_width = MMC_BUS_WIDTH_4;	554	host->bus_width = MMC_BUS_WIDTH_4;
555	else	555	else
556	host->bus_width = MMC_BUS_WIDTH_1;	556	host->bus_width = MMC_BUS_WIDTH_1;
557		557
558	debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);	558	debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
559	}	559	}
560		560
561	static int sh_mmcif_init(struct mmc *mmc)	561	static int sh_mmcif_init(struct mmc *mmc)
562	{	562	{
563	struct sh_mmcif_host *host = mmc->priv;	563	struct sh_mmcif_host *host = mmc->priv;
564		564
565	sh_mmcif_sync_reset(host);	565	sh_mmcif_sync_reset(host);
566	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);	566	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
567	return 0;	567	return 0;
568	}	568	}
569		569
570	static const struct mmc_ops sh_mmcif_ops = {	570	static const struct mmc_ops sh_mmcif_ops = {
571	.send_cmd = sh_mmcif_request,	571	.send_cmd = sh_mmcif_request,
572	.set_ios = sh_mmcif_set_ios,	572	.set_ios = sh_mmcif_set_ios,
573	.init = sh_mmcif_init,	573	.init = sh_mmcif_init,
574	};	574	};
575		575
576	static struct mmc_config sh_mmcif_cfg = {	576	static struct mmc_config sh_mmcif_cfg = {
577	.name = DRIVER_NAME,	577	.name = DRIVER_NAME,
578	.ops = &sh_mmcif_ops,	578	.ops = &sh_mmcif_ops,
579	.host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT \|	579	.host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT \|
580	MMC_MODE_8BIT \| MMC_MODE_HC,	580	MMC_MODE_8BIT,
581	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,	581	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
582	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,	582	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
583	};	583	};
584		584
585	int mmcif_mmc_init(void)	585	int mmcif_mmc_init(void)
586	{	586	{
587	struct mmc *mmc;	587	struct mmc *mmc;
588	struct sh_mmcif_host *host = NULL;	588	struct sh_mmcif_host *host = NULL;
589		589
590	host = malloc(sizeof(struct sh_mmcif_host));	590	host = malloc(sizeof(struct sh_mmcif_host));
591	if (!host)	591	if (!host)
592	return -ENOMEM;	592	return -ENOMEM;
593	memset(host, 0, sizeof(*host));	593	memset(host, 0, sizeof(*host));
594		594
595	host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;	595	host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
596	host->clk = CONFIG_SH_MMCIF_CLK;	596	host->clk = CONFIG_SH_MMCIF_CLK;
597		597
598	sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);	598	sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
599	sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);	599	sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
600		600
601	mmc = mmc_create(&sh_mmcif_cfg, host);	601	mmc = mmc_create(&sh_mmcif_cfg, host);
602	if (mmc == NULL) {	602	if (mmc == NULL) {
603	free(host);	603	free(host);
604	return -ENOMEM;	604	return -ENOMEM;
605	}	605	}
606		606
607	return 0;	607	return 0;
608	}	608	}
609		609

drivers/mmc/sunxi_mmc.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* (C) Copyright 2007-2011	2	* (C) Copyright 2007-2011
3	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>	3	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4	* Aaron <leafy.myeh@allwinnertech.com>	4	* Aaron <leafy.myeh@allwinnertech.com>
5	*	5	*
6	* MMC driver for allwinner sunxi platform.	6	* MMC driver for allwinner sunxi platform.
7	*	7	*
8	* SPDX-License-Identifier: GPL-2.0+	8	* SPDX-License-Identifier: GPL-2.0+
9	*/	9	*/
10		10
11	#include <common.h>	11	#include <common.h>
12	#include <malloc.h>	12	#include <malloc.h>
13	#include <mmc.h>	13	#include <mmc.h>
14	#include <asm/io.h>	14	#include <asm/io.h>
15	#include <asm/arch/clock.h>	15	#include <asm/arch/clock.h>
16	#include <asm/arch/cpu.h>	16	#include <asm/arch/cpu.h>
17	#include <asm/arch/gpio.h>	17	#include <asm/arch/gpio.h>
18	#include <asm/arch/mmc.h>	18	#include <asm/arch/mmc.h>
19	#include <asm-generic/gpio.h>	19	#include <asm-generic/gpio.h>
20		20
21	struct sunxi_mmc_host {	21	struct sunxi_mmc_host {
22	unsigned mmc_no;	22	unsigned mmc_no;
23	uint32_t *mclkreg;	23	uint32_t *mclkreg;
24	unsigned fatal_err;	24	unsigned fatal_err;
25	struct sunxi_mmc *reg;	25	struct sunxi_mmc *reg;
26	struct mmc_config cfg;	26	struct mmc_config cfg;
27	};	27	};
28		28
29	/* support 4 mmc hosts */	29	/* support 4 mmc hosts */
30	struct sunxi_mmc_host mmc_host[4];	30	struct sunxi_mmc_host mmc_host[4];
31		31
32	static int sunxi_mmc_getcd_gpio(int sdc_no)	32	static int sunxi_mmc_getcd_gpio(int sdc_no)
33	{	33	{
34	switch (sdc_no) {	34	switch (sdc_no) {
35	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);	35	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
36	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);	36	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
37	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);	37	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
38	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);	38	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
39	}	39	}
40	return -1;	40	return -1;
41	}	41	}
42		42
43	static int mmc_resource_init(int sdc_no)	43	static int mmc_resource_init(int sdc_no)
44	{	44	{
45	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];	45	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
46	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;	46	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;
47	int cd_pin, ret = 0;	47	int cd_pin, ret = 0;
48		48
49	debug("init mmc %d resource\n", sdc_no);	49	debug("init mmc %d resource\n", sdc_no);
50		50
51	switch (sdc_no) {	51	switch (sdc_no) {
52	case 0:	52	case 0:
53	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;	53	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
54	mmchost->mclkreg = &ccm->sd0_clk_cfg;	54	mmchost->mclkreg = &ccm->sd0_clk_cfg;
55	break;	55	break;
56	case 1:	56	case 1:
57	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;	57	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
58	mmchost->mclkreg = &ccm->sd1_clk_cfg;	58	mmchost->mclkreg = &ccm->sd1_clk_cfg;
59	break;	59	break;
60	case 2:	60	case 2:
61	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;	61	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
62	mmchost->mclkreg = &ccm->sd2_clk_cfg;	62	mmchost->mclkreg = &ccm->sd2_clk_cfg;
63	break;	63	break;
64	case 3:	64	case 3:
65	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;	65	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
66	mmchost->mclkreg = &ccm->sd3_clk_cfg;	66	mmchost->mclkreg = &ccm->sd3_clk_cfg;
67	break;	67	break;
68	default:	68	default:
69	printf("Wrong mmc number %d\n", sdc_no);	69	printf("Wrong mmc number %d\n", sdc_no);
70	return -1;	70	return -1;
71	}	71	}
72	mmchost->mmc_no = sdc_no;	72	mmchost->mmc_no = sdc_no;
73		73
74	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);	74	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
75	if (cd_pin != -1) {	75	if (cd_pin != -1) {
76	ret = gpio_request(cd_pin, "mmc_cd");	76	ret = gpio_request(cd_pin, "mmc_cd");
77	if (!ret)	77	if (!ret)
78	ret = gpio_direction_input(cd_pin);	78	ret = gpio_direction_input(cd_pin);
79	}	79	}
80		80
81	return ret;	81	return ret;
82	}	82	}
83		83
84	static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)	84	static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
85	{	85	{
86	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;	86	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
87		87
88	if (hz <= 24000000) {	88	if (hz <= 24000000) {
89	pll = CCM_MMC_CTRL_OSCM24;	89	pll = CCM_MMC_CTRL_OSCM24;
90	pll_hz = 24000000;	90	pll_hz = 24000000;
91	} else {	91	} else {
92	#ifdef CONFIG_MACH_SUN9I	92	#ifdef CONFIG_MACH_SUN9I
93	pll = CCM_MMC_CTRL_PLL_PERIPH0;	93	pll = CCM_MMC_CTRL_PLL_PERIPH0;
94	pll_hz = clock_get_pll4_periph0();	94	pll_hz = clock_get_pll4_periph0();
95	#else	95	#else
96	pll = CCM_MMC_CTRL_PLL6;	96	pll = CCM_MMC_CTRL_PLL6;
97	pll_hz = clock_get_pll6();	97	pll_hz = clock_get_pll6();
98	#endif	98	#endif
99	}	99	}
100		100
101	div = pll_hz / hz;	101	div = pll_hz / hz;
102	if (pll_hz % hz)	102	if (pll_hz % hz)
103	div++;	103	div++;
104		104
105	n = 0;	105	n = 0;
106	while (div > 16) {	106	while (div > 16) {
107	n++;	107	n++;
108	div = (div + 1) / 2;	108	div = (div + 1) / 2;
109	}	109	}
110		110
111	if (n > 3) {	111	if (n > 3) {
112	printf("mmc %u error cannot set clock to %u\n",	112	printf("mmc %u error cannot set clock to %u\n",
113	mmchost->mmc_no, hz);	113	mmchost->mmc_no, hz);
114	return -1;	114	return -1;
115	}	115	}
116		116
117	/* determine delays */	117	/* determine delays */
118	if (hz <= 400000) {	118	if (hz <= 400000) {
119	oclk_dly = 0;	119	oclk_dly = 0;
120	sclk_dly = 7;	120	sclk_dly = 7;
121	} else if (hz <= 25000000) {	121	} else if (hz <= 25000000) {
122	oclk_dly = 0;	122	oclk_dly = 0;
123	sclk_dly = 5;	123	sclk_dly = 5;
124	} else if (hz <= 50000000) {	124	} else if (hz <= 50000000) {
125	oclk_dly = 3;	125	oclk_dly = 3;
126	sclk_dly = 5;	126	sclk_dly = 5;
127	} else {	127	} else {
128	/* hz > 50000000 */	128	/* hz > 50000000 */
129	oclk_dly = 2;	129	oclk_dly = 2;
130	sclk_dly = 4;	130	sclk_dly = 4;
131	}	131	}
132		132
133	writel(CCM_MMC_CTRL_ENABLE \| pll \| CCM_MMC_CTRL_SCLK_DLY(sclk_dly) \|	133	writel(CCM_MMC_CTRL_ENABLE \| pll \| CCM_MMC_CTRL_SCLK_DLY(sclk_dly) \|
134	CCM_MMC_CTRL_N(n) \| CCM_MMC_CTRL_OCLK_DLY(oclk_dly) \|	134	CCM_MMC_CTRL_N(n) \| CCM_MMC_CTRL_OCLK_DLY(oclk_dly) \|
135	CCM_MMC_CTRL_M(div), mmchost->mclkreg);	135	CCM_MMC_CTRL_M(div), mmchost->mclkreg);
136		136
137	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",	137	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
138	mmchost->mmc_no, hz, pll_hz, 1u << n, div,	138	mmchost->mmc_no, hz, pll_hz, 1u << n, div,
139	pll_hz / (1u << n) / div);	139	pll_hz / (1u << n) / div);
140		140
141	return 0;	141	return 0;
142	}	142	}
143		143
144	static int mmc_clk_io_on(int sdc_no)	144	static int mmc_clk_io_on(int sdc_no)
145	{	145	{
146	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];	146	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
147	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;	147	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;
148		148
149	debug("init mmc %d clock and io\n", sdc_no);	149	debug("init mmc %d clock and io\n", sdc_no);
150		150
151	/* config ahb clock */	151	/* config ahb clock */
152	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));	152	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
153		153
154	#if defined(CONFIG_MACH_SUN6I) \|\| defined(CONFIG_MACH_SUN8I) \|\| \	154	#if defined(CONFIG_MACH_SUN6I) \|\| defined(CONFIG_MACH_SUN8I) \|\| \
155	defined(CONFIG_MACH_SUN9I)	155	defined(CONFIG_MACH_SUN9I)
156	/* unassert reset */	156	/* unassert reset */
157	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));	157	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
158	#endif	158	#endif
159	#if defined(CONFIG_MACH_SUN9I)	159	#if defined(CONFIG_MACH_SUN9I)
160	/* sun9i has a mmc-common module, also set the gate and reset there */	160	/* sun9i has a mmc-common module, also set the gate and reset there */
161	writel(SUNXI_MMC_COMMON_CLK_GATE \| SUNXI_MMC_COMMON_RESET,	161	writel(SUNXI_MMC_COMMON_CLK_GATE \| SUNXI_MMC_COMMON_RESET,
162	SUNXI_MMC_COMMON_BASE + 4 * sdc_no);	162	SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
163	#endif	163	#endif
164		164
165	return mmc_set_mod_clk(mmchost, 24000000);	165	return mmc_set_mod_clk(mmchost, 24000000);
166	}	166	}
167		167
168	static int mmc_update_clk(struct mmc *mmc)	168	static int mmc_update_clk(struct mmc *mmc)
169	{	169	{
170	struct sunxi_mmc_host *mmchost = mmc->priv;	170	struct sunxi_mmc_host *mmchost = mmc->priv;
171	unsigned int cmd;	171	unsigned int cmd;
172	unsigned timeout_msecs = 2000;	172	unsigned timeout_msecs = 2000;
173		173
174	cmd = SUNXI_MMC_CMD_START \|	174	cmd = SUNXI_MMC_CMD_START \|
175	SUNXI_MMC_CMD_UPCLK_ONLY \|	175	SUNXI_MMC_CMD_UPCLK_ONLY \|
176	SUNXI_MMC_CMD_WAIT_PRE_OVER;	176	SUNXI_MMC_CMD_WAIT_PRE_OVER;
177	writel(cmd, &mmchost->reg->cmd);	177	writel(cmd, &mmchost->reg->cmd);
178	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {	178	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
179	if (!timeout_msecs--)	179	if (!timeout_msecs--)
180	return -1;	180	return -1;
181	udelay(1000);	181	udelay(1000);
182	}	182	}
183		183
184	/* clock update sets various irq status bits, clear these */	184	/* clock update sets various irq status bits, clear these */
185	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);	185	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
186		186
187	return 0;	187	return 0;
188	}	188	}
189		189
190	static int mmc_config_clock(struct mmc *mmc)	190	static int mmc_config_clock(struct mmc *mmc)
191	{	191	{
192	struct sunxi_mmc_host *mmchost = mmc->priv;	192	struct sunxi_mmc_host *mmchost = mmc->priv;
193	unsigned rval = readl(&mmchost->reg->clkcr);	193	unsigned rval = readl(&mmchost->reg->clkcr);
194		194
195	/* Disable Clock */	195	/* Disable Clock */
196	rval &= ~SUNXI_MMC_CLK_ENABLE;	196	rval &= ~SUNXI_MMC_CLK_ENABLE;
197	writel(rval, &mmchost->reg->clkcr);	197	writel(rval, &mmchost->reg->clkcr);
198	if (mmc_update_clk(mmc))	198	if (mmc_update_clk(mmc))
199	return -1;	199	return -1;
200		200
201	/* Set mod_clk to new rate */	201	/* Set mod_clk to new rate */
202	if (mmc_set_mod_clk(mmchost, mmc->clock))	202	if (mmc_set_mod_clk(mmchost, mmc->clock))
203	return -1;	203	return -1;
204		204
205	/* Clear internal divider */	205	/* Clear internal divider */
206	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;	206	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
207	writel(rval, &mmchost->reg->clkcr);	207	writel(rval, &mmchost->reg->clkcr);
208		208
209	/* Re-enable Clock */	209	/* Re-enable Clock */
210	rval \|= SUNXI_MMC_CLK_ENABLE;	210	rval \|= SUNXI_MMC_CLK_ENABLE;
211	writel(rval, &mmchost->reg->clkcr);	211	writel(rval, &mmchost->reg->clkcr);
212	if (mmc_update_clk(mmc))	212	if (mmc_update_clk(mmc))
213	return -1;	213	return -1;
214		214
215	return 0;	215	return 0;
216	}	216	}
217		217
218	static void sunxi_mmc_set_ios(struct mmc *mmc)	218	static void sunxi_mmc_set_ios(struct mmc *mmc)
219	{	219	{
220	struct sunxi_mmc_host *mmchost = mmc->priv;	220	struct sunxi_mmc_host *mmchost = mmc->priv;
221		221
222	debug("set ios: bus_width: %x, clock: %d\n",	222	debug("set ios: bus_width: %x, clock: %d\n",
223	mmc->bus_width, mmc->clock);	223	mmc->bus_width, mmc->clock);
224		224
225	/* Change clock first */	225	/* Change clock first */
226	if (mmc->clock && mmc_config_clock(mmc) != 0) {	226	if (mmc->clock && mmc_config_clock(mmc) != 0) {
227	mmchost->fatal_err = 1;	227	mmchost->fatal_err = 1;
228	return;	228	return;
229	}	229	}
230		230
231	/* Change bus width */	231	/* Change bus width */
232	if (mmc->bus_width == 8)	232	if (mmc->bus_width == 8)
233	writel(0x2, &mmchost->reg->width);	233	writel(0x2, &mmchost->reg->width);
234	else if (mmc->bus_width == 4)	234	else if (mmc->bus_width == 4)
235	writel(0x1, &mmchost->reg->width);	235	writel(0x1, &mmchost->reg->width);
236	else	236	else
237	writel(0x0, &mmchost->reg->width);	237	writel(0x0, &mmchost->reg->width);
238	}	238	}
239		239
240	static int sunxi_mmc_core_init(struct mmc *mmc)	240	static int sunxi_mmc_core_init(struct mmc *mmc)
241	{	241	{
242	struct sunxi_mmc_host *mmchost = mmc->priv;	242	struct sunxi_mmc_host *mmchost = mmc->priv;
243		243
244	/* Reset controller */	244	/* Reset controller */
245	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);	245	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
246	udelay(1000);	246	udelay(1000);
247		247
248	return 0;	248	return 0;
249	}	249	}
250		250
251	static int mmc_trans_data_by_cpu(struct mmc mmc, struct mmc_data data)	251	static int mmc_trans_data_by_cpu(struct mmc mmc, struct mmc_data data)
252	{	252	{
253	struct sunxi_mmc_host *mmchost = mmc->priv;	253	struct sunxi_mmc_host *mmchost = mmc->priv;
254	const int reading = !!(data->flags & MMC_DATA_READ);	254	const int reading = !!(data->flags & MMC_DATA_READ);
255	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :	255	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
256	SUNXI_MMC_STATUS_FIFO_FULL;	256	SUNXI_MMC_STATUS_FIFO_FULL;
257	unsigned i;	257	unsigned i;
258	unsigned byte_cnt = data->blocksize * data->blocks;	258	unsigned byte_cnt = data->blocksize * data->blocks;
259	unsigned timeout_msecs = 2000;	259	unsigned timeout_msecs = 2000;
260	unsigned buff = (unsigned int )(reading ? data->dest : data->src);	260	unsigned buff = (unsigned int )(reading ? data->dest : data->src);
261		261
262	/* Always read / write data through the CPU */	262	/* Always read / write data through the CPU */
263	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);	263	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
264		264
265	for (i = 0; i < (byte_cnt >> 2); i++) {	265	for (i = 0; i < (byte_cnt >> 2); i++) {
266	while (readl(&mmchost->reg->status) & status_bit) {	266	while (readl(&mmchost->reg->status) & status_bit) {
267	if (!timeout_msecs--)	267	if (!timeout_msecs--)
268	return -1;	268	return -1;
269	udelay(1000);	269	udelay(1000);
270	}	270	}
271		271
272	if (reading)	272	if (reading)
273	buff[i] = readl(&mmchost->reg->fifo);	273	buff[i] = readl(&mmchost->reg->fifo);
274	else	274	else
275	writel(buff[i], &mmchost->reg->fifo);	275	writel(buff[i], &mmchost->reg->fifo);
276	}	276	}
277		277
278	return 0;	278	return 0;
279	}	279	}
280		280
281	static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,	281	static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
282	unsigned int done_bit, const char *what)	282	unsigned int done_bit, const char *what)
283	{	283	{
284	struct sunxi_mmc_host *mmchost = mmc->priv;	284	struct sunxi_mmc_host *mmchost = mmc->priv;
285	unsigned int status;	285	unsigned int status;
286		286
287	do {	287	do {
288	status = readl(&mmchost->reg->rint);	288	status = readl(&mmchost->reg->rint);
289	if (!timeout_msecs-- \|\|	289	if (!timeout_msecs-- \|\|
290	(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {	290	(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
291	debug("%s timeout %x\n", what,	291	debug("%s timeout %x\n", what,
292	status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);	292	status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
293	return TIMEOUT;	293	return TIMEOUT;
294	}	294	}
295	udelay(1000);	295	udelay(1000);
296	} while (!(status & done_bit));	296	} while (!(status & done_bit));
297		297
298	return 0;	298	return 0;
299	}	299	}
300		300
301	static int sunxi_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,	301	static int sunxi_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
302	struct mmc_data *data)	302	struct mmc_data *data)
303	{	303	{
304	struct sunxi_mmc_host *mmchost = mmc->priv;	304	struct sunxi_mmc_host *mmchost = mmc->priv;
305	unsigned int cmdval = SUNXI_MMC_CMD_START;	305	unsigned int cmdval = SUNXI_MMC_CMD_START;
306	unsigned int timeout_msecs;	306	unsigned int timeout_msecs;
307	int error = 0;	307	int error = 0;
308	unsigned int status = 0;	308	unsigned int status = 0;
309	unsigned int bytecnt = 0;	309	unsigned int bytecnt = 0;
310		310
311	if (mmchost->fatal_err)	311	if (mmchost->fatal_err)
312	return -1;	312	return -1;
313	if (cmd->resp_type & MMC_RSP_BUSY)	313	if (cmd->resp_type & MMC_RSP_BUSY)
314	debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);	314	debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
315	if (cmd->cmdidx == 12)	315	if (cmd->cmdidx == 12)
316	return 0;	316	return 0;
317		317
318	if (!cmd->cmdidx)	318	if (!cmd->cmdidx)
319	cmdval \|= SUNXI_MMC_CMD_SEND_INIT_SEQ;	319	cmdval \|= SUNXI_MMC_CMD_SEND_INIT_SEQ;
320	if (cmd->resp_type & MMC_RSP_PRESENT)	320	if (cmd->resp_type & MMC_RSP_PRESENT)
321	cmdval \|= SUNXI_MMC_CMD_RESP_EXPIRE;	321	cmdval \|= SUNXI_MMC_CMD_RESP_EXPIRE;
322	if (cmd->resp_type & MMC_RSP_136)	322	if (cmd->resp_type & MMC_RSP_136)
323	cmdval \|= SUNXI_MMC_CMD_LONG_RESPONSE;	323	cmdval \|= SUNXI_MMC_CMD_LONG_RESPONSE;
324	if (cmd->resp_type & MMC_RSP_CRC)	324	if (cmd->resp_type & MMC_RSP_CRC)
325	cmdval \|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;	325	cmdval \|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
326		326
327	if (data) {	327	if (data) {
328	if ((u32) data->dest & 0x3) {	328	if ((u32) data->dest & 0x3) {
329	error = -1;	329	error = -1;
330	goto out;	330	goto out;
331	}	331	}
332		332
333	cmdval \|= SUNXI_MMC_CMD_DATA_EXPIRE\|SUNXI_MMC_CMD_WAIT_PRE_OVER;	333	cmdval \|= SUNXI_MMC_CMD_DATA_EXPIRE\|SUNXI_MMC_CMD_WAIT_PRE_OVER;
334	if (data->flags & MMC_DATA_WRITE)	334	if (data->flags & MMC_DATA_WRITE)
335	cmdval \|= SUNXI_MMC_CMD_WRITE;	335	cmdval \|= SUNXI_MMC_CMD_WRITE;
336	if (data->blocks > 1)	336	if (data->blocks > 1)
337	cmdval \|= SUNXI_MMC_CMD_AUTO_STOP;	337	cmdval \|= SUNXI_MMC_CMD_AUTO_STOP;
338	writel(data->blocksize, &mmchost->reg->blksz);	338	writel(data->blocksize, &mmchost->reg->blksz);
339	writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);	339	writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
340	}	340	}
341		341
342	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,	342	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
343	cmd->cmdidx, cmdval \| cmd->cmdidx, cmd->cmdarg);	343	cmd->cmdidx, cmdval \| cmd->cmdidx, cmd->cmdarg);
344	writel(cmd->cmdarg, &mmchost->reg->arg);	344	writel(cmd->cmdarg, &mmchost->reg->arg);
345		345
346	if (!data)	346	if (!data)
347	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);	347	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);
348		348
349	/*	349	/*
350	* transfer data and check status	350	* transfer data and check status
351	* STATREG[2] : FIFO empty	351	* STATREG[2] : FIFO empty
352	* STATREG[3] : FIFO full	352	* STATREG[3] : FIFO full
353	*/	353	*/
354	if (data) {	354	if (data) {
355	int ret = 0;	355	int ret = 0;
356		356
357	bytecnt = data->blocksize * data->blocks;	357	bytecnt = data->blocksize * data->blocks;
358	debug("trans data %d bytes\n", bytecnt);	358	debug("trans data %d bytes\n", bytecnt);
359	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);	359	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);
360	ret = mmc_trans_data_by_cpu(mmc, data);	360	ret = mmc_trans_data_by_cpu(mmc, data);
361	if (ret) {	361	if (ret) {
362	error = readl(&mmchost->reg->rint) & \	362	error = readl(&mmchost->reg->rint) & \
363	SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;	363	SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
364	error = TIMEOUT;	364	error = TIMEOUT;
365	goto out;	365	goto out;
366	}	366	}
367	}	367	}
368		368
369	error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");	369	error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
370	if (error)	370	if (error)
371	goto out;	371	goto out;
372		372
373	if (data) {	373	if (data) {
374	timeout_msecs = 120;	374	timeout_msecs = 120;
375	debug("cacl timeout %x msec\n", timeout_msecs);	375	debug("cacl timeout %x msec\n", timeout_msecs);
376	error = mmc_rint_wait(mmc, timeout_msecs,	376	error = mmc_rint_wait(mmc, timeout_msecs,
377	data->blocks > 1 ?	377	data->blocks > 1 ?
378	SUNXI_MMC_RINT_AUTO_COMMAND_DONE :	378	SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
379	SUNXI_MMC_RINT_DATA_OVER,	379	SUNXI_MMC_RINT_DATA_OVER,
380	"data");	380	"data");
381	if (error)	381	if (error)
382	goto out;	382	goto out;
383	}	383	}
384		384
385	if (cmd->resp_type & MMC_RSP_BUSY) {	385	if (cmd->resp_type & MMC_RSP_BUSY) {
386	timeout_msecs = 2000;	386	timeout_msecs = 2000;
387	do {	387	do {
388	status = readl(&mmchost->reg->status);	388	status = readl(&mmchost->reg->status);
389	if (!timeout_msecs--) {	389	if (!timeout_msecs--) {
390	debug("busy timeout\n");	390	debug("busy timeout\n");
391	error = TIMEOUT;	391	error = TIMEOUT;
392	goto out;	392	goto out;
393	}	393	}
394	udelay(1000);	394	udelay(1000);
395	} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);	395	} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
396	}	396	}
397		397
398	if (cmd->resp_type & MMC_RSP_136) {	398	if (cmd->resp_type & MMC_RSP_136) {
399	cmd->response[0] = readl(&mmchost->reg->resp3);	399	cmd->response[0] = readl(&mmchost->reg->resp3);
400	cmd->response[1] = readl(&mmchost->reg->resp2);	400	cmd->response[1] = readl(&mmchost->reg->resp2);
401	cmd->response[2] = readl(&mmchost->reg->resp1);	401	cmd->response[2] = readl(&mmchost->reg->resp1);
402	cmd->response[3] = readl(&mmchost->reg->resp0);	402	cmd->response[3] = readl(&mmchost->reg->resp0);
403	debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",	403	debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
404	cmd->response[3], cmd->response[2],	404	cmd->response[3], cmd->response[2],
405	cmd->response[1], cmd->response[0]);	405	cmd->response[1], cmd->response[0]);
406	} else {	406	} else {
407	cmd->response[0] = readl(&mmchost->reg->resp0);	407	cmd->response[0] = readl(&mmchost->reg->resp0);
408	debug("mmc resp 0x%08x\n", cmd->response[0]);	408	debug("mmc resp 0x%08x\n", cmd->response[0]);
409	}	409	}
410	out:	410	out:
411	if (error < 0) {	411	if (error < 0) {
412	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);	412	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
413	mmc_update_clk(mmc);	413	mmc_update_clk(mmc);
414	}	414	}
415	writel(0xffffffff, &mmchost->reg->rint);	415	writel(0xffffffff, &mmchost->reg->rint);
416	writel(readl(&mmchost->reg->gctrl) \| SUNXI_MMC_GCTRL_FIFO_RESET,	416	writel(readl(&mmchost->reg->gctrl) \| SUNXI_MMC_GCTRL_FIFO_RESET,
417	&mmchost->reg->gctrl);	417	&mmchost->reg->gctrl);
418		418
419	return error;	419	return error;
420	}	420	}
421		421
422	static int sunxi_mmc_getcd(struct mmc *mmc)	422	static int sunxi_mmc_getcd(struct mmc *mmc)
423	{	423	{
424	struct sunxi_mmc_host *mmchost = mmc->priv;	424	struct sunxi_mmc_host *mmchost = mmc->priv;
425	int cd_pin;	425	int cd_pin;
426		426
427	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);	427	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
428	if (cd_pin == -1)	428	if (cd_pin == -1)
429	return 1;	429	return 1;
430		430
431	return !gpio_get_value(cd_pin);	431	return !gpio_get_value(cd_pin);
432	}	432	}
433		433
434	static const struct mmc_ops sunxi_mmc_ops = {	434	static const struct mmc_ops sunxi_mmc_ops = {
435	.send_cmd = sunxi_mmc_send_cmd,	435	.send_cmd = sunxi_mmc_send_cmd,
436	.set_ios = sunxi_mmc_set_ios,	436	.set_ios = sunxi_mmc_set_ios,
437	.init = sunxi_mmc_core_init,	437	.init = sunxi_mmc_core_init,
438	.getcd = sunxi_mmc_getcd,	438	.getcd = sunxi_mmc_getcd,
439	};	439	};
440		440
441	struct mmc *sunxi_mmc_init(int sdc_no)	441	struct mmc *sunxi_mmc_init(int sdc_no)
442	{	442	{
443	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;	443	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
444		444
445	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));	445	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
446		446
447	cfg->name = "SUNXI SD/MMC";	447	cfg->name = "SUNXI SD/MMC";
448	cfg->ops = &sunxi_mmc_ops;	448	cfg->ops = &sunxi_mmc_ops;
449		449
450	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;	450	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
451	cfg->host_caps = MMC_MODE_4BIT;	451	cfg->host_caps = MMC_MODE_4BIT;
452	cfg->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS \| MMC_MODE_HC;	452	cfg->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
453	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;	453	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
454		454
455	cfg->f_min = 400000;	455	cfg->f_min = 400000;
456	cfg->f_max = 52000000;	456	cfg->f_max = 52000000;
457		457
458	if (mmc_resource_init(sdc_no) != 0)	458	if (mmc_resource_init(sdc_no) != 0)
459	return NULL;	459	return NULL;
460		460
461	mmc_clk_io_on(sdc_no);	461	mmc_clk_io_on(sdc_no);
462		462
463	return mmc_create(cfg, &mmc_host[sdc_no]);	463	return mmc_create(cfg, &mmc_host[sdc_no]);
464	}	464	}
465		465

drivers/mmc/tegra_mmc.c

Diff comments View file @ 5a20397

1	/*	1	/*
2	* (C) Copyright 2009 SAMSUNG Electronics	2	* (C) Copyright 2009 SAMSUNG Electronics
3	* Minkyu Kang <mk7.kang@samsung.com>	3	* Minkyu Kang <mk7.kang@samsung.com>
4	* Jaehoon Chung <jh80.chung@samsung.com>	4	* Jaehoon Chung <jh80.chung@samsung.com>
5	* Portions Copyright 2011-2013 NVIDIA Corporation	5	* Portions Copyright 2011-2013 NVIDIA Corporation
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#include <bouncebuf.h>	10	#include <bouncebuf.h>
11	#include <common.h>	11	#include <common.h>
12	#include <asm/gpio.h>	12	#include <asm/gpio.h>
13	#include <asm/io.h>	13	#include <asm/io.h>
14	#include <asm/arch/clock.h>	14	#include <asm/arch/clock.h>
15	#include <asm/arch-tegra/clk_rst.h>	15	#include <asm/arch-tegra/clk_rst.h>
16	#include <asm/arch-tegra/mmc.h>	16	#include <asm/arch-tegra/mmc.h>
17	#include <asm/arch-tegra/tegra_mmc.h>	17	#include <asm/arch-tegra/tegra_mmc.h>
18	#include <mmc.h>	18	#include <mmc.h>
19		19
20	DECLARE_GLOBAL_DATA_PTR;	20	DECLARE_GLOBAL_DATA_PTR;
21		21
22	struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];	22	struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
23		23
24	#ifndef CONFIG_OF_CONTROL	24	#ifndef CONFIG_OF_CONTROL
25	#error "Please enable device tree support to use this driver"	25	#error "Please enable device tree support to use this driver"
26	#endif	26	#endif
27		27
28	static void mmc_set_power(struct mmc_host *host, unsigned short power)	28	static void mmc_set_power(struct mmc_host *host, unsigned short power)
29	{	29	{
30	u8 pwr = 0;	30	u8 pwr = 0;
31	debug("%s: power = %x\n", __func__, power);	31	debug("%s: power = %x\n", __func__, power);
32		32
33	if (power != (unsigned short)-1) {	33	if (power != (unsigned short)-1) {
34	switch (1 << power) {	34	switch (1 << power) {
35	case MMC_VDD_165_195:	35	case MMC_VDD_165_195:
36	pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;	36	pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
37	break;	37	break;
38	case MMC_VDD_29_30:	38	case MMC_VDD_29_30:
39	case MMC_VDD_30_31:	39	case MMC_VDD_30_31:
40	pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;	40	pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
41	break;	41	break;
42	case MMC_VDD_32_33:	42	case MMC_VDD_32_33:
43	case MMC_VDD_33_34:	43	case MMC_VDD_33_34:
44	pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;	44	pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
45	break;	45	break;
46	}	46	}
47	}	47	}
48	debug("%s: pwr = %X\n", __func__, pwr);	48	debug("%s: pwr = %X\n", __func__, pwr);
49		49
50	/* Set the bus voltage first (if any) */	50	/* Set the bus voltage first (if any) */
51	writeb(pwr, &host->reg->pwrcon);	51	writeb(pwr, &host->reg->pwrcon);
52	if (pwr == 0)	52	if (pwr == 0)
53	return;	53	return;
54		54
55	/* Now enable bus power */	55	/* Now enable bus power */
56	pwr \|= TEGRA_MMC_PWRCTL_SD_BUS_POWER;	56	pwr \|= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
57	writeb(pwr, &host->reg->pwrcon);	57	writeb(pwr, &host->reg->pwrcon);
58	}	58	}
59		59
60	static void mmc_prepare_data(struct mmc_host host, struct mmc_data data,	60	static void mmc_prepare_data(struct mmc_host host, struct mmc_data data,
61	struct bounce_buffer *bbstate)	61	struct bounce_buffer *bbstate)
62	{	62	{
63	unsigned char ctrl;	63	unsigned char ctrl;
64		64
65		65
66	debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",	66	debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
67	bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,	67	bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
68	data->blocksize);	68	data->blocksize);
69		69
70	writel((u32)bbstate->bounce_buffer, &host->reg->sysad);	70	writel((u32)bbstate->bounce_buffer, &host->reg->sysad);
71	/*	71	/*
72	* DMASEL[4:3]	72	* DMASEL[4:3]
73	* 00 = Selects SDMA	73	* 00 = Selects SDMA
74	* 01 = Reserved	74	* 01 = Reserved
75	* 10 = Selects 32-bit Address ADMA2	75	* 10 = Selects 32-bit Address ADMA2
76	* 11 = Selects 64-bit Address ADMA2	76	* 11 = Selects 64-bit Address ADMA2
77	*/	77	*/
78	ctrl = readb(&host->reg->hostctl);	78	ctrl = readb(&host->reg->hostctl);
79	ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;	79	ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
80	ctrl \|= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;	80	ctrl \|= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
81	writeb(ctrl, &host->reg->hostctl);	81	writeb(ctrl, &host->reg->hostctl);
82		82
83	/* We do not handle DMA boundaries, so set it to max (512 KiB) */	83	/* We do not handle DMA boundaries, so set it to max (512 KiB) */
84	writew((7 << 12) \| (data->blocksize & 0xFFF), &host->reg->blksize);	84	writew((7 << 12) \| (data->blocksize & 0xFFF), &host->reg->blksize);
85	writew(data->blocks, &host->reg->blkcnt);	85	writew(data->blocks, &host->reg->blkcnt);
86	}	86	}
87		87
88	static void mmc_set_transfer_mode(struct mmc_host host, struct mmc_data data)	88	static void mmc_set_transfer_mode(struct mmc_host host, struct mmc_data data)
89	{	89	{
90	unsigned short mode;	90	unsigned short mode;
91	debug(" mmc_set_transfer_mode called\n");	91	debug(" mmc_set_transfer_mode called\n");
92	/*	92	/*
93	* TRNMOD	93	* TRNMOD
94	* MUL1SIN0[5] : Multi/Single Block Select	94	* MUL1SIN0[5] : Multi/Single Block Select
95	* RD1WT0[4] : Data Transfer Direction Select	95	* RD1WT0[4] : Data Transfer Direction Select
96	* 1 = read	96	* 1 = read
97	* 0 = write	97	* 0 = write
98	* ENACMD12[2] : Auto CMD12 Enable	98	* ENACMD12[2] : Auto CMD12 Enable
99	* ENBLKCNT[1] : Block Count Enable	99	* ENBLKCNT[1] : Block Count Enable
100	* ENDMA[0] : DMA Enable	100	* ENDMA[0] : DMA Enable
101	*/	101	*/
102	mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE \|	102	mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE \|
103	TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);	103	TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
104		104
105	if (data->blocks > 1)	105	if (data->blocks > 1)
106	mode \|= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;	106	mode \|= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
107		107
108	if (data->flags & MMC_DATA_READ)	108	if (data->flags & MMC_DATA_READ)
109	mode \|= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;	109	mode \|= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
110		110
111	writew(mode, &host->reg->trnmod);	111	writew(mode, &host->reg->trnmod);
112	}	112	}
113		113
114	static int mmc_wait_inhibit(struct mmc_host *host,	114	static int mmc_wait_inhibit(struct mmc_host *host,
115	struct mmc_cmd *cmd,	115	struct mmc_cmd *cmd,
116	struct mmc_data *data,	116	struct mmc_data *data,
117	unsigned int timeout)	117	unsigned int timeout)
118	{	118	{
119	/*	119	/*
120	* PRNSTS	120	* PRNSTS
121	* CMDINHDAT[1] : Command Inhibit (DAT)	121	* CMDINHDAT[1] : Command Inhibit (DAT)
122	* CMDINHCMD[0] : Command Inhibit (CMD)	122	* CMDINHCMD[0] : Command Inhibit (CMD)
123	*/	123	*/
124	unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;	124	unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
125		125
126	/*	126	/*
127	* We shouldn't wait for data inhibit for stop commands, even	127	* We shouldn't wait for data inhibit for stop commands, even
128	* though they might use busy signaling	128	* though they might use busy signaling
129	*/	129	*/
130	if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))	130	if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
131	mask \|= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;	131	mask \|= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
132		132
133	while (readl(&host->reg->prnsts) & mask) {	133	while (readl(&host->reg->prnsts) & mask) {
134	if (timeout == 0) {	134	if (timeout == 0) {
135	printf("%s: timeout error\n", __func__);	135	printf("%s: timeout error\n", __func__);
136	return -1;	136	return -1;
137	}	137	}
138	timeout--;	138	timeout--;
139	udelay(1000);	139	udelay(1000);
140	}	140	}
141		141
142	return 0;	142	return 0;
143	}	143	}
144		144
145	static int mmc_send_cmd_bounced(struct mmc mmc, struct mmc_cmd cmd,	145	static int mmc_send_cmd_bounced(struct mmc mmc, struct mmc_cmd cmd,
146	struct mmc_data data, struct bounce_buffer bbstate)	146	struct mmc_data data, struct bounce_buffer bbstate)
147	{	147	{
148	struct mmc_host *host = mmc->priv;	148	struct mmc_host *host = mmc->priv;
149	int flags, i;	149	int flags, i;
150	int result;	150	int result;
151	unsigned int mask = 0;	151	unsigned int mask = 0;
152	unsigned int retry = 0x100000;	152	unsigned int retry = 0x100000;
153	debug(" mmc_send_cmd called\n");	153	debug(" mmc_send_cmd called\n");
154		154
155	result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);	155	result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
156		156
157	if (result < 0)	157	if (result < 0)
158	return result;	158	return result;
159		159
160	if (data)	160	if (data)
161	mmc_prepare_data(host, data, bbstate);	161	mmc_prepare_data(host, data, bbstate);
162		162
163	debug("cmd->arg: %08x\n", cmd->cmdarg);	163	debug("cmd->arg: %08x\n", cmd->cmdarg);
164	writel(cmd->cmdarg, &host->reg->argument);	164	writel(cmd->cmdarg, &host->reg->argument);
165		165
166	if (data)	166	if (data)
167	mmc_set_transfer_mode(host, data);	167	mmc_set_transfer_mode(host, data);
168		168
169	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))	169	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
170	return -1;	170	return -1;
171		171
172	/*	172	/*
173	* CMDREG	173	* CMDREG
174	* CMDIDX[13:8] : Command index	174	* CMDIDX[13:8] : Command index
175	* DATAPRNT[5] : Data Present Select	175	* DATAPRNT[5] : Data Present Select
176	* ENCMDIDX[4] : Command Index Check Enable	176	* ENCMDIDX[4] : Command Index Check Enable
177	* ENCMDCRC[3] : Command CRC Check Enable	177	* ENCMDCRC[3] : Command CRC Check Enable
178	* RSPTYP[1:0]	178	* RSPTYP[1:0]
179	* 00 = No Response	179	* 00 = No Response
180	* 01 = Length 136	180	* 01 = Length 136
181	* 10 = Length 48	181	* 10 = Length 48
182	* 11 = Length 48 Check busy after response	182	* 11 = Length 48 Check busy after response
183	*/	183	*/
184	if (!(cmd->resp_type & MMC_RSP_PRESENT))	184	if (!(cmd->resp_type & MMC_RSP_PRESENT))
185	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;	185	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
186	else if (cmd->resp_type & MMC_RSP_136)	186	else if (cmd->resp_type & MMC_RSP_136)
187	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;	187	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
188	else if (cmd->resp_type & MMC_RSP_BUSY)	188	else if (cmd->resp_type & MMC_RSP_BUSY)
189	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;	189	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
190	else	190	else
191	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;	191	flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
192		192
193	if (cmd->resp_type & MMC_RSP_CRC)	193	if (cmd->resp_type & MMC_RSP_CRC)
194	flags \|= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;	194	flags \|= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
195	if (cmd->resp_type & MMC_RSP_OPCODE)	195	if (cmd->resp_type & MMC_RSP_OPCODE)
196	flags \|= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;	196	flags \|= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
197	if (data)	197	if (data)
198	flags \|= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;	198	flags \|= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
199		199
200	debug("cmd: %d\n", cmd->cmdidx);	200	debug("cmd: %d\n", cmd->cmdidx);
201		201
202	writew((cmd->cmdidx << 8) \| flags, &host->reg->cmdreg);	202	writew((cmd->cmdidx << 8) \| flags, &host->reg->cmdreg);
203		203
204	for (i = 0; i < retry; i++) {	204	for (i = 0; i < retry; i++) {
205	mask = readl(&host->reg->norintsts);	205	mask = readl(&host->reg->norintsts);
206	/* Command Complete */	206	/* Command Complete */
207	if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {	207	if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
208	if (!data)	208	if (!data)
209	writel(mask, &host->reg->norintsts);	209	writel(mask, &host->reg->norintsts);
210	break;	210	break;
211	}	211	}
212	}	212	}
213		213
214	if (i == retry) {	214	if (i == retry) {
215	printf("%s: waiting for status update\n", __func__);	215	printf("%s: waiting for status update\n", __func__);
216	writel(mask, &host->reg->norintsts);	216	writel(mask, &host->reg->norintsts);
217	return TIMEOUT;	217	return TIMEOUT;
218	}	218	}
219		219
220	if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {	220	if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
221	/* Timeout Error */	221	/* Timeout Error */
222	debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);	222	debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
223	writel(mask, &host->reg->norintsts);	223	writel(mask, &host->reg->norintsts);
224	return TIMEOUT;	224	return TIMEOUT;
225	} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {	225	} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
226	/* Error Interrupt */	226	/* Error Interrupt */
227	debug("error: %08x cmd %d\n", mask, cmd->cmdidx);	227	debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
228	writel(mask, &host->reg->norintsts);	228	writel(mask, &host->reg->norintsts);
229	return -1;	229	return -1;
230	}	230	}
231		231
232	if (cmd->resp_type & MMC_RSP_PRESENT) {	232	if (cmd->resp_type & MMC_RSP_PRESENT) {
233	if (cmd->resp_type & MMC_RSP_136) {	233	if (cmd->resp_type & MMC_RSP_136) {
234	/* CRC is stripped so we need to do some shifting. */	234	/* CRC is stripped so we need to do some shifting. */
235	for (i = 0; i < 4; i++) {	235	for (i = 0; i < 4; i++) {
236	unsigned int offset =	236	unsigned int offset =
237	(unsigned int)(&host->reg->rspreg3 - i);	237	(unsigned int)(&host->reg->rspreg3 - i);
238	cmd->response[i] = readl(offset) << 8;	238	cmd->response[i] = readl(offset) << 8;
239		239
240	if (i != 3) {	240	if (i != 3) {
241	cmd->response[i] \|=	241	cmd->response[i] \|=
242	readb(offset - 1);	242	readb(offset - 1);
243	}	243	}
244	debug("cmd->resp[%d]: %08x\n",	244	debug("cmd->resp[%d]: %08x\n",
245	i, cmd->response[i]);	245	i, cmd->response[i]);
246	}	246	}
247	} else if (cmd->resp_type & MMC_RSP_BUSY) {	247	} else if (cmd->resp_type & MMC_RSP_BUSY) {
248	for (i = 0; i < retry; i++) {	248	for (i = 0; i < retry; i++) {
249	/* PRNTDATA[23:20] : DAT[3:0] Line Signal */	249	/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
250	if (readl(&host->reg->prnsts)	250	if (readl(&host->reg->prnsts)
251	& (1 << 20)) /* DAT[0] */	251	& (1 << 20)) /* DAT[0] */
252	break;	252	break;
253	}	253	}
254		254
255	if (i == retry) {	255	if (i == retry) {
256	printf("%s: card is still busy\n", __func__);	256	printf("%s: card is still busy\n", __func__);
257	writel(mask, &host->reg->norintsts);	257	writel(mask, &host->reg->norintsts);
258	return TIMEOUT;	258	return TIMEOUT;
259	}	259	}
260		260
261	cmd->response[0] = readl(&host->reg->rspreg0);	261	cmd->response[0] = readl(&host->reg->rspreg0);
262	debug("cmd->resp[0]: %08x\n", cmd->response[0]);	262	debug("cmd->resp[0]: %08x\n", cmd->response[0]);
263	} else {	263	} else {
264	cmd->response[0] = readl(&host->reg->rspreg0);	264	cmd->response[0] = readl(&host->reg->rspreg0);
265	debug("cmd->resp[0]: %08x\n", cmd->response[0]);	265	debug("cmd->resp[0]: %08x\n", cmd->response[0]);
266	}	266	}
267	}	267	}
268		268
269	if (data) {	269	if (data) {
270	unsigned long start = get_timer(0);	270	unsigned long start = get_timer(0);
271		271
272	while (1) {	272	while (1) {
273	mask = readl(&host->reg->norintsts);	273	mask = readl(&host->reg->norintsts);
274		274
275	if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {	275	if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
276	/* Error Interrupt */	276	/* Error Interrupt */
277	writel(mask, &host->reg->norintsts);	277	writel(mask, &host->reg->norintsts);
278	printf("%s: error during transfer: 0x%08x\n",	278	printf("%s: error during transfer: 0x%08x\n",
279	__func__, mask);	279	__func__, mask);
280	return -1;	280	return -1;
281	} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {	281	} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
282	/*	282	/*
283	* DMA Interrupt, restart the transfer where	283	* DMA Interrupt, restart the transfer where
284	* it was interrupted.	284	* it was interrupted.
285	*/	285	*/
286	unsigned int address = readl(&host->reg->sysad);	286	unsigned int address = readl(&host->reg->sysad);
287		287
288	debug("DMA end\n");	288	debug("DMA end\n");
289	writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,	289	writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
290	&host->reg->norintsts);	290	&host->reg->norintsts);
291	writel(address, &host->reg->sysad);	291	writel(address, &host->reg->sysad);
292	} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {	292	} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
293	/* Transfer Complete */	293	/* Transfer Complete */
294	debug("r/w is done\n");	294	debug("r/w is done\n");
295	break;	295	break;
296	} else if (get_timer(start) > 8000UL) {	296	} else if (get_timer(start) > 8000UL) {
297	writel(mask, &host->reg->norintsts);	297	writel(mask, &host->reg->norintsts);
298	printf("%s: MMC Timeout\n"	298	printf("%s: MMC Timeout\n"
299	" Interrupt status 0x%08x\n"	299	" Interrupt status 0x%08x\n"
300	" Interrupt status enable 0x%08x\n"	300	" Interrupt status enable 0x%08x\n"
301	" Interrupt signal enable 0x%08x\n"	301	" Interrupt signal enable 0x%08x\n"
302	" Present status 0x%08x\n",	302	" Present status 0x%08x\n",
303	__func__, mask,	303	__func__, mask,
304	readl(&host->reg->norintstsen),	304	readl(&host->reg->norintstsen),
305	readl(&host->reg->norintsigen),	305	readl(&host->reg->norintsigen),
306	readl(&host->reg->prnsts));	306	readl(&host->reg->prnsts));
307	return -1;	307	return -1;
308	}	308	}
309	}	309	}
310	writel(mask, &host->reg->norintsts);	310	writel(mask, &host->reg->norintsts);
311	}	311	}
312		312
313	udelay(1000);	313	udelay(1000);
314	return 0;	314	return 0;
315	}	315	}
316		316
317	static int tegra_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,	317	static int tegra_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
318	struct mmc_data *data)	318	struct mmc_data *data)
319	{	319	{
320	void *buf;	320	void *buf;
321	unsigned int bbflags;	321	unsigned int bbflags;
322	size_t len;	322	size_t len;
323	struct bounce_buffer bbstate;	323	struct bounce_buffer bbstate;
324	int ret;	324	int ret;
325		325
326	if (data) {	326	if (data) {
327	if (data->flags & MMC_DATA_READ) {	327	if (data->flags & MMC_DATA_READ) {
328	buf = data->dest;	328	buf = data->dest;
329	bbflags = GEN_BB_WRITE;	329	bbflags = GEN_BB_WRITE;
330	} else {	330	} else {
331	buf = (void *)data->src;	331	buf = (void *)data->src;
332	bbflags = GEN_BB_READ;	332	bbflags = GEN_BB_READ;
333	}	333	}
334	len = data->blocks * data->blocksize;	334	len = data->blocks * data->blocksize;
335		335
336	bounce_buffer_start(&bbstate, buf, len, bbflags);	336	bounce_buffer_start(&bbstate, buf, len, bbflags);
337	}	337	}
338		338
339	ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);	339	ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
340		340
341	if (data)	341	if (data)
342	bounce_buffer_stop(&bbstate);	342	bounce_buffer_stop(&bbstate);
343		343
344	return ret;	344	return ret;
345	}	345	}
346		346
347	static void mmc_change_clock(struct mmc_host *host, uint clock)	347	static void mmc_change_clock(struct mmc_host *host, uint clock)
348	{	348	{
349	int div;	349	int div;
350	unsigned short clk;	350	unsigned short clk;
351	unsigned long timeout;	351	unsigned long timeout;
352		352
353	debug(" mmc_change_clock called\n");	353	debug(" mmc_change_clock called\n");
354		354
355	/*	355	/*
356	* Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0	356	* Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
357	*/	357	*/
358	if (clock == 0)	358	if (clock == 0)
359	goto out;	359	goto out;
360	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,	360	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
361	&div);	361	&div);
362	debug("div = %d\n", div);	362	debug("div = %d\n", div);
363		363
364	writew(0, &host->reg->clkcon);	364	writew(0, &host->reg->clkcon);
365		365
366	/*	366	/*
367	* CLKCON	367	* CLKCON
368	* SELFREQ[15:8] : base clock divided by value	368	* SELFREQ[15:8] : base clock divided by value
369	* ENSDCLK[2] : SD Clock Enable	369	* ENSDCLK[2] : SD Clock Enable
370	* STBLINTCLK[1] : Internal Clock Stable	370	* STBLINTCLK[1] : Internal Clock Stable
371	* ENINTCLK[0] : Internal Clock Enable	371	* ENINTCLK[0] : Internal Clock Enable
372	*/	372	*/
373	div >>= 1;	373	div >>= 1;
374	clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) \|	374	clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) \|
375	TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);	375	TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
376	writew(clk, &host->reg->clkcon);	376	writew(clk, &host->reg->clkcon);
377		377
378	/* Wait max 10 ms */	378	/* Wait max 10 ms */
379	timeout = 10;	379	timeout = 10;
380	while (!(readw(&host->reg->clkcon) &	380	while (!(readw(&host->reg->clkcon) &
381	TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {	381	TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
382	if (timeout == 0) {	382	if (timeout == 0) {
383	printf("%s: timeout error\n", __func__);	383	printf("%s: timeout error\n", __func__);
384	return;	384	return;
385	}	385	}
386	timeout--;	386	timeout--;
387	udelay(1000);	387	udelay(1000);
388	}	388	}
389		389
390	clk \|= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;	390	clk \|= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
391	writew(clk, &host->reg->clkcon);	391	writew(clk, &host->reg->clkcon);
392		392
393	debug("mmc_change_clock: clkcon = %08X\n", clk);	393	debug("mmc_change_clock: clkcon = %08X\n", clk);
394		394
395	out:	395	out:
396	host->clock = clock;	396	host->clock = clock;
397	}	397	}
398		398
399	static void tegra_mmc_set_ios(struct mmc *mmc)	399	static void tegra_mmc_set_ios(struct mmc *mmc)
400	{	400	{
401	struct mmc_host *host = mmc->priv;	401	struct mmc_host *host = mmc->priv;
402	unsigned char ctrl;	402	unsigned char ctrl;
403	debug(" mmc_set_ios called\n");	403	debug(" mmc_set_ios called\n");
404		404
405	debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);	405	debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
406		406
407	/* Change clock first */	407	/* Change clock first */
408	mmc_change_clock(host, mmc->clock);	408	mmc_change_clock(host, mmc->clock);
409		409
410	ctrl = readb(&host->reg->hostctl);	410	ctrl = readb(&host->reg->hostctl);
411		411
412	/*	412	/*
413	* WIDE8[5]	413	* WIDE8[5]
414	* 0 = Depend on WIDE4	414	* 0 = Depend on WIDE4
415	* 1 = 8-bit mode	415	* 1 = 8-bit mode
416	* WIDE4[1]	416	* WIDE4[1]
417	* 1 = 4-bit mode	417	* 1 = 4-bit mode
418	* 0 = 1-bit mode	418	* 0 = 1-bit mode
419	*/	419	*/
420	if (mmc->bus_width == 8)	420	if (mmc->bus_width == 8)
421	ctrl \|= (1 << 5);	421	ctrl \|= (1 << 5);
422	else if (mmc->bus_width == 4)	422	else if (mmc->bus_width == 4)
423	ctrl \|= (1 << 1);	423	ctrl \|= (1 << 1);
424	else	424	else
425	ctrl &= ~(1 << 1);	425	ctrl &= ~(1 << 1);
426		426
427	writeb(ctrl, &host->reg->hostctl);	427	writeb(ctrl, &host->reg->hostctl);
428	debug("mmc_set_ios: hostctl = %08X\n", ctrl);	428	debug("mmc_set_ios: hostctl = %08X\n", ctrl);
429	}	429	}
430		430
431	static void mmc_reset(struct mmc_host host, struct mmc mmc)	431	static void mmc_reset(struct mmc_host host, struct mmc mmc)
432	{	432	{
433	unsigned int timeout;	433	unsigned int timeout;
434	debug(" mmc_reset called\n");	434	debug(" mmc_reset called\n");
435		435
436	/*	436	/*
437	* RSTALL[0] : Software reset for all	437	* RSTALL[0] : Software reset for all
438	* 1 = reset	438	* 1 = reset
439	* 0 = work	439	* 0 = work
440	*/	440	*/
441	writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);	441	writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
442		442
443	host->clock = 0;	443	host->clock = 0;
444		444
445	/* Wait max 100 ms */	445	/* Wait max 100 ms */
446	timeout = 100;	446	timeout = 100;
447		447
448	/* hw clears the bit when it's done */	448	/* hw clears the bit when it's done */
449	while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {	449	while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
450	if (timeout == 0) {	450	if (timeout == 0) {
451	printf("%s: timeout error\n", __func__);	451	printf("%s: timeout error\n", __func__);
452	return;	452	return;
453	}	453	}
454	timeout--;	454	timeout--;
455	udelay(1000);	455	udelay(1000);
456	}	456	}
457		457
458	/* Set SD bus voltage & enable bus power */	458	/* Set SD bus voltage & enable bus power */
459	mmc_set_power(host, fls(mmc->cfg->voltages) - 1);	459	mmc_set_power(host, fls(mmc->cfg->voltages) - 1);
460	debug("%s: power control = %02X, host control = %02X\n", __func__,	460	debug("%s: power control = %02X, host control = %02X\n", __func__,
461	readb(&host->reg->pwrcon), readb(&host->reg->hostctl));	461	readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
462		462
463	/* Make sure SDIO pads are set up */	463	/* Make sure SDIO pads are set up */
464	pad_init_mmc(host);	464	pad_init_mmc(host);
465	}	465	}
466		466
467	static int tegra_mmc_core_init(struct mmc *mmc)	467	static int tegra_mmc_core_init(struct mmc *mmc)
468	{	468	{
469	struct mmc_host *host = mmc->priv;	469	struct mmc_host *host = mmc->priv;
470	unsigned int mask;	470	unsigned int mask;
471	debug(" mmc_core_init called\n");	471	debug(" mmc_core_init called\n");
472		472
473	mmc_reset(host, mmc);	473	mmc_reset(host, mmc);
474		474
475	host->version = readw(&host->reg->hcver);	475	host->version = readw(&host->reg->hcver);
476	debug("host version = %x\n", host->version);	476	debug("host version = %x\n", host->version);
477		477
478	/* mask all */	478	/* mask all */
479	writel(0xffffffff, &host->reg->norintstsen);	479	writel(0xffffffff, &host->reg->norintstsen);
480	writel(0xffffffff, &host->reg->norintsigen);	480	writel(0xffffffff, &host->reg->norintsigen);
481		481
482	writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */	482	writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
483	/*	483	/*
484	* NORMAL Interrupt Status Enable Register init	484	* NORMAL Interrupt Status Enable Register init
485	* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable	485	* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
486	* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable	486	* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
487	* [3] ENSTADMAINT : DMA boundary interrupt	487	* [3] ENSTADMAINT : DMA boundary interrupt
488	* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable	488	* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
489	* [0] ENSTACMDCMPLT : Command Complete Status Enable	489	* [0] ENSTACMDCMPLT : Command Complete Status Enable
490	*/	490	*/
491	mask = readl(&host->reg->norintstsen);	491	mask = readl(&host->reg->norintstsen);
492	mask &= ~(0xffff);	492	mask &= ~(0xffff);
493	mask \|= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE \|	493	mask \|= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE \|
494	TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE \|	494	TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE \|
495	TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT \|	495	TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT \|
496	TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY \|	496	TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY \|
497	TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);	497	TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
498	writel(mask, &host->reg->norintstsen);	498	writel(mask, &host->reg->norintstsen);
499		499
500	/*	500	/*
501	* NORMAL Interrupt Signal Enable Register init	501	* NORMAL Interrupt Signal Enable Register init
502	* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable	502	* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
503	*/	503	*/
504	mask = readl(&host->reg->norintsigen);	504	mask = readl(&host->reg->norintsigen);
505	mask &= ~(0xffff);	505	mask &= ~(0xffff);
506	mask \|= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;	506	mask \|= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
507	writel(mask, &host->reg->norintsigen);	507	writel(mask, &host->reg->norintsigen);
508		508
509	return 0;	509	return 0;
510	}	510	}
511		511
512	static int tegra_mmc_getcd(struct mmc *mmc)	512	static int tegra_mmc_getcd(struct mmc *mmc)
513	{	513	{
514	struct mmc_host *host = mmc->priv;	514	struct mmc_host *host = mmc->priv;
515		515
516	debug("tegra_mmc_getcd called\n");	516	debug("tegra_mmc_getcd called\n");
517		517
518	if (dm_gpio_is_valid(&host->cd_gpio))	518	if (dm_gpio_is_valid(&host->cd_gpio))
519	return dm_gpio_get_value(&host->cd_gpio);	519	return dm_gpio_get_value(&host->cd_gpio);
520		520
521	return 1;	521	return 1;
522	}	522	}
523		523
524	static const struct mmc_ops tegra_mmc_ops = {	524	static const struct mmc_ops tegra_mmc_ops = {
525	.send_cmd = tegra_mmc_send_cmd,	525	.send_cmd = tegra_mmc_send_cmd,
526	.set_ios = tegra_mmc_set_ios,	526	.set_ios = tegra_mmc_set_ios,
527	.init = tegra_mmc_core_init,	527	.init = tegra_mmc_core_init,
528	.getcd = tegra_mmc_getcd,	528	.getcd = tegra_mmc_getcd,
529	};	529	};
530		530
531	static int do_mmc_init(int dev_index)	531	static int do_mmc_init(int dev_index)
532	{	532	{
533	struct mmc_host *host;	533	struct mmc_host *host;
534	struct mmc *mmc;	534	struct mmc *mmc;
535		535
536	/* DT should have been read & host config filled in */	536	/* DT should have been read & host config filled in */
537	host = &mmc_host[dev_index];	537	host = &mmc_host[dev_index];
538	if (!host->enabled)	538	if (!host->enabled)
539	return -1;	539	return -1;
540		540
541	debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n",	541	debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n",
542	dev_index, host->width, gpio_get_number(&host->pwr_gpio),	542	dev_index, host->width, gpio_get_number(&host->pwr_gpio),
543	gpio_get_number(&host->cd_gpio));	543	gpio_get_number(&host->cd_gpio));
544		544
545	host->clock = 0;	545	host->clock = 0;
546	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);	546	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
547		547
548	if (dm_gpio_is_valid(&host->pwr_gpio))	548	if (dm_gpio_is_valid(&host->pwr_gpio))
549	dm_gpio_set_value(&host->pwr_gpio, 1);	549	dm_gpio_set_value(&host->pwr_gpio, 1);
550		550
551	memset(&host->cfg, 0, sizeof(host->cfg));	551	memset(&host->cfg, 0, sizeof(host->cfg));
552		552
553	host->cfg.name = "Tegra SD/MMC";	553	host->cfg.name = "Tegra SD/MMC";
554	host->cfg.ops = &tegra_mmc_ops;	554	host->cfg.ops = &tegra_mmc_ops;
555		555
556	host->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;	556	host->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
557	host->cfg.host_caps = 0;	557	host->cfg.host_caps = 0;
558	if (host->width == 8)	558	if (host->width == 8)
559	host->cfg.host_caps \|= MMC_MODE_8BIT;	559	host->cfg.host_caps \|= MMC_MODE_8BIT;
560	if (host->width >= 4)	560	if (host->width >= 4)
561	host->cfg.host_caps \|= MMC_MODE_4BIT;	561	host->cfg.host_caps \|= MMC_MODE_4BIT;
562	host->cfg.host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS \| MMC_MODE_HC;	562	host->cfg.host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
563		563
564	/*	564	/*
565	* min freq is for card identification, and is the highest	565	* min freq is for card identification, and is the highest
566	* low-speed SDIO card frequency (actually 400KHz)	566	* low-speed SDIO card frequency (actually 400KHz)
567	* max freq is highest HS eMMC clock as per the SD/MMC spec	567	* max freq is highest HS eMMC clock as per the SD/MMC spec
568	* (actually 52MHz)	568	* (actually 52MHz)
569	*/	569	*/
570	host->cfg.f_min = 375000;	570	host->cfg.f_min = 375000;
571	host->cfg.f_max = 48000000;	571	host->cfg.f_max = 48000000;
572		572
573	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;	573	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
574		574
575	mmc = mmc_create(&host->cfg, host);	575	mmc = mmc_create(&host->cfg, host);
576	if (mmc == NULL)	576	if (mmc == NULL)
577	return -1;	577	return -1;
578		578
579	return 0;	579	return 0;
580	}	580	}
581		581
582	/**	582	/**
583	* Get the host address and peripheral ID for a node.	583	* Get the host address and peripheral ID for a node.
584	*	584	*
585	* @param blob fdt blob	585	* @param blob fdt blob
586	* @param node Device index (0-3)	586	* @param node Device index (0-3)
587	* @param host Structure to fill in (reg, width, mmc_id)	587	* @param host Structure to fill in (reg, width, mmc_id)
588	*/	588	*/
589	static int mmc_get_config(const void blob, int node, struct mmc_host host)	589	static int mmc_get_config(const void blob, int node, struct mmc_host host)
590	{	590	{
591	debug("%s: node = %d\n", __func__, node);	591	debug("%s: node = %d\n", __func__, node);
592		592
593	host->enabled = fdtdec_get_is_enabled(blob, node);	593	host->enabled = fdtdec_get_is_enabled(blob, node);
594		594
595	host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");	595	host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
596	if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {	596	if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
597	debug("%s: no sdmmc base reg info found\n", __func__);	597	debug("%s: no sdmmc base reg info found\n", __func__);
598	return -FDT_ERR_NOTFOUND;	598	return -FDT_ERR_NOTFOUND;
599	}	599	}
600		600
601	host->mmc_id = clock_decode_periph_id(blob, node);	601	host->mmc_id = clock_decode_periph_id(blob, node);
602	if (host->mmc_id == PERIPH_ID_NONE) {	602	if (host->mmc_id == PERIPH_ID_NONE) {
603	debug("%s: could not decode periph id\n", __func__);	603	debug("%s: could not decode periph id\n", __func__);
604	return -FDT_ERR_NOTFOUND;	604	return -FDT_ERR_NOTFOUND;
605	}	605	}
606		606
607	/*	607	/*
608	* NOTE: mmc->bus_width is determined by mmc.c dynamically.	608	* NOTE: mmc->bus_width is determined by mmc.c dynamically.
609	* TBD: Override it with this value?	609	* TBD: Override it with this value?
610	*/	610	*/
611	host->width = fdtdec_get_int(blob, node, "bus-width", 0);	611	host->width = fdtdec_get_int(blob, node, "bus-width", 0);
612	if (!host->width)	612	if (!host->width)
613	debug("%s: no sdmmc width found\n", __func__);	613	debug("%s: no sdmmc width found\n", __func__);
614		614
615	/* These GPIOs are optional */	615	/* These GPIOs are optional */
616	gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio,	616	gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio,
617	GPIOD_IS_IN);	617	GPIOD_IS_IN);
618	gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &host->wp_gpio,	618	gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &host->wp_gpio,
619	GPIOD_IS_IN);	619	GPIOD_IS_IN);
620	gpio_request_by_name_nodev(blob, node, "power-gpios", 0,	620	gpio_request_by_name_nodev(blob, node, "power-gpios", 0,
621	&host->pwr_gpio, GPIOD_IS_OUT);	621	&host->pwr_gpio, GPIOD_IS_OUT);
622		622
623	debug("%s: found controller at %p, width = %d, periph_id = %d\n",	623	debug("%s: found controller at %p, width = %d, periph_id = %d\n",
624	__func__, host->reg, host->width, host->mmc_id);	624	__func__, host->reg, host->width, host->mmc_id);
625	return 0;	625	return 0;
626	}	626	}
627		627
628	/*	628	/*
629	* Process a list of nodes, adding them to our list of SDMMC ports.	629	* Process a list of nodes, adding them to our list of SDMMC ports.
630	*	630	*
631	* @param blob fdt blob	631	* @param blob fdt blob
632	* @param node_list list of nodes to process (any <=0 are ignored)	632	* @param node_list list of nodes to process (any <=0 are ignored)
633	* @param count number of nodes to process	633	* @param count number of nodes to process
634	* @return 0 if ok, -1 on error	634	* @return 0 if ok, -1 on error
635	*/	635	*/
636	static int process_nodes(const void *blob, int node_list[], int count)	636	static int process_nodes(const void *blob, int node_list[], int count)
637	{	637	{
638	struct mmc_host *host;	638	struct mmc_host *host;
639	int i, node;	639	int i, node;
640		640
641	debug("%s: count = %d\n", __func__, count);	641	debug("%s: count = %d\n", __func__, count);
642		642
643	/* build mmc_host[] for each controller */	643	/* build mmc_host[] for each controller */
644	for (i = 0; i < count; i++) {	644	for (i = 0; i < count; i++) {
645	node = node_list[i];	645	node = node_list[i];
646	if (node <= 0)	646	if (node <= 0)
647	continue;	647	continue;
648		648
649	host = &mmc_host[i];	649	host = &mmc_host[i];
650	host->id = i;	650	host->id = i;
651		651
652	if (mmc_get_config(blob, node, host)) {	652	if (mmc_get_config(blob, node, host)) {
653	printf("%s: failed to decode dev %d\n", __func__, i);	653	printf("%s: failed to decode dev %d\n", __func__, i);
654	return -1;	654	return -1;
655	}	655	}
656	do_mmc_init(i);	656	do_mmc_init(i);
657	}	657	}
658	return 0;	658	return 0;
659	}	659	}
660		660
661	void tegra_mmc_init(void)	661	void tegra_mmc_init(void)
662	{	662	{
663	int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;	663	int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;
664	const void *blob = gd->fdt_blob;	664	const void *blob = gd->fdt_blob;
665	debug("%s entry\n", __func__);	665	debug("%s entry\n", __func__);
666		666
667	/* See if any Tegra124 MMC controllers are present */	667	/* See if any Tegra124 MMC controllers are present */
668	count = fdtdec_find_aliases_for_id(blob, "sdhci",	668	count = fdtdec_find_aliases_for_id(blob, "sdhci",
669	COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,	669	COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,
670	CONFIG_SYS_MMC_MAX_DEVICE);	670	CONFIG_SYS_MMC_MAX_DEVICE);
671	debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);	671	debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
672	if (process_nodes(blob, node_list, count)) {	672	if (process_nodes(blob, node_list, count)) {
673	printf("%s: Error processing T30 mmc node(s)!\n", __func__);	673	printf("%s: Error processing T30 mmc node(s)!\n", __func__);
674	return;	674	return;
675	}	675	}
676		676
677	/* See if any Tegra30 MMC controllers are present */	677	/* See if any Tegra30 MMC controllers are present */
678	count = fdtdec_find_aliases_for_id(blob, "sdhci",	678	count = fdtdec_find_aliases_for_id(blob, "sdhci",
679	COMPAT_NVIDIA_TEGRA30_SDMMC, node_list,	679	COMPAT_NVIDIA_TEGRA30_SDMMC, node_list,
680	CONFIG_SYS_MMC_MAX_DEVICE);	680	CONFIG_SYS_MMC_MAX_DEVICE);
681	debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);	681	debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
682	if (process_nodes(blob, node_list, count)) {	682	if (process_nodes(blob, node_list, count)) {
683	printf("%s: Error processing T30 mmc node(s)!\n", __func__);	683	printf("%s: Error processing T30 mmc node(s)!\n", __func__);
684	return;	684	return;
685	}	685	}
686		686
687	/* Now look for any Tegra20 MMC controllers */	687	/* Now look for any Tegra20 MMC controllers */
688	count = fdtdec_find_aliases_for_id(blob, "sdhci",	688	count = fdtdec_find_aliases_for_id(blob, "sdhci",
689	COMPAT_NVIDIA_TEGRA20_SDMMC, node_list,	689	COMPAT_NVIDIA_TEGRA20_SDMMC, node_list,
690	CONFIG_SYS_MMC_MAX_DEVICE);	690	CONFIG_SYS_MMC_MAX_DEVICE);
691	debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);	691	debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
692	if (process_nodes(blob, node_list, count)) {	692	if (process_nodes(blob, node_list, count)) {
693	printf("%s: Error processing T20 mmc node(s)!\n", __func__);	693	printf("%s: Error processing T20 mmc node(s)!\n", __func__);
694	return;	694	return;
695	}	695	}
696	}	696	}
697		697

drivers/mmc/zynq_sdhci.c

Diff comments View file @ 5a20397

 /*
  * (C) Copyright 2013 Inc.
  *
  * Xilinx Zynq SD Host Controller Interface
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <fdtdec.h>
 #include <libfdt.h>
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/arch/sys_proto.h>
 int zynq_sdhci_init(phys_addr_t regbase)
 {
 	struct sdhci_host *host = NULL;
 	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
 	if (!host) {
 		printf("zynq_sdhci_init: sdhci_host malloc fail\n");
 		return 1;
 	}
 	host->name = "zynq_sdhci";
 	host->ioaddr = (void *)regbase;
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 		       SDHCI_QUIRK_BROKEN_R1B;
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-	host->host_caps = MMC_MODE_HC;
 	add_sdhci(host, 52000000, 52000000 >> 9);
 	return 0;
 }
 #ifdef CONFIG_OF_CONTROL
 int zynq_sdhci_of_init(const void *blob)
 {
 	int offset = 0;
 	u32 ret = 0;
 	phys_addr_t reg;
 	debug("ZYNQ SDHCI: Initialization\n");
 	do {
 		offset = fdt_node_offset_by_compatible(blob, offset,
 					"arasan,sdhci-8.9a");
 		if (offset != -1) {
 			reg = fdtdec_get_addr(blob, offset, "reg");
 			if (reg != FDT_ADDR_T_NONE) {
 				ret |= zynq_sdhci_init(reg);
 			} else {
 				debug("ZYNQ SDHCI: Can't get base address\n");
 				return -1;
 			}
 		}
 	} while (offset != -1);
 	return ret;
 }
 #endif

include/mmc.h

Diff comments View file @ 5a20397

 /*
  * Copyright 2008,2010 Freescale Semiconductor, Inc
  * Andy Fleming
  *
  * Based (loosely) on the Linux code
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _MMC_H_
 #define _MMC_H_
 #include <linux/list.h>
 #include <linux/compiler.h>
 #include <part.h>
 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
 #define SD_VERSION_SD	(1U << 31)
 #define MMC_VERSION_MMC	(1U << 30)
 #define MAKE_SDMMC_VERSION(a, b, c)	\
 	((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
 #define MAKE_SD_VERSION(a, b, c)	\
 	(SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
 #define MAKE_MMC_VERSION(a, b, c)	\
 	(MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
 #define EXTRACT_SDMMC_MAJOR_VERSION(x)	\
 	(((u32)(x) >> 16) & 0xff)
 #define EXTRACT_SDMMC_MINOR_VERSION(x)	\
 	(((u32)(x) >> 8) & 0xff)
 #define EXTRACT_SDMMC_CHANGE_VERSION(x)	\
 	((u32)(x) & 0xff)
 #define SD_VERSION_3		MAKE_SD_VERSION(3, 0, 0)
 #define SD_VERSION_2		MAKE_SD_VERSION(2, 0, 0)
 #define SD_VERSION_1_0		MAKE_SD_VERSION(1, 0, 0)
 #define SD_VERSION_1_10		MAKE_SD_VERSION(1, 10, 0)
 #define MMC_VERSION_UNKNOWN	MAKE_MMC_VERSION(0, 0, 0)
 #define MMC_VERSION_1_2		MAKE_MMC_VERSION(1, 2, 0)
 #define MMC_VERSION_1_4		MAKE_MMC_VERSION(1, 4, 0)
 #define MMC_VERSION_2_2		MAKE_MMC_VERSION(2, 2, 0)
 #define MMC_VERSION_3		MAKE_MMC_VERSION(3, 0, 0)
 #define MMC_VERSION_4		MAKE_MMC_VERSION(4, 0, 0)
 #define MMC_VERSION_4_1		MAKE_MMC_VERSION(4, 1, 0)
 #define MMC_VERSION_4_2		MAKE_MMC_VERSION(4, 2, 0)
 #define MMC_VERSION_4_3		MAKE_MMC_VERSION(4, 3, 0)
 #define MMC_VERSION_4_41	MAKE_MMC_VERSION(4, 4, 1)
 #define MMC_VERSION_4_5		MAKE_MMC_VERSION(4, 5, 0)
 #define MMC_VERSION_5_0		MAKE_MMC_VERSION(5, 0, 0)
 #define MMC_MODE_HS		(1 << 0)
 #define MMC_MODE_HS_52MHz	(1 << 1)
 #define MMC_MODE_4BIT		(1 << 2)
 #define MMC_MODE_8BIT		(1 << 3)
 #define MMC_MODE_SPI		(1 << 4)
-#define MMC_MODE_HC		(1 << 5)
+#define MMC_MODE_DDR_52MHz	(1 << 5)
-#define MMC_MODE_DDR_52MHz	(1 << 6)
 #define SD_DATA_4BIT	0x00040000
 #define IS_SD(x)	((x)->version & SD_VERSION_SD)
 #define IS_MMC(x)	((x)->version & MMC_VERSION_MMC)
 #define MMC_DATA_READ		1
 #define MMC_DATA_WRITE		2
 #define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
 #define UNUSABLE_ERR		-17 /* Unusable Card */
 #define COMM_ERR		-18 /* Communications Error */
 #define TIMEOUT			-19
 #define SWITCH_ERR		-20 /* Card reports failure to switch mode */
 #define MMC_CMD_GO_IDLE_STATE		0
 #define MMC_CMD_SEND_OP_COND		1
 #define MMC_CMD_ALL_SEND_CID		2
 #define MMC_CMD_SET_RELATIVE_ADDR	3
 #define MMC_CMD_SET_DSR			4
 #define MMC_CMD_SWITCH			6
 #define MMC_CMD_SELECT_CARD		7
 #define MMC_CMD_SEND_EXT_CSD		8
 #define MMC_CMD_SEND_CSD		9
 #define MMC_CMD_SEND_CID		10
 #define MMC_CMD_STOP_TRANSMISSION	12
 #define MMC_CMD_SEND_STATUS		13
 #define MMC_CMD_SET_BLOCKLEN		16
 #define MMC_CMD_READ_SINGLE_BLOCK	17
 #define MMC_CMD_READ_MULTIPLE_BLOCK	18
 #define MMC_CMD_SET_BLOCK_COUNT         23
 #define MMC_CMD_WRITE_SINGLE_BLOCK	24
 #define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
 #define MMC_CMD_ERASE_GROUP_START	35
 #define MMC_CMD_ERASE_GROUP_END		36
 #define MMC_CMD_ERASE			38
 #define MMC_CMD_APP_CMD			55
 #define MMC_CMD_SPI_READ_OCR		58
 #define MMC_CMD_SPI_CRC_ON_OFF		59
 #define MMC_CMD_RES_MAN			62
 #define MMC_CMD62_ARG1			0xefac62ec
 #define MMC_CMD62_ARG2			0xcbaea7
 #define SD_CMD_SEND_RELATIVE_ADDR	3
 #define SD_CMD_SWITCH_FUNC		6
 #define SD_CMD_SEND_IF_COND		8
 #define SD_CMD_SWITCH_UHS18V		11
 #define SD_CMD_APP_SET_BUS_WIDTH	6
 #define SD_CMD_ERASE_WR_BLK_START	32
 #define SD_CMD_ERASE_WR_BLK_END		33
 #define SD_CMD_APP_SEND_OP_COND		41
 #define SD_CMD_APP_SEND_SCR		51
 /* SCR definitions in different words */
 #define SD_HIGHSPEED_BUSY	0x00020000
 #define SD_HIGHSPEED_SUPPORTED	0x00020000
 #define OCR_BUSY		0x80000000
 #define OCR_HCS			0x40000000
 #define OCR_VOLTAGE_MASK	0x007FFF80
 #define OCR_ACCESS_MODE		0x60000000
 #define SECURE_ERASE		0x80000000
 #define MMC_STATUS_MASK		(~0x0206BF7F)
 #define MMC_STATUS_SWITCH_ERROR	(1 << 7)
 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 #define MMC_STATUS_CURR_STATE	(0xf << 9)
 #define MMC_STATUS_ERROR	(1 << 19)
 #define MMC_STATE_PRG		(7 << 9)
 #define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
 #define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
 #define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
 #define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
 #define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
 #define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
 #define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
 #define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
 #define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
 #define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
 #define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
 #define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
 #define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
 #define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
 #define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
 #define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
 #define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
 #define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
 #define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
 						addressed by index which are
 						1 in value field */
 #define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
 						addressed by index, which are
 						1 in value field */
 #define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */
 #define SD_SWITCH_CHECK		0
 #define SD_SWITCH_SWITCH	1
 /*
  * EXT_CSD fields
  */
 #define EXT_CSD_ENH_START_ADDR		136	/* R/W */
 #define EXT_CSD_ENH_SIZE_MULT		140	/* R/W */
 #define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
 #define EXT_CSD_PARTITION_SETTING	155	/* R/W */
 #define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
 #define EXT_CSD_MAX_ENH_SIZE_MULT	157	/* R */
 #define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
 #define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
 #define EXT_CSD_WR_REL_PARAM		166	/* R */
 #define EXT_CSD_WR_REL_SET		167	/* R/W */
 #define EXT_CSD_RPMB_MULT		168	/* RO */
 #define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
 #define EXT_CSD_BOOT_BUS_WIDTH		177
 #define EXT_CSD_PART_CONF		179	/* R/W */
 #define EXT_CSD_BUS_WIDTH		183	/* R/W */
 #define EXT_CSD_HS_TIMING		185	/* R/W */
 #define EXT_CSD_REV			192	/* RO */
 #define EXT_CSD_CARD_TYPE		196	/* RO */
 #define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
 #define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
 #define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
 #define EXT_CSD_BOOT_MULT		226	/* RO */
 /*
  * EXT_CSD field definitions
  */
 #define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
 #define EXT_CSD_CMD_SET_SECURE		(1 << 1)
 #define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)
 #define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
 #define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */
 #define EXT_CSD_CARD_TYPE_DDR_1_8V	(1 << 2)
 #define EXT_CSD_CARD_TYPE_DDR_1_2V	(1 << 3)
 #define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V \
 					| EXT_CSD_CARD_TYPE_DDR_1_2V)
 #define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
 #define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
 #define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
 #define EXT_CSD_DDR_BUS_WIDTH_4	5	/* Card is in 4 bit DDR mode */
 #define EXT_CSD_DDR_BUS_WIDTH_8	6	/* Card is in 8 bit DDR mode */
 #define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
 #define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
 #define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
 #define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)
 #define EXT_CSD_BOOT_ACK(x)		(x << 6)
 #define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
 #define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)
 #define EXT_CSD_PARTITION_SETTING_COMPLETED	(1 << 0)
 #define EXT_CSD_ENH_USR		(1 << 0)	/* user data area is enhanced */
 #define EXT_CSD_ENH_GP(x)	(1 << ((x)+1))	/* GP part (x+1) is enhanced */
 #define EXT_CSD_HS_CTRL_REL	(1 << 0)	/* host controlled WR_REL_SET */
 #define EXT_CSD_WR_DATA_REL_USR		(1 << 0)	/* user data area WR_REL */
 #define EXT_CSD_WR_DATA_REL_GP(x)	(1 << ((x)+1))	/* GP part (x+1) WR_REL */
 #define R1_ILLEGAL_COMMAND		(1 << 22)
 #define R1_APP_CMD			(1 << 5)
 #define MMC_RSP_PRESENT (1 << 0)
 #define MMC_RSP_136	(1 << 1)		/* 136 bit response */
 #define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
 #define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
 #define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */
 #define MMC_RSP_NONE	(0)
 #define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 #define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 			MMC_RSP_BUSY)
 #define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 #define MMC_RSP_R3	(MMC_RSP_PRESENT)
 #define MMC_RSP_R4	(MMC_RSP_PRESENT)
 #define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 #define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 #define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 #define MMCPART_NOAVAILABLE	(0xff)
 #define PART_ACCESS_MASK	(0x7)
 #define PART_SUPPORT		(0x1)
 #define ENHNCD_SUPPORT		(0x2)
 #define PART_ENH_ATTRIB		(0x1f)
 /* Maximum block size for MMC */
 #define MMC_MAX_BLOCK_LEN	512
 /* The number of MMC physical partitions.  These consist of:
  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  */
 #define MMC_NUM_BOOT_PARTITION	2
 #define MMC_PART_RPMB           3       /* RPMB partition number */
 struct mmc_cid {
 	unsigned long psn;
 	unsigned short oid;
 	unsigned char mid;
 	unsigned char prv;
 	unsigned char mdt;
 	char pnm[7];
 };
 struct mmc_cmd {
 	ushort cmdidx;
 	uint resp_type;
 	uint cmdarg;
 	uint response[4];
 };
 struct mmc_data {
 	union {
 		char *dest;
 		const char *src; /* src buffers don't get written to */
 	};
 	uint flags;
 	uint blocks;
 	uint blocksize;
 };
 /* forward decl. */
 struct mmc;
 struct mmc_ops {
 	int (*send_cmd)(struct mmc *mmc,
 			struct mmc_cmd *cmd, struct mmc_data *data);
 	void (*set_ios)(struct mmc *mmc);
 	int (*init)(struct mmc *mmc);
 	int (*getcd)(struct mmc *mmc);
 	int (*getwp)(struct mmc *mmc);
 };
 struct mmc_config {
 	const char *name;
 	const struct mmc_ops *ops;
 	uint host_caps;
 	uint voltages;
 	uint f_min;
 	uint f_max;
 	uint b_max;
 	unsigned char part_type;
 };
 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 struct mmc {
 	struct list_head link;
 	const struct mmc_config *cfg;	/* provided configuration */
 	uint version;
 	void *priv;
 	uint has_init;
 	int high_capacity;
 	uint bus_width;
 	uint clock;
 	uint card_caps;
 	uint ocr;
 	uint dsr;
 	uint dsr_imp;
 	uint scr[2];
 	uint csd[4];
 	uint cid[4];
 	ushort rca;
 	u8 part_support;
 	u8 part_attr;
 	u8 wr_rel_set;
 	char part_config;
 	char part_num;
 	uint tran_speed;
 	uint read_bl_len;
 	uint write_bl_len;
 	uint erase_grp_size;	/* in 512-byte sectors */
 	uint hc_wp_grp_size;	/* in 512-byte sectors */
 	u64 capacity;
 	u64 capacity_user;
 	u64 capacity_boot;
 	u64 capacity_rpmb;
 	u64 capacity_gp[4];
 	u64 enh_user_start;
 	u64 enh_user_size;
 	block_dev_desc_t block_dev;
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
 	int ddr_mode;
 };
 struct mmc_hwpart_conf {
 	struct {
 		uint enh_start;	/* in 512-byte sectors */
 		uint enh_size;	/* in 512-byte sectors, if 0 no enh area */
 		unsigned wr_rel_change : 1;
 		unsigned wr_rel_set : 1;
 	} user;
 	struct {
 		uint size;	/* in 512-byte sectors */
 		unsigned enhanced : 1;
 		unsigned wr_rel_change : 1;
 		unsigned wr_rel_set : 1;
 	} gp_part[4];
 };
 enum mmc_hwpart_conf_mode {
 	MMC_HWPART_CONF_CHECK,
 	MMC_HWPART_CONF_SET,
 	MMC_HWPART_CONF_COMPLETE,
 };
 int mmc_register(struct mmc *mmc);
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 void mmc_destroy(struct mmc *mmc);
 int mmc_initialize(bd_t *bis);
 int mmc_init(struct mmc *mmc);
 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 void mmc_set_clock(struct mmc *mmc, uint clock);
 struct mmc *find_mmc_device(int dev_num);
 int mmc_set_dev(int dev_num);
 void print_mmc_devices(char separator);
 int get_mmc_num(void);
 int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode);
 int mmc_getcd(struct mmc *mmc);
 int board_mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
 int board_mmc_getwp(struct mmc *mmc);
 int mmc_set_dsr(struct mmc *mmc, u16 val);
 /* Function to change the size of boot partition and rpmb partitions */
 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 					unsigned long rpmbsize);
 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 /* Functions to read / write the RPMB partition */
 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 		  unsigned short cnt, unsigned char *key);
 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 		   unsigned short cnt, unsigned char *key);
 /**
  * Start device initialization and return immediately; it does not block on
  * polling OCR (operation condition register) status.  Then you should call
  * mmc_init, which would block on polling OCR status and complete the device
  * initializatin.
  *
  * @param mmc	Pointer to a MMC device struct
  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
  */
 int mmc_start_init(struct mmc *mmc);
 /**
  * Set preinit flag of mmc device.
  *
  * This will cause the device to be pre-inited during mmc_initialize(),
  * which may save boot time if the device is not accessed until later.
  * Some eMMC devices take 200-300ms to init, but unfortunately they
  * must be sent a series of commands to even get them to start preparing
  * for operation.
  *
  * @param mmc		Pointer to a MMC device struct
  * @param preinit	preinit flag value
  */
 void mmc_set_preinit(struct mmc *mmc, int preinit);
 #ifdef CONFIG_GENERIC_MMC
 #ifdef CONFIG_MMC_SPI
 #define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
 #else
 #define mmc_host_is_spi(mmc)	0
 #endif
 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 #else
 int mmc_legacy_init(int verbose);
 #endif
 void board_mmc_power_init(void);
 int board_mmc_init(bd_t *bis);
 int cpu_mmc_init(bd_t *bis);
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 struct pci_device_id;
 /**
  * pci_mmc_init() - set up PCI MMC devices
  *
  * This finds all the matching PCI IDs and sets them up as MMC devices.
  *
  * @name:		Name to use for devices
  * @mmc_supported:	PCI IDs to search for
  * @num_ids:		Number of elements in @mmc_supported
  */
 int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
 		 int num_ids);
 /* Set block count limit because of 16 bit register limit on some hardware*/
 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 #endif
 #endif /* _MMC_H_ */