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Commit 5a4696088376fff82629e7e4a2444294dc589c96

Authored by Timur Tabi
Committed by Kumar Gala
1 parent 2feb4af001
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

p2020ds: add alternate boot bank support using the ngPIXIS FPGA 

The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS.
The ngPIXIS has one distinct new feature: the values of the on-board switches
can be selectively overridden with shadow registers.  This feature is used to
boot from a different NOR flash bank, instead of having a register dedicated
for this purpose.  Because the ngPIXIS is so different from the previous PIXIS,
a new file is introduced: ngpixis.c.

Also update the P2020DS checkboard() function to use the new macros defined
in the header file.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 5 changed files with 222 additions and 89 deletions Inline Diff

board/freescale/common/Makefile
Diff comments   View file @ 5a46960
1 # 1 #
2 # (C) Copyright 2006 2 # (C) Copyright 2006
3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 # 4 #
5 # See file CREDITS for list of people who contributed to this 5 # See file CREDITS for list of people who contributed to this
6 # project. 6 # project.
7 # 7 #
8 # This program is free software; you can redistribute it and/or 8 # This program is free software; you can redistribute it and/or
9 # modify it under the terms of the GNU General Public License as 9 # modify it under the terms of the GNU General Public License as
10 # published by the Free Software Foundation; either version 2 of 10 # published by the Free Software Foundation; either version 2 of
11 # the License, or (at your option) any later version. 11 # the License, or (at your option) any later version.
12 # 12 #
13 # This program is distributed in the hope that it will be useful, 13 # This program is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of 14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details. 16 # GNU General Public License for more details.
17 # 17 #
18 # You should have received a copy of the GNU General Public License 18 # You should have received a copy of the GNU General Public License
19 # along with this program; if not, write to the Free Software 19 # along with this program; if not, write to the Free Software
20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 # MA 02111-1307 USA 21 # MA 02111-1307 USA
22 # 22 #
23 23
24 include $(TOPDIR)/config.mk 24 include $(TOPDIR)/config.mk
25 25
26 ifneq ($(OBJTREE),$(SRCTREE)) 26 ifneq ($(OBJTREE),$(SRCTREE))
27 $(shell mkdir -p $(obj)board/$(VENDOR)/common) 27 $(shell mkdir -p $(obj)board/$(VENDOR)/common)
28 endif 28 endif
29 29
30 LIB = $(obj)lib$(VENDOR).a 30 LIB = $(obj)lib$(VENDOR).a
31 31
32 COBJS-${CONFIG_FSL_CADMUS} += cadmus.o 32 COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
33 COBJS-${CONFIG_FSL_VIA} += cds_via.o 33 COBJS-${CONFIG_FSL_VIA} += cds_via.o
34 COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o 34 COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
35 COBJS-${CONFIG_FSL_PIXIS} += pixis.o 35 COBJS-${CONFIG_FSL_PIXIS} += pixis.o
36 COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
36 COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o 37 COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
37 COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o 38 COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
38 COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o 39 COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
39 40
40 COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o 41 COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o
41 COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o 42 COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o
42 COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o 43 COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o
43 44
44 45
45 SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) 46 SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
46 OBJS := $(addprefix $(obj),$(COBJS-y)) 47 OBJS := $(addprefix $(obj),$(COBJS-y))
47 SOBJS := $(addprefix $(obj),$(SOBJS)) 48 SOBJS := $(addprefix $(obj),$(SOBJS))
48 49
49 $(LIB): $(obj).depend $(OBJS) 50 $(LIB): $(obj).depend $(OBJS)
50 $(AR) $(ARFLAGS) $@ $(OBJS) 51 $(AR) $(ARFLAGS) $@ $(OBJS)
51 52
52 clean: 53 clean:
53 rm -f $(SOBJS) $(OBJS) 54 rm -f $(SOBJS) $(OBJS)
54 55
55 distclean: clean 56 distclean: clean
56 rm -f $(LIB) core *.bak $(obj).depend 57 rm -f $(LIB) core *.bak $(obj).depend
57 58
58 ######################################################################### 59 #########################################################################
59 60
60 # defines $(obj).depend target 61 # defines $(obj).depend target
61 include $(SRCTREE)/rules.mk 62 include $(SRCTREE)/rules.mk
62 63
63 sinclude $(obj).depend 64 sinclude $(obj).depend
64 65
65 ######################################################################### 66 #########################################################################
66 67
board/freescale/common/ngpixis.c
Diff comments   View file @ 5a46960
File was created 1 /**
2 * Copyright 2010 Freescale Semiconductor
3 * Author: Timur Tabi <timur@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or (at your option)
8 * any later version.
9 *
10 * This file provides support for the ngPIXIS, a board-specific FPGA used on
11 * some Freescale reference boards.
12 *
13 * A "switch" is black rectangular block on the motherboard. It contains
14 * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
15 * shadow the actual physical switches. There is also another set of
16 * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
17 * used to override the values of the bits in the physical switches.
18 *
19 * The following macros need to be defined:
20 *
21 * PIXIS_BASE - The virtual address of the base of the PIXIS register map
22 *
23 * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
24 * is used in the PIXIS_SW() macro to determine which offset in
25 * the PIXIS register map corresponds to the physical switch that controls
26 * the boot bank.
27 *
28 * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
29 *
30 * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
31 *
32 * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
33 * boot from the alternate bank.
34 */
35
36 #include <common.h>
37 #include <command.h>
38 #include <watchdog.h>
39 #include <asm/cache.h>
40 #include <asm/io.h>
41
42 #include "ngpixis.h"
43
44 /*
45 * Reset the board. This ignores the ENx registers.
46 */
47 void pixis_reset(void)
48 {
49 out_8(&pixis->rst, 0);
50
51 while (1);
52 }
53
54 /*
55 * Reset the board. Like pixis_reset(), but it honors the ENx registers.
56 */
57 void pixis_bank_reset(void)
58 {
59 out_8(&pixis->vctl, 0);
60 out_8(&pixis->vctl, 1);
61
62 while (1);
63 }
64
65 /**
66 * Set the boot bank to the power-on default bank
67 */
68 void clear_altbank(void)
69 {
70 /* Tell the ngPIXIS to use this the bits in the physical switch for the
71 * boot bank value, instead of the SWx register. We need to be careful
72 * only to set the bits in SWx that correspond to the boot bank.
73 */
74 clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
75 }
76
77 /**
78 * Set the boot bank to the alternate bank
79 */
80 void set_altbank(void)
81 {
82 /* Program the alternate bank number into the SWx register.
83 */
84 clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
85 PIXIS_LBMAP_ALTBANK);
86
87 /* Tell the ngPIXIS to use this the bits in the SWx register for the
88 * boot bank value, instead of the physical switch. We need to be
89 * careful only to set the bits in SWx that correspond to the boot bank.
90 */
91 setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
92 }
93
94
95 int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
96 {
97 unsigned int i;
98 char *p_altbank = NULL;
99 char *unknown_param = NULL;
100
101 /* No args is a simple reset request.
102 */
103 if (argc <= 1)
104 pixis_reset();
105
106 for (i = 1; i < argc; i++) {
107 if (strcmp(argv[i], "altbank") == 0) {
108 p_altbank = argv[i];
109 continue;
110 }
111
112 unknown_param = argv[i];
113 }
114
115 if (unknown_param) {
116 printf("Invalid option: %s\n", unknown_param);
117 return 1;
118 }
119
120 if (p_altbank)
121 set_altbank();
122 else
123 clear_altbank();
124
125 pixis_bank_reset();
126
127 /* Shouldn't be reached. */
128 return 0;
129 }
130
131 U_BOOT_CMD(
132 pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
133 "Reset the board using the FPGA sequencer",
134 "- hard reset to default bank\n"
135 "pixis_reset altbank - reset to alternate bank\n"
136 );
137
board/freescale/common/ngpixis.h
Diff comments   View file @ 5a46960
File was created 1 /**
2 * Copyright 2010 Freescale Semiconductor
3 * Author: Timur Tabi <timur@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or (at your option)
8 * any later version.
9 *
10 * This file provides support for the ngPIXIS, a board-specific FPGA used on
11 * some Freescale reference boards.
12 */
13
14 /* ngPIXIS register set. Hopefully, this won't change too much over time.
15 * Feel free to add board-specific #ifdefs where necessary.
16 */
17 typedef struct ngpixis {
18 u8 id;
19 u8 arch;
20 u8 scver;
21 u8 csr;
22 u8 rst;
23 u8 res1;
24 u8 aux;
25 u8 spd;
26 u8 brdcfg0;
27 u8 dma;
28 u8 addr;
29 u8 res2[2];
30 u8 data;
31 u8 led;
32 u8 res3;
33 u8 vctl;
34 u8 vstat;
35 u8 vcfgen0;
36 u8 res4;
37 u8 ocmcsr;
38 u8 ocmmsg;
39 u8 gmdbg;
40 u8 res5[2];
41 u8 sclk[3];
42 u8 dclk[3];
43 u8 watch;
44 struct {
45 u8 sw;
46 u8 en;
47 } s[8];
48 } ngpixis_t __attribute__ ((aligned(1)));
49
50 /* Pointer to the PIXIS register set */
51 #define pixis ((ngpixis_t *)PIXIS_BASE)
52
53 /* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
54 #define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
55
56 /* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
57 #define PIXIS_EN(x) (pixis->s[(x) - 1].en)
58
board/freescale/p2020ds/p2020ds.c
Diff comments   View file @ 5a46960
1 /* 1 /*
2 * Copyright 2007-2009 Freescale Semiconductor, Inc. 2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #include <common.h> 23 #include <common.h>
24 #include <command.h> 24 #include <command.h>
25 #include <pci.h> 25 #include <pci.h>
26 #include <asm/processor.h> 26 #include <asm/processor.h>
27 #include <asm/mmu.h> 27 #include <asm/mmu.h>
28 #include <asm/cache.h> 28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h> 29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h> 30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/io.h> 32 #include <asm/io.h>
33 #include <miiphy.h> 33 #include <miiphy.h>
34 #include <libfdt.h> 34 #include <libfdt.h>
35 #include <fdt_support.h> 35 #include <fdt_support.h>
36 #include <tsec.h> 36 #include <tsec.h>
37 #include <asm/fsl_law.h> 37 #include <asm/fsl_law.h>
38 #include <asm/mp.h> 38 #include <asm/mp.h>
39 #include <netdev.h> 39 #include <netdev.h>
40 40
41 #include "../common/ngpixis.h"
41 #include "../common/sgmii_riser.h" 42 #include "../common/sgmii_riser.h"
42 43
43 DECLARE_GLOBAL_DATA_PTR; 44 DECLARE_GLOBAL_DATA_PTR;
44 45
45 phys_size_t fixed_sdram(void); 46 phys_size_t fixed_sdram(void);
46 47
47 int checkboard(void) 48 int checkboard(void)
48 { 49 {
49 u8 sw7; 50 u8 sw;
50 u8 *pixis_base = (u8 *)PIXIS_BASE;
51 51
52 puts("Board: P2020DS "); 52 puts("Board: P2020DS ");
53 #ifdef CONFIG_PHYS_64BIT 53 #ifdef CONFIG_PHYS_64BIT
54 puts("(36-bit addrmap) "); 54 puts("(36-bit addrmap) ");
55 #endif 55 #endif
56 56
57 printf("Sys ID: 0x%02x, " 57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 58 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
59 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
60 in_8(pixis_base + PIXIS_PVER));
61 59
62 sw7 = in_8(pixis_base + PIXIS_SW(7)); 60 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
63 switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) { 61 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
64 case 0:
65 case 1:
66 printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
67 break;
68 case 2:
69 case 3:
70 puts ("Promjet\n");
71 break;
72 }
73 62
63 if (sw < 0x8)
64 /* The lower two bits are the actual vbank number */
65 printf("vBank: %d\n", sw & 3);
66 else
67 puts("Promjet\n");
68
74 return 0; 69 return 0;
75 } 70 }
76 71
77 phys_size_t initdram(int board_type) 72 phys_size_t initdram(int board_type)
78 { 73 {
79 phys_size_t dram_size = 0; 74 phys_size_t dram_size = 0;
80 75
81 puts("Initializing...."); 76 puts("Initializing....");
82 77
83 #ifdef CONFIG_SPD_EEPROM 78 #ifdef CONFIG_SPD_EEPROM
84 dram_size = fsl_ddr_sdram(); 79 dram_size = fsl_ddr_sdram();
85 #else 80 #else
86 dram_size = fixed_sdram(); 81 dram_size = fixed_sdram();
87 82
88 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 83 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
89 dram_size, 84 dram_size,
90 LAW_TRGT_IF_DDR) < 0) { 85 LAW_TRGT_IF_DDR) < 0) {
91 printf("ERROR setting Local Access Windows for DDR\n"); 86 printf("ERROR setting Local Access Windows for DDR\n");
92 return 0; 87 return 0;
93 }; 88 };
94 #endif 89 #endif
95 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 90 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
96 dram_size *= 0x100000; 91 dram_size *= 0x100000;
97 92
98 puts(" DDR: "); 93 puts(" DDR: ");
99 return dram_size; 94 return dram_size;
100 } 95 }
101 96
102 #if !defined(CONFIG_SPD_EEPROM) 97 #if !defined(CONFIG_SPD_EEPROM)
103 /* 98 /*
104 * Fixed sdram init -- doesn't use serial presence detect. 99 * Fixed sdram init -- doesn't use serial presence detect.
105 */ 100 */
106 101
107 phys_size_t fixed_sdram(void) 102 phys_size_t fixed_sdram(void)
108 { 103 {
109 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 104 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
110 uint d_init; 105 uint d_init;
111 106
112 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 107 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
113 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 108 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
114 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 109 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
115 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 110 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
116 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 111 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
117 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL; 112 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
118 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 113 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
119 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 114 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
120 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 115 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
121 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 116 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
122 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL; 117 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
123 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL; 118 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
124 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1; 119 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
125 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4; 120 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
126 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5; 121 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
127 122
128 if (!strcmp("performance", getenv("perf_mode"))) { 123 if (!strcmp("performance", getenv("perf_mode"))) {
129 /* Performance Mode Values */ 124 /* Performance Mode Values */
130 125
131 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF; 126 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
132 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF; 127 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
133 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF; 128 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
134 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; 129 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
135 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; 130 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
136 131
137 asm("sync;isync"); 132 asm("sync;isync");
138 133
139 udelay(500); 134 udelay(500);
140 135
141 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF; 136 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
142 } else { 137 } else {
143 /* Stable Mode Values */ 138 /* Stable Mode Values */
144 139
145 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; 140 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
146 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 141 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
147 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; 142 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
148 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 143 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
149 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 144 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
150 145
151 /* ECC will be assumed in stable mode */ 146 /* ECC will be assumed in stable mode */
152 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
153 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
154 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
155 150
156 asm("sync;isync"); 151 asm("sync;isync");
157 152
158 udelay(500); 153 udelay(500);
159 154
160 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
161 } 156 }
162 157
163 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 158 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
164 d_init = 1; 159 d_init = 1;
165 debug("DDR - 1st controller: memory initializing\n"); 160 debug("DDR - 1st controller: memory initializing\n");
166 /* 161 /*
167 * Poll until memory is initialized. 162 * Poll until memory is initialized.
168 * 512 Meg at 400 might hit this 200 times or so. 163 * 512 Meg at 400 might hit this 200 times or so.
169 */ 164 */
170 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 165 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
171 udelay(1000); 166 udelay(1000);
172 debug("DDR: memory initialized\n\n"); 167 debug("DDR: memory initialized\n\n");
173 asm("sync; isync"); 168 asm("sync; isync");
174 udelay(500); 169 udelay(500);
175 #endif 170 #endif
176 171
177 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 172 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
178 } 173 }
179 174
180 #endif 175 #endif
181 176
182 #ifdef CONFIG_PCIE1 177 #ifdef CONFIG_PCIE1
183 static struct pci_controller pcie1_hose; 178 static struct pci_controller pcie1_hose;
184 #endif 179 #endif
185 180
186 #ifdef CONFIG_PCIE2 181 #ifdef CONFIG_PCIE2
187 static struct pci_controller pcie2_hose; 182 static struct pci_controller pcie2_hose;
188 #endif 183 #endif
189 184
190 #ifdef CONFIG_PCIE3 185 #ifdef CONFIG_PCIE3
191 static struct pci_controller pcie3_hose; 186 static struct pci_controller pcie3_hose;
192 #endif 187 #endif
193 188
194 #ifdef CONFIG_PCI 189 #ifdef CONFIG_PCI
195 void pci_init_board(void) 190 void pci_init_board(void)
196 { 191 {
197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 192 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
198 struct fsl_pci_info pci_info[3]; 193 struct fsl_pci_info pci_info[3];
199 u32 devdisr, pordevsr, io_sel; 194 u32 devdisr, pordevsr, io_sel;
200 int first_free_busno = 0; 195 int first_free_busno = 0;
201 int num = 0; 196 int num = 0;
202 197
203 int pcie_ep, pcie_configured; 198 int pcie_ep, pcie_configured;
204 199
205 devdisr = in_be32(&gur->devdisr); 200 devdisr = in_be32(&gur->devdisr);
206 pordevsr = in_be32(&gur->pordevsr); 201 pordevsr = in_be32(&gur->pordevsr);
207 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 202 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
208 203
209 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 204 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
210 205
211 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 206 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
212 printf(" eTSEC2 is in sgmii mode.\n"); 207 printf(" eTSEC2 is in sgmii mode.\n");
213 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 208 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
214 printf(" eTSEC3 is in sgmii mode.\n"); 209 printf(" eTSEC3 is in sgmii mode.\n");
215 210
216 puts("\n"); 211 puts("\n");
217 #ifdef CONFIG_PCIE2 212 #ifdef CONFIG_PCIE2
218 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 213 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
219 214
220 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { 215 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
221 SET_STD_PCIE_INFO(pci_info[num], 2); 216 SET_STD_PCIE_INFO(pci_info[num], 2);
222 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 217 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
223 printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", 218 printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
224 pcie_ep ? "Endpoint" : "Root Complex", 219 pcie_ep ? "Endpoint" : "Root Complex",
225 pci_info[num].regs); 220 pci_info[num].regs);
226 first_free_busno = fsl_pci_init_port(&pci_info[num++], 221 first_free_busno = fsl_pci_init_port(&pci_info[num++],
227 &pcie2_hose, first_free_busno); 222 &pcie2_hose, first_free_busno);
228 223
229 /* 224 /*
230 * The workaround doesn't work on p2020 because the location 225 * The workaround doesn't work on p2020 because the location
231 * we try and read isn't valid on p2020, fix this later 226 * we try and read isn't valid on p2020, fix this later
232 */ 227 */
233 #if 0 228 #if 0
234 /* 229 /*
235 * Activate ULI1575 legacy chip by performing a fake 230 * Activate ULI1575 legacy chip by performing a fake
236 * memory access. Needed to make ULI RTC work. 231 * memory access. Needed to make ULI RTC work.
237 * Device 1d has the first on-board memory BAR. 232 * Device 1d has the first on-board memory BAR.
238 */ 233 */
239 234
240 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0), 235 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
241 PCI_BASE_ADDRESS_1, &temp32); 236 PCI_BASE_ADDRESS_1, &temp32);
242 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 237 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
243 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 238 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
244 temp32, 4, 0); 239 temp32, 4, 0);
245 debug(" uli1575 read to %p\n", p); 240 debug(" uli1575 read to %p\n", p);
246 in_be32(p); 241 in_be32(p);
247 } 242 }
248 #endif 243 #endif
249 } else { 244 } else {
250 printf(" PCIE2: disabled\n"); 245 printf(" PCIE2: disabled\n");
251 } 246 }
252 puts("\n"); 247 puts("\n");
253 #else 248 #else
254 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 249 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
255 #endif 250 #endif
256 251
257 #ifdef CONFIG_PCIE3 252 #ifdef CONFIG_PCIE3
258 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 253 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
259 254
260 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { 255 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
261 SET_STD_PCIE_INFO(pci_info[num], 3); 256 SET_STD_PCIE_INFO(pci_info[num], 3);
262 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 257 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
263 printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", 258 printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
264 pcie_ep ? "Endpoint" : "Root Complex", 259 pcie_ep ? "Endpoint" : "Root Complex",
265 pci_info[num].regs); 260 pci_info[num].regs);
266 first_free_busno = fsl_pci_init_port(&pci_info[num++], 261 first_free_busno = fsl_pci_init_port(&pci_info[num++],
267 &pcie3_hose, first_free_busno); 262 &pcie3_hose, first_free_busno);
268 } else { 263 } else {
269 printf(" PCIE3: disabled\n"); 264 printf(" PCIE3: disabled\n");
270 } 265 }
271 puts("\n"); 266 puts("\n");
272 #else 267 #else
273 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 268 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
274 #endif 269 #endif
275 270
276 #ifdef CONFIG_PCIE1 271 #ifdef CONFIG_PCIE1
277 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 272 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
278 273
279 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { 274 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
280 SET_STD_PCIE_INFO(pci_info[num], 1); 275 SET_STD_PCIE_INFO(pci_info[num], 1);
281 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 276 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
282 printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", 277 printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
283 pcie_ep ? "Endpoint" : "Root Complex", 278 pcie_ep ? "Endpoint" : "Root Complex",
284 pci_info[num].regs); 279 pci_info[num].regs);
285 first_free_busno = fsl_pci_init_port(&pci_info[num++], 280 first_free_busno = fsl_pci_init_port(&pci_info[num++],
286 &pcie1_hose, first_free_busno); 281 &pcie1_hose, first_free_busno);
287 } else { 282 } else {
288 printf(" PCIE1: disabled\n"); 283 printf(" PCIE1: disabled\n");
289 } 284 }
290 puts("\n"); 285 puts("\n");
291 #else 286 #else
292 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 287 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
293 #endif 288 #endif
294 } 289 }
295 #endif 290 #endif
296 291
297 int board_early_init_r(void) 292 int board_early_init_r(void)
298 { 293 {
299 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 294 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
300 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 295 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
301 296
302 /* 297 /*
303 * Remap Boot flash + PROMJET region to caching-inhibited 298 * Remap Boot flash + PROMJET region to caching-inhibited
304 * so that flash can be erased properly. 299 * so that flash can be erased properly.
305 */ 300 */
306 301
307 /* Flush d-cache and invalidate i-cache of any FLASH data */ 302 /* Flush d-cache and invalidate i-cache of any FLASH data */
308 flush_dcache(); 303 flush_dcache();
309 invalidate_icache(); 304 invalidate_icache();
310 305
311 /* invalidate existing TLB entry for flash + promjet */ 306 /* invalidate existing TLB entry for flash + promjet */
312 disable_tlb(flash_esel); 307 disable_tlb(flash_esel);
313 308
314 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 309 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
315 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 310 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
316 0, flash_esel, BOOKE_PAGESZ_256M, 1); 311 0, flash_esel, BOOKE_PAGESZ_256M, 1);
317 312
318 return 0; 313 return 0;
319 } 314 }
320 315
321 #ifdef CONFIG_GET_CLK_FROM_ICS307 316 #ifdef CONFIG_GET_CLK_FROM_ICS307
322 /* decode S[0-2] to Output Divider (OD) */ 317 /* decode S[0-2] to Output Divider (OD) */
323 static unsigned char ics307_S_to_OD[] = { 318 static unsigned char ics307_S_to_OD[] = {
324 10, 2, 8, 4, 5, 7, 3, 6 319 10, 2, 8, 4, 5, 7, 3, 6
325 }; 320 };
326 321
327 /* Calculate frequency being generated by ICS307-02 clock chip based upon 322 /* Calculate frequency being generated by ICS307-02 clock chip based upon
328 * the control bytes being programmed into it. */ 323 * the control bytes being programmed into it. */
329 /* XXX: This function should probably go into a common library */ 324 /* XXX: This function should probably go into a common library */
330 static unsigned long 325 static unsigned long
331 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2) 326 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
332 { 327 {
333 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 328 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
334 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 329 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
335 unsigned long RDW = cw2 & 0x7F; 330 unsigned long RDW = cw2 & 0x7F;
336 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 331 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
337 unsigned long freq; 332 unsigned long freq;
338 333
339 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 334 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
340 335
341 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 336 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
342 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 337 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
343 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 338 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
344 * 339 *
345 * R6:R0 = Reference Divider Word (RDW) 340 * R6:R0 = Reference Divider Word (RDW)
346 * V8:V0 = VCO Divider Word (VDW) 341 * V8:V0 = VCO Divider Word (VDW)
347 * S2:S0 = Output Divider Select (OD) 342 * S2:S0 = Output Divider Select (OD)
348 * F1:F0 = Function of CLK2 Output 343 * F1:F0 = Function of CLK2 Output
349 * TTL = duty cycle 344 * TTL = duty cycle
350 * C1:C0 = internal load capacitance for cyrstal 345 * C1:C0 = internal load capacitance for cyrstal
351 */ 346 */
352 347
353 /* Adding 1 to get a "nicely" rounded number, but this needs 348 /* Adding 1 to get a "nicely" rounded number, but this needs
354 * more tweaking to get a "properly" rounded number. */ 349 * more tweaking to get a "properly" rounded number. */
355 350
356 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 351 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
357 352
358 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, 353 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
359 freq); 354 freq);
360 return freq; 355 return freq;
361 } 356 }
362 357
363 unsigned long get_board_sys_clk(ulong dummy) 358 unsigned long get_board_sys_clk(ulong dummy)
364 { 359 {
365 return gd->bus_clk; 360 return gd->bus_clk;
366 } 361 }
367 362
368 unsigned long get_board_ddr_clk(ulong dummy) 363 unsigned long get_board_ddr_clk(ulong dummy)
369 { 364 {
370 return gd->mem_clk; 365 return gd->mem_clk;
371 } 366 }
372 367
373 unsigned long 368 unsigned long calculate_board_sys_clk(ulong dummy)
374 calculate_board_sys_clk(ulong dummy)
375 { 369 {
376 ulong val; 370 ulong val;
377 u8 *pixis_base = (u8 *)PIXIS_BASE;
378 371
379 val = ics307_clk_freq( 372 val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
380 in_8(pixis_base + PIXIS_VSYSCLK0), 373 in_8(&pixis->sclk[2]));
381 in_8(pixis_base + PIXIS_VSYSCLK1),
382 in_8(pixis_base + PIXIS_VSYSCLK2));
383 debug("sysclk val = %lu\n", val); 374 debug("sysclk val = %lu\n", val);
384 return val; 375 return val;
385 } 376 }
386 377
387 unsigned long 378 unsigned long calculate_board_ddr_clk(ulong dummy)
388 calculate_board_ddr_clk(ulong dummy)
389 { 379 {
390 ulong val; 380 ulong val;
391 u8 *pixis_base = (u8 *)PIXIS_BASE;
392 381
393 val = ics307_clk_freq( 382 val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
394 in_8(pixis_base + PIXIS_VDDRCLK0), 383 in_8(&pixis->dclk[2]));
395 in_8(pixis_base + PIXIS_VDDRCLK1),
396 in_8(pixis_base + PIXIS_VDDRCLK2));
397 debug("ddrclk val = %lu\n", val); 384 debug("ddrclk val = %lu\n", val);
398 return val; 385 return val;
399 } 386 }
400 #else 387 #else
401 unsigned long get_board_sys_clk(ulong dummy) 388 unsigned long get_board_sys_clk(ulong dummy)
402 { 389 {
403 u8 i; 390 u8 i;
404 ulong val = 0; 391 ulong val = 0;
405 u8 *pixis_base = (u8 *)PIXIS_BASE;
406 392
407 i = in_8(pixis_base + PIXIS_SPD); 393 i = in_8(&pixis->spd);
408 i &= 0x07; 394 i &= 0x07;
409 395
410 switch (i) { 396 switch (i) {
411 case 0: 397 case 0:
412 val = 33333333; 398 val = 33333333;
413 break; 399 break;
414 case 1: 400 case 1:
415 val = 40000000; 401 val = 40000000;
416 break; 402 break;
417 case 2: 403 case 2:
418 val = 50000000; 404 val = 50000000;
419 break; 405 break;
420 case 3: 406 case 3:
421 val = 66666666; 407 val = 66666666;
422 break; 408 break;
423 case 4: 409 case 4:
424 val = 83333333; 410 val = 83333333;
425 break; 411 break;
426 case 5: 412 case 5:
427 val = 100000000; 413 val = 100000000;
428 break; 414 break;
429 case 6: 415 case 6:
430 val = 133333333; 416 val = 133333333;
431 break; 417 break;
432 case 7: 418 case 7:
433 val = 166666666; 419 val = 166666666;
434 break; 420 break;
435 } 421 }
436 422
437 return val; 423 return val;
438 } 424 }
439 425
440 unsigned long get_board_ddr_clk(ulong dummy) 426 unsigned long get_board_ddr_clk(ulong dummy)
441 { 427 {
442 u8 i; 428 u8 i;
443 ulong val = 0; 429 ulong val = 0;
444 u8 *pixis_base = (u8 *)PIXIS_BASE;
445 430
446 i = in_8(pixis_base + PIXIS_SPD); 431 i = in_8(&pixis->spd);
447 i &= 0x38; 432 i &= 0x38;
448 i >>= 3; 433 i >>= 3;
449 434
450 switch (i) { 435 switch (i) {
451 case 0: 436 case 0:
452 val = 33333333; 437 val = 33333333;
453 break; 438 break;
454 case 1: 439 case 1:
455 val = 40000000; 440 val = 40000000;
456 break; 441 break;
457 case 2: 442 case 2:
458 val = 50000000; 443 val = 50000000;
459 break; 444 break;
460 case 3: 445 case 3:
461 val = 66666666; 446 val = 66666666;
462 break; 447 break;
463 case 4: 448 case 4:
464 val = 83333333; 449 val = 83333333;
465 break; 450 break;
466 case 5: 451 case 5:
467 val = 100000000; 452 val = 100000000;
468 break; 453 break;
469 case 6: 454 case 6:
470 val = 133333333; 455 val = 133333333;
471 break; 456 break;
472 case 7: 457 case 7:
473 val = 166666666; 458 val = 166666666;
474 break; 459 break;
475 } 460 }
476 return val; 461 return val;
477 } 462 }
478 #endif 463 #endif
479 464
480 #ifdef CONFIG_TSEC_ENET 465 #ifdef CONFIG_TSEC_ENET
481 int board_eth_init(bd_t *bis) 466 int board_eth_init(bd_t *bis)
482 { 467 {
483 struct tsec_info_struct tsec_info[4]; 468 struct tsec_info_struct tsec_info[4];
484 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 469 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
485 int num = 0; 470 int num = 0;
486 471
487 #ifdef CONFIG_TSEC1 472 #ifdef CONFIG_TSEC1
488 SET_STD_TSEC_INFO(tsec_info[num], 1); 473 SET_STD_TSEC_INFO(tsec_info[num], 1);
489 num++; 474 num++;
490 #endif 475 #endif
491 #ifdef CONFIG_TSEC2 476 #ifdef CONFIG_TSEC2
492 SET_STD_TSEC_INFO(tsec_info[num], 2); 477 SET_STD_TSEC_INFO(tsec_info[num], 2);
493 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 478 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
494 tsec_info[num].flags |= TSEC_SGMII; 479 tsec_info[num].flags |= TSEC_SGMII;
495 num++; 480 num++;
496 #endif 481 #endif
497 #ifdef CONFIG_TSEC3 482 #ifdef CONFIG_TSEC3
498 SET_STD_TSEC_INFO(tsec_info[num], 3); 483 SET_STD_TSEC_INFO(tsec_info[num], 3);
499 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 484 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
500 tsec_info[num].flags |= TSEC_SGMII; 485 tsec_info[num].flags |= TSEC_SGMII;
501 num++; 486 num++;
502 #endif 487 #endif
503 488
504 if (!num) { 489 if (!num) {
505 printf("No TSECs initialized\n"); 490 printf("No TSECs initialized\n");
506 491
507 return 0; 492 return 0;
508 } 493 }
509 494
510 #ifdef CONFIG_FSL_SGMII_RISER 495 #ifdef CONFIG_FSL_SGMII_RISER
511 fsl_sgmii_riser_init(tsec_info, num); 496 fsl_sgmii_riser_init(tsec_info, num);
512 #endif 497 #endif
513 498
514 tsec_eth_init(bis, tsec_info, num); 499 tsec_eth_init(bis, tsec_info, num);
515 500
516 return pci_eth_init(bis); 501 return pci_eth_init(bis);
517 } 502 }
518 #endif 503 #endif
519 504
520 #if defined(CONFIG_OF_BOARD_SETUP) 505 #if defined(CONFIG_OF_BOARD_SETUP)
521 void ft_board_setup(void *blob, bd_t *bd) 506 void ft_board_setup(void *blob, bd_t *bd)
522 { 507 {
523 phys_addr_t base; 508 phys_addr_t base;
524 phys_size_t size; 509 phys_size_t size;
525 510
526 ft_cpu_setup(blob, bd); 511 ft_cpu_setup(blob, bd);
527 512
528 base = getenv_bootm_low(); 513 base = getenv_bootm_low();
529 size = getenv_bootm_size(); 514 size = getenv_bootm_size();
530 515
531 fdt_fixup_memory(blob, (u64)base, (u64)size); 516 fdt_fixup_memory(blob, (u64)base, (u64)size);
532 517
533 #ifdef CONFIG_PCIE3 518 #ifdef CONFIG_PCIE3
534 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); 519 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
535 #endif 520 #endif
536 #ifdef CONFIG_PCIE2 521 #ifdef CONFIG_PCIE2
537 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 522 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
538 #endif 523 #endif
539 #ifdef CONFIG_PCIE1 524 #ifdef CONFIG_PCIE1
540 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 525 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
541 #endif 526 #endif
542 #ifdef CONFIG_FSL_SGMII_RISER 527 #ifdef CONFIG_FSL_SGMII_RISER
543 fsl_sgmii_riser_fdt_fixup(blob); 528 fsl_sgmii_riser_fdt_fixup(blob);
544 #endif 529 #endif
545 } 530 }
546 #endif 531 #endif
547 532
include/configs/P2020DS.h
Diff comments   View file @ 5a46960
1 /* 1 /*
2 * Copyright 2007-2009 Freescale Semiconductor, Inc. 2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 /* 23 /*
24 * p2020ds board configuration file 24 * p2020ds board configuration file
25 * 25 *
26 */ 26 */
27 #ifndef __CONFIG_H 27 #ifndef __CONFIG_H
28 #define __CONFIG_H 28 #define __CONFIG_H
29 29
30 #ifdef CONFIG_MK_36BIT 30 #ifdef CONFIG_MK_36BIT
31 #define CONFIG_PHYS_64BIT 31 #define CONFIG_PHYS_64BIT
32 #endif 32 #endif
33 33
34 /* High Level Configuration Options */ 34 /* High Level Configuration Options */
35 #define CONFIG_BOOKE 1 /* BOOKE */ 35 #define CONFIG_BOOKE 1 /* BOOKE */
36 #define CONFIG_E500 1 /* BOOKE e500 family */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */
37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38 #define CONFIG_P2020 1 38 #define CONFIG_P2020 1
39 #define CONFIG_P2020DS 1 39 #define CONFIG_P2020DS 1
40 #define CONFIG_MP 1 /* support multiple processors */ 40 #define CONFIG_MP 1 /* support multiple processors */
41 41
42 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 42 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
43 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 43 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
44 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 44 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
45 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 45 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
46 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 46 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
48 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 48 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
50 50
51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
52 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 52 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
53 53
54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */
55 #define CONFIG_ENV_OVERWRITE 55 #define CONFIG_ENV_OVERWRITE
56 56
57 #ifndef __ASSEMBLY__ 57 #ifndef __ASSEMBLY__
58 extern unsigned long calculate_board_sys_clk(unsigned long dummy); 58 extern unsigned long calculate_board_sys_clk(unsigned long dummy);
59 extern unsigned long calculate_board_ddr_clk(unsigned long dummy); 59 extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
60 /* extern unsigned long get_board_sys_clk(unsigned long dummy); */ 60 /* extern unsigned long get_board_sys_clk(unsigned long dummy); */
61 /* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ 61 /* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
62 #endif 62 #endif
63 #define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ 63 #define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
67 from ICS307 instead of switches */ 67 from ICS307 instead of switches */
68 68
69 /* 69 /*
70 * These can be toggled for performance analysis, otherwise use default. 70 * These can be toggled for performance analysis, otherwise use default.
71 */ 71 */
72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */
73 #define CONFIG_BTB /* toggle branch predition */ 73 #define CONFIG_BTB /* toggle branch predition */
74 74
75 #define CONFIG_ENABLE_36BIT_PHYS 1 75 #define CONFIG_ENABLE_36BIT_PHYS 1
76 76
77 #ifdef CONFIG_PHYS_64BIT 77 #ifdef CONFIG_PHYS_64BIT
78 #define CONFIG_ADDR_MAP 1 78 #define CONFIG_ADDR_MAP 1
79 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 79 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
80 #endif 80 #endif
81 81
82 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 82 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
83 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 83 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
84 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 84 #define CONFIG_PANIC_HANG /* do not reset board on panic */
85 85
86 /* 86 /*
87 * Base addresses -- Note these are effective addresses where the 87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses) 88 * actual resources get mapped (not physical addresses)
89 */ 89 */
90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 91 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
92 #ifdef CONFIG_PHYS_64BIT 92 #ifdef CONFIG_PHYS_64BIT
93 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 93 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
94 #else 94 #else
95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
96 #endif 96 #endif
97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
98 98
99 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 99 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
100 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 100 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
101 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 101 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
102 102
103 /* DDR Setup */ 103 /* DDR Setup */
104 #define CONFIG_VERY_BIG_RAM 104 #define CONFIG_VERY_BIG_RAM
105 #define CONFIG_FSL_DDR3 1 105 #define CONFIG_FSL_DDR3 1
106 #undef CONFIG_FSL_DDR_INTERACTIVE 106 #undef CONFIG_FSL_DDR_INTERACTIVE
107 107
108 /* ECC will be enabled based on perf_mode environment variable */ 108 /* ECC will be enabled based on perf_mode environment variable */
109 /* #define CONFIG_DDR_ECC */ 109 /* #define CONFIG_DDR_ECC */
110 110
111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
112 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 112 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
113 113
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
116 116
117 #define CONFIG_NUM_DDR_CONTROLLERS 1 117 #define CONFIG_NUM_DDR_CONTROLLERS 1
118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
119 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 119 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
120 120
121 /* I2C addresses of SPD EEPROMs */ 121 /* I2C addresses of SPD EEPROMs */
122 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ 122 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
123 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 123 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
124 124
125 /* These are used when DDR doesn't use SPD. */ 125 /* These are used when DDR doesn't use SPD. */
126 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ 126 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
127 127
128 /* Default settings for "stable" mode */ 128 /* Default settings for "stable" mode */
129 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 129 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
130 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 130 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
131 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 131 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
132 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 132 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
133 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 133 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
134 #define CONFIG_SYS_DDR_TIMING_0 0x00330804 134 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
135 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 135 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
136 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 136 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
137 #define CONFIG_SYS_DDR_MODE_1 0x00421422 137 #define CONFIG_SYS_DDR_MODE_1 0x00421422
138 #define CONFIG_SYS_DDR_MODE_2 0x00000000 138 #define CONFIG_SYS_DDR_MODE_2 0x00000000
139 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 139 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
140 #define CONFIG_SYS_DDR_INTERVAL 0x61800100 140 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
141 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 141 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
142 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 142 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
143 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 143 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
144 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 144 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
145 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 145 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
146 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 146 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
147 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ 147 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
148 #define CONFIG_SYS_DDR_CONTROL2 0x24400011 148 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
149 #define CONFIG_SYS_DDR_CDR1 0x00040000 149 #define CONFIG_SYS_DDR_CDR1 0x00040000
150 #define CONFIG_SYS_DDR_CDR2 0x00000000 150 #define CONFIG_SYS_DDR_CDR2 0x00000000
151 151
152 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 152 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
153 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 153 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
154 #define CONFIG_SYS_DDR_SBE 0x00010000 154 #define CONFIG_SYS_DDR_SBE 0x00010000
155 155
156 /* Settings that differ for "performance" mode */ 156 /* Settings that differ for "performance" mode */
157 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ 157 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
158 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ 158 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
159 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 159 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
160 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 160 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
161 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce 161 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
162 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ 162 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
163 163
164 /* 164 /*
165 * The following set of values were tested for DDR2 165 * The following set of values were tested for DDR2
166 * with a DDR3 to DDR2 interposer 166 * with a DDR3 to DDR2 interposer
167 * 167 *
168 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 168 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
169 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 169 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
170 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 170 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
171 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 171 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
172 #define CONFIG_SYS_DDR_MODE_1 0x00480432 172 #define CONFIG_SYS_DDR_MODE_1 0x00480432
173 #define CONFIG_SYS_DDR_MODE_2 0x00000000 173 #define CONFIG_SYS_DDR_MODE_2 0x00000000
174 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 174 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
175 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 175 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
176 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 176 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
177 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 177 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
178 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 178 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
179 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 179 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
180 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 180 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
181 * 181 *
182 */ 182 */
183 183
184 #undef CONFIG_CLOCKS_IN_MHZ 184 #undef CONFIG_CLOCKS_IN_MHZ
185 185
186 /* 186 /*
187 * Memory map 187 * Memory map
188 * 188 *
189 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 189 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
190 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 190 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
191 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 191 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
192 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 192 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
193 * 193 *
194 * Localbus cacheable (TBD) 194 * Localbus cacheable (TBD)
195 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 195 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
196 * 196 *
197 * Localbus non-cacheable 197 * Localbus non-cacheable
198 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 198 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
199 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 199 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
200 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 200 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
201 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 201 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
202 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 202 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
203 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 203 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
204 */ 204 */
205 205
206 /* 206 /*
207 * Local Bus Definitions 207 * Local Bus Definitions
208 */ 208 */
209 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 209 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
210 #ifdef CONFIG_PHYS_64BIT 210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 211 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
212 #else 212 #else
213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
214 #endif 214 #endif
215 215
216 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 216 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
217 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 217 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
218 218
219 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 219 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
220 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 220 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
221 221
222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
223 #define CONFIG_SYS_FLASH_QUIET_TEST 223 #define CONFIG_SYS_FLASH_QUIET_TEST
224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
225 225
226 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 226 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
228 #undef CONFIG_SYS_FLASH_CHECKSUM 228 #undef CONFIG_SYS_FLASH_CHECKSUM
229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
231 231
232 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 232 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
233 233
234 #define CONFIG_FLASH_CFI_DRIVER 234 #define CONFIG_FLASH_CFI_DRIVER
235 #define CONFIG_SYS_FLASH_CFI 235 #define CONFIG_SYS_FLASH_CFI
236 #define CONFIG_SYS_FLASH_EMPTY_INFO 236 #define CONFIG_SYS_FLASH_EMPTY_INFO
237 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 237 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
238 238
239 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 239 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
240 240
241 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 241 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
242
243 #ifdef CONFIG_FSL_NGPIXIS
242 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 244 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
243 #ifdef CONFIG_PHYS_64BIT 245 #ifdef CONFIG_PHYS_64BIT
244 #define PIXIS_BASE_PHYS 0xfffdf0000ull 246 #define PIXIS_BASE_PHYS 0xfffdf0000ull
245 #else 247 #else
246 #define PIXIS_BASE_PHYS PIXIS_BASE 248 #define PIXIS_BASE_PHYS PIXIS_BASE
247 #endif 249 #endif
248 250
249 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 251 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
250 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 252 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
251 253
252 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 254 #define PIXIS_LBMAP_SWITCH 7
253 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 255 #define PIXIS_LBMAP_MASK 0xf0
254 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 256 #define PIXIS_LBMAP_SHIFT 4
255 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 257 #define PIXIS_LBMAP_ALTBANK 0x20
256 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 258 #endif
257 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
258 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
259 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
260 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
261 #define PIXIS_VCTL 0x10 /* VELA Control Register */
262 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
263 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
264 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
265 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
266 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
267 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
268 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
269 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
270 #define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
271 #define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
272 #define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
273 #define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
274 #define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
275 #define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
276
277 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
278 #define PIXIS_LED 0x25 /* LED Register */
279
280 #define PIXIS_SW(x) 0x20 + (x - 1) * 2
281 #define PIXIS_EN(x) 0x21 + (x - 1) * 2
282 #define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
283 #define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
284
285 /* old pixis referenced names */
286 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
287 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
288 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
289 #define PIXIS_VSPEED2_TSEC1SER 0x8
290 #define PIXIS_VSPEED2_TSEC2SER 0x4
291 #define PIXIS_VSPEED2_TSEC3SER 0x2
292 #define PIXIS_VSPEED2_TSEC4SER 0x1
293 #define PIXIS_VCFGEN1_TSEC1SER 0x20
294 #define PIXIS_VCFGEN1_TSEC2SER 0x20
295 #define PIXIS_VCFGEN1_TSEC3SER 0x20
296 #define PIXIS_VCFGEN1_TSEC4SER 0x20
297 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
298 | PIXIS_VSPEED2_TSEC2SER \
299 | PIXIS_VSPEED2_TSEC3SER \
300 | PIXIS_VSPEED2_TSEC4SER)
301 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
302 | PIXIS_VCFGEN1_TSEC2SER \
303 | PIXIS_VCFGEN1_TSEC3SER \
304 | PIXIS_VCFGEN1_TSEC4SER)
305 259
306 #define CONFIG_SYS_INIT_RAM_LOCK 1 260 #define CONFIG_SYS_INIT_RAM_LOCK 1
307 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 261 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
308 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 262 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
309 263
310 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 264 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
312 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 266 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
313 267
314 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 268 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
315 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 269 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
316 270
317 #define CONFIG_SYS_NAND_BASE 0xffa00000 271 #define CONFIG_SYS_NAND_BASE 0xffa00000
318 #ifdef CONFIG_PHYS_64BIT 272 #ifdef CONFIG_PHYS_64BIT
319 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 273 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
320 #else 274 #else
321 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 275 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
322 #endif 276 #endif
323 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 277 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
324 CONFIG_SYS_NAND_BASE + 0x40000, \ 278 CONFIG_SYS_NAND_BASE + 0x40000, \
325 CONFIG_SYS_NAND_BASE + 0x80000,\ 279 CONFIG_SYS_NAND_BASE + 0x80000,\
326 CONFIG_SYS_NAND_BASE + 0xC0000} 280 CONFIG_SYS_NAND_BASE + 0xC0000}
327 #define CONFIG_SYS_MAX_NAND_DEVICE 4 281 #define CONFIG_SYS_MAX_NAND_DEVICE 4
328 #define CONFIG_MTD_NAND_VERIFY_WRITE 282 #define CONFIG_MTD_NAND_VERIFY_WRITE
329 #define CONFIG_CMD_NAND 1 283 #define CONFIG_CMD_NAND 1
330 #define CONFIG_NAND_FSL_ELBC 1 284 #define CONFIG_NAND_FSL_ELBC 1
331 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 285 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
332 286
333 /* NAND flash config */ 287 /* NAND flash config */
334 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 288 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
335 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 289 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
336 | BR_PS_8 /* Port Size = 8bit */ \ 290 | BR_PS_8 /* Port Size = 8bit */ \
337 | BR_MS_FCM /* MSEL = FCM */ \ 291 | BR_MS_FCM /* MSEL = FCM */ \
338 | BR_V) /* valid */ 292 | BR_V) /* valid */
339 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 293 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
340 | OR_FCM_PGS /* Large Page*/ \ 294 | OR_FCM_PGS /* Large Page*/ \
341 | OR_FCM_CSCT \ 295 | OR_FCM_CSCT \
342 | OR_FCM_CST \ 296 | OR_FCM_CST \
343 | OR_FCM_CHT \ 297 | OR_FCM_CHT \
344 | OR_FCM_SCY_1 \ 298 | OR_FCM_SCY_1 \
345 | OR_FCM_TRLX \ 299 | OR_FCM_TRLX \
346 | OR_FCM_EHTR) 300 | OR_FCM_EHTR)
347 301
348 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 302 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
349 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 303 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
350 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 304 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
351 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 305 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
352 306
353 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 307 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
354 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 308 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
355 | BR_PS_8 /* Port Size = 8bit */ \ 309 | BR_PS_8 /* Port Size = 8bit */ \
356 | BR_MS_FCM /* MSEL = FCM */ \ 310 | BR_MS_FCM /* MSEL = FCM */ \
357 | BR_V) /* valid */ 311 | BR_V) /* valid */
358 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 312 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
359 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 313 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
360 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 314 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
361 | BR_PS_8 /* Port Size = 8bit */ \ 315 | BR_PS_8 /* Port Size = 8bit */ \
362 | BR_MS_FCM /* MSEL = FCM */ \ 316 | BR_MS_FCM /* MSEL = FCM */ \
363 | BR_V) /* valid */ 317 | BR_V) /* valid */
364 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 318 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
365 319
366 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 320 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
367 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 321 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
368 | BR_PS_8 /* Port Size = 8bit */ \ 322 | BR_PS_8 /* Port Size = 8bit */ \
369 | BR_MS_FCM /* MSEL = FCM */ \ 323 | BR_MS_FCM /* MSEL = FCM */ \
370 | BR_V) /* valid */ 324 | BR_V) /* valid */
371 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 325 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
372 326
373 /* Serial Port - controlled on board with jumper J8 327 /* Serial Port - controlled on board with jumper J8
374 * open - index 2 328 * open - index 2
375 * shorted - index 1 329 * shorted - index 1
376 */ 330 */
377 #define CONFIG_CONS_INDEX 1 331 #define CONFIG_CONS_INDEX 1
378 #undef CONFIG_SERIAL_SOFTWARE_FIFO 332 #undef CONFIG_SERIAL_SOFTWARE_FIFO
379 #define CONFIG_SYS_NS16550 333 #define CONFIG_SYS_NS16550
380 #define CONFIG_SYS_NS16550_SERIAL 334 #define CONFIG_SYS_NS16550_SERIAL
381 #define CONFIG_SYS_NS16550_REG_SIZE 1 335 #define CONFIG_SYS_NS16550_REG_SIZE 1
382 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 336 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
383 337
384 #define CONFIG_SYS_BAUDRATE_TABLE \ 338 #define CONFIG_SYS_BAUDRATE_TABLE \
385 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
386 340
387 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
388 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
389 343
390 /* Use the HUSH parser */ 344 /* Use the HUSH parser */
391 #define CONFIG_SYS_HUSH_PARSER 345 #define CONFIG_SYS_HUSH_PARSER
392 #ifdef CONFIG_SYS_HUSH_PARSER 346 #ifdef CONFIG_SYS_HUSH_PARSER
393 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 347 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
394 #endif 348 #endif
395 349
396 /* 350 /*
397 * Pass open firmware flat tree 351 * Pass open firmware flat tree
398 */ 352 */
399 #define CONFIG_OF_LIBFDT 1 353 #define CONFIG_OF_LIBFDT 1
400 #define CONFIG_OF_BOARD_SETUP 1 354 #define CONFIG_OF_BOARD_SETUP 1
401 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 355 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
402 356
403 /* I2C */ 357 /* I2C */
404 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 358 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
405 #define CONFIG_HARD_I2C /* I2C with hardware support */ 359 #define CONFIG_HARD_I2C /* I2C with hardware support */
406 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 360 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
407 #define CONFIG_I2C_MULTI_BUS 361 #define CONFIG_I2C_MULTI_BUS
408 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 362 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
409 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 363 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
410 #define CONFIG_SYS_I2C_SLAVE 0x7F 364 #define CONFIG_SYS_I2C_SLAVE 0x7F
411 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 365 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
412 #define CONFIG_SYS_I2C_OFFSET 0x3000 366 #define CONFIG_SYS_I2C_OFFSET 0x3000
413 #define CONFIG_SYS_I2C2_OFFSET 0x3100 367 #define CONFIG_SYS_I2C2_OFFSET 0x3100
414 368
415 /* 369 /*
416 * I2C2 EEPROM 370 * I2C2 EEPROM
417 */ 371 */
418 #define CONFIG_ID_EEPROM 372 #define CONFIG_ID_EEPROM
419 #ifdef CONFIG_ID_EEPROM 373 #ifdef CONFIG_ID_EEPROM
420 #define CONFIG_SYS_I2C_EEPROM_NXID 374 #define CONFIG_SYS_I2C_EEPROM_NXID
421 #endif 375 #endif
422 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 376 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
423 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 377 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
424 #define CONFIG_SYS_EEPROM_BUS_NUM 0 378 #define CONFIG_SYS_EEPROM_BUS_NUM 0
425 379
426 /* 380 /*
427 * General PCI 381 * General PCI
428 * Memory space is mapped 1-1, but I/O space must start from 0. 382 * Memory space is mapped 1-1, but I/O space must start from 0.
429 */ 383 */
430 384
431 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 385 /* controller 3, Slot 1, tgtid 3, Base address b000 */
432 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 386 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
433 #ifdef CONFIG_PHYS_64BIT 387 #ifdef CONFIG_PHYS_64BIT
434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 388 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
435 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 389 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
436 #else 390 #else
437 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 391 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 392 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
439 #endif 393 #endif
440 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 394 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
441 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 395 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
442 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 396 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
443 #ifdef CONFIG_PHYS_64BIT 397 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 398 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
445 #else 399 #else
446 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 400 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
447 #endif 401 #endif
448 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 402 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
449 403
450 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 404 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
451 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 405 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
452 #ifdef CONFIG_PHYS_64BIT 406 #ifdef CONFIG_PHYS_64BIT
453 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 407 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
454 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 408 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
455 #else 409 #else
456 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 410 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
457 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 411 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
458 #endif 412 #endif
459 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 413 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
460 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
461 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 415 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
462 #ifdef CONFIG_PHYS_64BIT 416 #ifdef CONFIG_PHYS_64BIT
463 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
464 #else 418 #else
465 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
466 #endif 420 #endif
467 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 421 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
468 422
469 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 423 /* controller 1, Slot 2, tgtid 1, Base address a000 */
470 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 424 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
471 #ifdef CONFIG_PHYS_64BIT 425 #ifdef CONFIG_PHYS_64BIT
472 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
473 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 427 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
474 #else 428 #else
475 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 429 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
476 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 430 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
477 #endif 431 #endif
478 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
479 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 433 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
480 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 434 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
481 #ifdef CONFIG_PHYS_64BIT 435 #ifdef CONFIG_PHYS_64BIT
482 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 436 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
483 #else 437 #else
484 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 438 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
485 #endif 439 #endif
486 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 440 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
487 441
488 #if defined(CONFIG_PCI) 442 #if defined(CONFIG_PCI)
489 443
490 /*PCIE video card used*/ 444 /*PCIE video card used*/
491 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 445 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
492 446
493 /* video */ 447 /* video */
494 #define CONFIG_VIDEO 448 #define CONFIG_VIDEO
495 449
496 #if defined(CONFIG_VIDEO) 450 #if defined(CONFIG_VIDEO)
497 #define CONFIG_BIOSEMU 451 #define CONFIG_BIOSEMU
498 #define CONFIG_CFB_CONSOLE 452 #define CONFIG_CFB_CONSOLE
499 #define CONFIG_VIDEO_SW_CURSOR 453 #define CONFIG_VIDEO_SW_CURSOR
500 #define CONFIG_VGA_AS_SINGLE_DEVICE 454 #define CONFIG_VGA_AS_SINGLE_DEVICE
501 #define CONFIG_ATI_RADEON_FB 455 #define CONFIG_ATI_RADEON_FB
502 #define CONFIG_VIDEO_LOGO 456 #define CONFIG_VIDEO_LOGO
503 /*#define CONFIG_CONSOLE_CURSOR*/ 457 /*#define CONFIG_CONSOLE_CURSOR*/
504 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 458 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
505 #endif 459 #endif
506 460
507 #define CONFIG_NET_MULTI 461 #define CONFIG_NET_MULTI
508 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 462 #define CONFIG_PCI_PNP /* do pci plug-and-play */
509 463
510 #undef CONFIG_EEPRO100 464 #undef CONFIG_EEPRO100
511 #undef CONFIG_TULIP 465 #undef CONFIG_TULIP
512 #define CONFIG_RTL8139 466 #define CONFIG_RTL8139
513 467
514 #ifndef CONFIG_PCI_PNP 468 #ifndef CONFIG_PCI_PNP
515 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 469 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
516 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 470 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
517 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 471 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
518 #endif 472 #endif
519 473
520 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 474 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
521 #define CONFIG_DOS_PARTITION 475 #define CONFIG_DOS_PARTITION
522 #define CONFIG_SCSI_AHCI 476 #define CONFIG_SCSI_AHCI
523 477
524 #ifdef CONFIG_SCSI_AHCI 478 #ifdef CONFIG_SCSI_AHCI
525 #define CONFIG_SATA_ULI5288 479 #define CONFIG_SATA_ULI5288
526 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 480 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
527 #define CONFIG_SYS_SCSI_MAX_LUN 1 481 #define CONFIG_SYS_SCSI_MAX_LUN 1
528 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 482 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
529 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 483 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
530 #endif /* SCSI */ 484 #endif /* SCSI */
531 485
532 #endif /* CONFIG_PCI */ 486 #endif /* CONFIG_PCI */
533 487
534 488
535 #if defined(CONFIG_TSEC_ENET) 489 #if defined(CONFIG_TSEC_ENET)
536 490
537 #ifndef CONFIG_NET_MULTI 491 #ifndef CONFIG_NET_MULTI
538 #define CONFIG_NET_MULTI 1 492 #define CONFIG_NET_MULTI 1
539 #endif 493 #endif
540 494
541 #define CONFIG_MII 1 /* MII PHY management */ 495 #define CONFIG_MII 1 /* MII PHY management */
542 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 496 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
543 #define CONFIG_TSEC1 1 497 #define CONFIG_TSEC1 1
544 #define CONFIG_TSEC1_NAME "eTSEC1" 498 #define CONFIG_TSEC1_NAME "eTSEC1"
545 #define CONFIG_TSEC2 1 499 #define CONFIG_TSEC2 1
546 #define CONFIG_TSEC2_NAME "eTSEC2" 500 #define CONFIG_TSEC2_NAME "eTSEC2"
547 #define CONFIG_TSEC3 1 501 #define CONFIG_TSEC3 1
548 #define CONFIG_TSEC3_NAME "eTSEC3" 502 #define CONFIG_TSEC3_NAME "eTSEC3"
549 503
550 #define CONFIG_PIXIS_SGMII_CMD 504 #define CONFIG_PIXIS_SGMII_CMD
551 #define CONFIG_FSL_SGMII_RISER 1 505 #define CONFIG_FSL_SGMII_RISER 1
552 #define SGMII_RISER_PHY_OFFSET 0x1b 506 #define SGMII_RISER_PHY_OFFSET 0x1b
553 507
554 #ifdef CONFIG_FSL_SGMII_RISER 508 #ifdef CONFIG_FSL_SGMII_RISER
555 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 509 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
556 #endif 510 #endif
557 511
558 #define TSEC1_PHY_ADDR 0 512 #define TSEC1_PHY_ADDR 0
559 #define TSEC2_PHY_ADDR 1 513 #define TSEC2_PHY_ADDR 1
560 #define TSEC3_PHY_ADDR 2 514 #define TSEC3_PHY_ADDR 2
561 515
562 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 516 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
563 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 517 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
564 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 518 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
565 519
566 #define TSEC1_PHYIDX 0 520 #define TSEC1_PHYIDX 0
567 #define TSEC2_PHYIDX 0 521 #define TSEC2_PHYIDX 0
568 #define TSEC3_PHYIDX 0 522 #define TSEC3_PHYIDX 0
569 523
570 #define CONFIG_ETHPRIME "eTSEC1" 524 #define CONFIG_ETHPRIME "eTSEC1"
571 525
572 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 526 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
573 #endif /* CONFIG_TSEC_ENET */ 527 #endif /* CONFIG_TSEC_ENET */
574 528
575 /* 529 /*
576 * Environment 530 * Environment
577 */ 531 */
578 #define CONFIG_ENV_IS_IN_FLASH 1 532 #define CONFIG_ENV_IS_IN_FLASH 1
579 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 533 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
580 #define CONFIG_ENV_ADDR 0xfff80000 534 #define CONFIG_ENV_ADDR 0xfff80000
581 #else 535 #else
582 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 536 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
583 #endif 537 #endif
584 #define CONFIG_ENV_SIZE 0x2000 538 #define CONFIG_ENV_SIZE 0x2000
585 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 539 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
586 540
587 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 541 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
588 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 542 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
589 543
590 /* 544 /*
591 * Command line configuration. 545 * Command line configuration.
592 */ 546 */
593 #include <config_cmd_default.h> 547 #include <config_cmd_default.h>
594 548
595 #define CONFIG_CMD_IRQ 549 #define CONFIG_CMD_IRQ
596 #define CONFIG_CMD_PING 550 #define CONFIG_CMD_PING
597 #define CONFIG_CMD_I2C 551 #define CONFIG_CMD_I2C
598 #define CONFIG_CMD_MII 552 #define CONFIG_CMD_MII
599 #define CONFIG_CMD_ELF 553 #define CONFIG_CMD_ELF
600 #define CONFIG_CMD_IRQ 554 #define CONFIG_CMD_IRQ
601 #define CONFIG_CMD_SETEXPR 555 #define CONFIG_CMD_SETEXPR
602 556
603 #if defined(CONFIG_PCI) 557 #if defined(CONFIG_PCI)
604 #define CONFIG_CMD_PCI 558 #define CONFIG_CMD_PCI
605 #define CONFIG_CMD_NET 559 #define CONFIG_CMD_NET
606 #define CONFIG_CMD_SCSI 560 #define CONFIG_CMD_SCSI
607 #define CONFIG_CMD_EXT2 561 #define CONFIG_CMD_EXT2
608 #endif 562 #endif
609 563
610 /* 564 /*
611 * USB 565 * USB
612 */ 566 */
613 #define CONFIG_CMD_USB 567 #define CONFIG_CMD_USB
614 #define CONFIG_USB_STORAGE 568 #define CONFIG_USB_STORAGE
615 #define CONFIG_USB_EHCI 569 #define CONFIG_USB_EHCI
616 #define CONFIG_USB_EHCI_FSL 570 #define CONFIG_USB_EHCI_FSL
617 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 571 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
618 572
619 #undef CONFIG_WATCHDOG /* watchdog disabled */ 573 #undef CONFIG_WATCHDOG /* watchdog disabled */
620 574
621 /* 575 /*
622 * Miscellaneous configurable options 576 * Miscellaneous configurable options
623 */ 577 */
624 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 578 #define CONFIG_SYS_LONGHELP /* undef to save memory */
625 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 579 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
626 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 580 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
627 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 581 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
628 #if defined(CONFIG_CMD_KGDB) 582 #if defined(CONFIG_CMD_KGDB)
629 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 583 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
630 #else 584 #else
631 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 585 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
632 #endif 586 #endif
633 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 587 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
634 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 588 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
635 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 589 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
636 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 590 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
637 591
638 /* 592 /*
639 * For booting Linux, the board info and command line data 593 * For booting Linux, the board info and command line data
640 * have to be in the first 16 MB of memory, since this is 594 * have to be in the first 16 MB of memory, since this is
641 * the maximum mapped by the Linux kernel during initialization. 595 * the maximum mapped by the Linux kernel during initialization.
642 */ 596 */
643 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 597 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
644 598
645 /* 599 /*
646 * Internal Definitions 600 * Internal Definitions
647 * 601 *
648 * Boot Flags 602 * Boot Flags
649 */ 603 */
650 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 604 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
651 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 605 #define BOOTFLAG_WARM 0x02 /* Software reboot */
652 606
653 #if defined(CONFIG_CMD_KGDB) 607 #if defined(CONFIG_CMD_KGDB)
654 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 608 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
655 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 609 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
656 #endif 610 #endif
657 611
658 /* 612 /*
659 * Environment Configuration 613 * Environment Configuration
660 */ 614 */
661 615
662 /* The mac addresses for all ethernet interface */ 616 /* The mac addresses for all ethernet interface */
663 #if defined(CONFIG_TSEC_ENET) 617 #if defined(CONFIG_TSEC_ENET)
664 #define CONFIG_HAS_ETH0 618 #define CONFIG_HAS_ETH0
665 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 619 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
666 #define CONFIG_HAS_ETH1 620 #define CONFIG_HAS_ETH1
667 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 621 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
668 #define CONFIG_HAS_ETH2 622 #define CONFIG_HAS_ETH2
669 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 623 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
670 #define CONFIG_HAS_ETH3 624 #define CONFIG_HAS_ETH3
671 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 625 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
672 #endif 626 #endif
673 627
674 #define CONFIG_IPADDR 192.168.1.254 628 #define CONFIG_IPADDR 192.168.1.254
675 629
676 #define CONFIG_HOSTNAME unknown 630 #define CONFIG_HOSTNAME unknown
677 #define CONFIG_ROOTPATH /opt/nfsroot 631 #define CONFIG_ROOTPATH /opt/nfsroot
678 #define CONFIG_BOOTFILE uImage 632 #define CONFIG_BOOTFILE uImage
679 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 633 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
680 634
681 #define CONFIG_SERVERIP 192.168.1.1 635 #define CONFIG_SERVERIP 192.168.1.1
682 #define CONFIG_GATEWAYIP 192.168.1.1 636 #define CONFIG_GATEWAYIP 192.168.1.1
683 #define CONFIG_NETMASK 255.255.255.0 637 #define CONFIG_NETMASK 255.255.255.0
684 638
685 /* default location for tftp and bootm */ 639 /* default location for tftp and bootm */
686 #define CONFIG_LOADADDR 1000000 640 #define CONFIG_LOADADDR 1000000
687 641
688 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 642 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
689 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 643 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
690 644
691 #define CONFIG_BAUDRATE 115200 645 #define CONFIG_BAUDRATE 115200
692 646
693 #define CONFIG_EXTRA_ENV_SETTINGS \ 647 #define CONFIG_EXTRA_ENV_SETTINGS \
694 "perf_mode=stable\0" \ 648 "perf_mode=stable\0" \
695 "memctl_intlv_ctl=2\0" \ 649 "memctl_intlv_ctl=2\0" \
696 "netdev=eth0\0" \ 650 "netdev=eth0\0" \
697 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 651 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
698 "tftpflash=tftpboot $loadaddr $uboot; " \ 652 "tftpflash=tftpboot $loadaddr $uboot; " \
699 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 653 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
700 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 654 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
701 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 655 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
702 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 656 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
703 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 657 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
704 "consoledev=ttyS0\0" \ 658 "consoledev=ttyS0\0" \
705 "ramdiskaddr=2000000\0" \ 659 "ramdiskaddr=2000000\0" \
706 "ramdiskfile=p2020ds/ramdisk.uboot\0" \ 660 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
707 "fdtaddr=c00000\0" \ 661 "fdtaddr=c00000\0" \
708 "fdtfile=p2020ds/p2020ds.dtb\0" \ 662 "fdtfile=p2020ds/p2020ds.dtb\0" \
709 "bdev=sda3\0" 663 "bdev=sda3\0"
710 664
711 #define CONFIG_HDBOOT \ 665 #define CONFIG_HDBOOT \
712 "setenv bootargs root=/dev/$bdev rw " \ 666 "setenv bootargs root=/dev/$bdev rw " \
713 "console=$consoledev,$baudrate $othbootargs;" \ 667 "console=$consoledev,$baudrate $othbootargs;" \
714 "tftp $loadaddr $bootfile;" \ 668 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \ 669 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr - $fdtaddr" 670 "bootm $loadaddr - $fdtaddr"
717 671
718 #define CONFIG_NFSBOOTCOMMAND \ 672 #define CONFIG_NFSBOOTCOMMAND \
719 "setenv bootargs root=/dev/nfs rw " \ 673 "setenv bootargs root=/dev/nfs rw " \
720 "nfsroot=$serverip:$rootpath " \ 674 "nfsroot=$serverip:$rootpath " \
721 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
722 "console=$consoledev,$baudrate $othbootargs;" \ 676 "console=$consoledev,$baudrate $othbootargs;" \
723 "tftp $loadaddr $bootfile;" \ 677 "tftp $loadaddr $bootfile;" \
724 "tftp $fdtaddr $fdtfile;" \ 678 "tftp $fdtaddr $fdtfile;" \
725 "bootm $loadaddr - $fdtaddr" 679 "bootm $loadaddr - $fdtaddr"
726 680
727 #define CONFIG_RAMBOOTCOMMAND \ 681 #define CONFIG_RAMBOOTCOMMAND \
728 "setenv bootargs root=/dev/ram rw " \ 682 "setenv bootargs root=/dev/ram rw " \
729 "console=$consoledev,$baudrate $othbootargs;" \ 683 "console=$consoledev,$baudrate $othbootargs;" \
730 "tftp $ramdiskaddr $ramdiskfile;" \ 684 "tftp $ramdiskaddr $ramdiskfile;" \
731 "tftp $loadaddr $bootfile;" \ 685 "tftp $loadaddr $bootfile;" \
732 "tftp $fdtaddr $fdtfile;" \ 686 "tftp $fdtaddr $fdtfile;" \
733 "bootm $loadaddr $ramdiskaddr $fdtaddr" 687 "bootm $loadaddr $ramdiskaddr $fdtaddr"
734 688
735 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 689 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
736 690