p2020ds: add alternate boot bank support using the ngPIXIS FPGA

The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. The ngPIXIS has one distinct new feature: the values of the on-board switches can be selectively overridden with shadow registers. This feature is used to boot from a different NOR flash bank, instead of having a register dedicated for this purpose. Because the ngPIXIS is so different from the previous PIXIS, a new file is introduced: ngpixis.c. Also update the P2020DS checkboard() function to use the new macros defined in the header file. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

p2020ds: add alternate boot bank support using the ngPIXIS FPGA
The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. The ngPIXIS has one distinct new feature: the values of the on-board switches can be selectively overridden with shadow registers. This feature is used to boot from a different NOR flash bank, instead of having a register dedicated for this purpose. Because the ngPIXIS is so different from the previous PIXIS, a new file is introduced: ngpixis.c. Also update the P2020DS checkboard() function to use the new macros defined in the header file. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi · Kumar Gala
1 parent 2feb4af001
Showing 5 changed files with 222 additions and 89 deletions Side-by-side Diff
board/freescale/common/Makefile
board/freescale/common/ngpixis.c
board/freescale/common/ngpixis.h
board/freescale/p2020ds/p2020ds.c
include/configs/P2020DS.h
@@ -33,6 +33,7 @@
 COBJS-${CONFIG_FSL_VIA}		+= cds_via.o
 COBJS-${CONFIG_FSL_DIU_FB}	+= fsl_diu_fb.o fsl_logo_bmp.o
 COBJS-${CONFIG_FSL_PIXIS}	+= pixis.o
+COBJS-${CONFIG_FSL_NGPIXIS}	+= ngpixis.o
 COBJS-${CONFIG_PQ_MDS_PIB}	+= pq-mds-pib.o
 COBJS-${CONFIG_ID_EEPROM}	+= sys_eeprom.o
 COBJS-${CONFIG_FSL_SGMII_RISER}	+= sgmii_riser.o
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard.  It contains
+ * eight "bits".  The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches.  There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ *    is used in the PIXIS_SW() macro to determine which offset in
+ *    the PIXIS register map corresponds to the physical switch that controls
+ *    the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ *    boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+
+#include "ngpixis.h"
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void pixis_reset(void)
+{
+	out_8(&pixis->rst, 0);
+
+	while (1);
+}
+
+/*
+ * Reset the board.  Like pixis_reset(), but it honors the ENx registers.
+ */
+void pixis_bank_reset(void)
+{
+	out_8(&pixis->vctl, 0);
+	out_8(&pixis->vctl, 1);
+
+	while (1);
+}
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void clear_altbank(void)
+{
+	/* Tell the ngPIXIS to use this the bits in the physical switch for the
+	 * boot bank value, instead of the SWx register.  We need to be careful
+	 * only to set the bits in SWx that correspond to the boot bank.
+	 */
+	clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void set_altbank(void)
+{
+	/* Program the alternate bank number into the SWx register.
+	 */
+	clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
+		     PIXIS_LBMAP_ALTBANK);
+
+	/* Tell the ngPIXIS to use this the bits in the SWx register for the
+	 * boot bank value, instead of the physical switch.  We need to be
+	 * careful only to set the bits in SWx that correspond to the boot bank.
+	 */
+	setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+
+int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int i;
+	char *p_altbank = NULL;
+	char *unknown_param = NULL;
+
+	/* No args is a simple reset request.
+	 */
+	if (argc <= 1)
+		pixis_reset();
+
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "altbank") == 0) {
+			p_altbank = argv[i];
+			continue;
+		}
+
+		unknown_param = argv[i];
+	}
+
+	if (unknown_param) {
+		printf("Invalid option: %s\n", unknown_param);
+		return 1;
+	}
+
+	if (p_altbank)
+		set_altbank();
+	else
+		clear_altbank();
+
+	pixis_bank_reset();
+
+	/* Shouldn't be reached. */
+	return 0;
+}
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer",
+	"- hard reset to default bank\n"
+	"pixis_reset altbank - reset to alternate bank\n"
+	);
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/* ngPIXIS register set. Hopefully, this won't change too much over time.
+ * Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct ngpixis {
+	u8 id;
+	u8 arch;
+	u8 scver;
+	u8 csr;
+	u8 rst;
+	u8 res1;
+	u8 aux;
+	u8 spd;
+	u8 brdcfg0;
+	u8 dma;
+	u8 addr;
+	u8 res2[2];
+	u8 data;
+	u8 led;
+	u8 res3;
+	u8 vctl;
+	u8 vstat;
+	u8 vcfgen0;
+	u8 res4;
+	u8 ocmcsr;
+	u8 ocmmsg;
+	u8 gmdbg;
+	u8 res5[2];
+	u8 sclk[3];
+	u8 dclk[3];
+	u8 watch;
+	struct {
+		u8 sw;
+		u8 en;
+	} s[8];
+} ngpixis_t  __attribute__ ((aligned(1)));
+
+/* Pointer to the PIXIS register set */
+#define pixis ((ngpixis_t *)PIXIS_BASE)
+
+/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_SW(x)		(pixis->s[(x) - 1].sw)
+
+/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_EN(x)		(pixis->s[(x) - 1].en)
@@ -38,6 +38,7 @@
 #include <asm/mp.h>
 #include <netdev.h>
  
+#include "../common/ngpixis.h"
 #include "../common/sgmii_riser.h"
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
  
@@ -46,31 +47,25 @@
  
 int checkboard(void)
 {
-	u8 sw7;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
+	u8 sw;
  
 	puts("Board: P2020DS ");
 #ifdef CONFIG_PHYS_64BIT
 	puts("(36-bit addrmap) ");
 #endif
  
-	printf("Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  
-	sw7 = in_8(pixis_base + PIXIS_SW(7));
-	switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
-		case 0:
-		case 1:
-			printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
-			break;
-		case 2:
-		case 3:
-			puts ("Promjet\n");
-			break;
-	}
+	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+	sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  
+	if (sw < 0x8)
+		/* The lower two bits are the actual vbank number */
+		printf("vBank: %d\n", sw & 3);
+	else
+		puts("Promjet\n");
+
 	return 0;
 }
  
  
  
  
  
  
@@ -370,30 +365,22 @@
 	return gd->mem_clk;
 }
  
-unsigned long
-calculate_board_sys_clk(ulong dummy)
+unsigned long calculate_board_sys_clk(ulong dummy)
 {
 	ulong val;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
  
-	val = ics307_clk_freq(
-	    in_8(pixis_base + PIXIS_VSYSCLK0),
-	    in_8(pixis_base + PIXIS_VSYSCLK1),
-	    in_8(pixis_base + PIXIS_VSYSCLK2));
+	val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
+			      in_8(&pixis->sclk[2]));
 	debug("sysclk val = %lu\n", val);
 	return val;
 }
  
-unsigned long
-calculate_board_ddr_clk(ulong dummy)
+unsigned long calculate_board_ddr_clk(ulong dummy)
 {
 	ulong val;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
  
-	val = ics307_clk_freq(
-	    in_8(pixis_base + PIXIS_VDDRCLK0),
-	    in_8(pixis_base + PIXIS_VDDRCLK1),
-	    in_8(pixis_base + PIXIS_VDDRCLK2));
+	val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
+			      in_8(&pixis->dclk[2]));
 	debug("ddrclk val = %lu\n", val);
 	return val;
 }
  
@@ -402,9 +389,8 @@
 {
 	u8 i;
 	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
  
-	i = in_8(pixis_base + PIXIS_SPD);
+	i = in_8(&pixis->spd);
 	i &= 0x07;
  
 	switch (i) {
  
@@ -441,9 +427,8 @@
 {
 	u8 i;
 	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
  
-	i = in_8(pixis_base + PIXIS_SPD);
+	i = in_8(&pixis->spd);
 	i &= 0x38;
 	i >>= 3;
  
@@ -238,7 +238,9 @@
  
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
  
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#ifdef CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS	0xfffdf0000ull
@@ -249,59 +251,11 @@
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
  
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR		0x3	/* PIXIS General control/status register */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_PWR		0x5	/* PIXIS Power status register */
-#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VSTAT		0x11	/* VELA Status Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VCORE0		0x14	/* VELA VCORE0 Register */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0		0x19	/* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1		0x1A	/* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2		0x1B	/* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0		0x1C	/* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1		0x1D	/* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2		0x1E	/* VELA DDRCLK2 Register */
-
-#define PIXIS_VWATCH		0x24	/* Watchdog Register */
-#define PIXIS_LED		0x25	/* LED Register */
-
-#define PIXIS_SW(x)		0x20 + (x - 1) * 2
-#define PIXIS_EN(x)		0x21 + (x - 1) * 2
-#define PIXIS_SW7_LBMAP		0xc0	/* SW7 - cfg_lbmap */
-#define PIXIS_SW7_VBANK		0x30	/* SW7 - cfg_vbank */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
-#define PIXIS_VSPEED2_TSEC1SER	0x8
-#define PIXIS_VSPEED2_TSEC2SER	0x4
-#define PIXIS_VSPEED2_TSEC3SER	0x2
-#define PIXIS_VSPEED2_TSEC4SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC2SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x20
-#define PIXIS_VCFGEN1_TSEC4SER	0x20
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
-					| PIXIS_VSPEED2_TSEC2SER \
-					| PIXIS_VSPEED2_TSEC3SER \
-					| PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
-					| PIXIS_VCFGEN1_TSEC2SER \
-					| PIXIS_VCFGEN1_TSEC3SER \
-					| PIXIS_VCFGEN1_TSEC4SER)
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x20
+#endif
  
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
...	...	@@ -33,6 +33,7 @@
33	33	COBJS-${CONFIG_FSL_VIA} += cds_via.o
34	34	COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
35	35	COBJS-${CONFIG_FSL_PIXIS} += pixis.o
	36	+COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
36	37	COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
37	38	COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
38	39	COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
	1	+/**
	2	+ * Copyright 2010 Freescale Semiconductor
	3	+ * Author: Timur Tabi <timur@freescale.com>
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or modify it
	6	+ * under the terms of the GNU General Public License as published by the Free
	7	+ * Software Foundation; either version 2 of the License, or (at your option)
	8	+ * any later version.
	9	+ *
	10	+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
	11	+ * some Freescale reference boards.
	12	+ *
	13	+ * A "switch" is black rectangular block on the motherboard. It contains
	14	+ * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
	15	+ * shadow the actual physical switches. There is also another set of
	16	+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
	17	+ * used to override the values of the bits in the physical switches.
	18	+ *
	19	+ * The following macros need to be defined:
	20	+ *
	21	+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
	22	+ *
	23	+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
	24	+ * is used in the PIXIS_SW() macro to determine which offset in
	25	+ * the PIXIS register map corresponds to the physical switch that controls
	26	+ * the boot bank.
	27	+ *
	28	+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
	29	+ *
	30	+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
	31	+ *
	32	+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
	33	+ * boot from the alternate bank.
	34	+ */
	35	+
	36	+#include <common.h>
	37	+#include <command.h>
	38	+#include <watchdog.h>
	39	+#include <asm/cache.h>
	40	+#include <asm/io.h>
	41	+
	42	+#include "ngpixis.h"
	43	+
	44	+/*
	45	+ * Reset the board. This ignores the ENx registers.
	46	+ */
	47	+void pixis_reset(void)
	48	+{
	49	+ out_8(&pixis->rst, 0);
	50	+
	51	+ while (1);
	52	+}
	53	+
	54	+/*
	55	+ * Reset the board. Like pixis_reset(), but it honors the ENx registers.
	56	+ */
	57	+void pixis_bank_reset(void)
	58	+{
	59	+ out_8(&pixis->vctl, 0);
	60	+ out_8(&pixis->vctl, 1);
	61	+
	62	+ while (1);
	63	+}
	64	+
	65	+/**
	66	+ * Set the boot bank to the power-on default bank
	67	+ */
	68	+void clear_altbank(void)
	69	+{
	70	+ /* Tell the ngPIXIS to use this the bits in the physical switch for the
	71	+ * boot bank value, instead of the SWx register. We need to be careful
	72	+ * only to set the bits in SWx that correspond to the boot bank.
	73	+ */
	74	+ clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
	75	+}
	76	+
	77	+/**
	78	+ * Set the boot bank to the alternate bank
	79	+ */
	80	+void set_altbank(void)
	81	+{
	82	+ /* Program the alternate bank number into the SWx register.
	83	+ */
	84	+ clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
	85	+ PIXIS_LBMAP_ALTBANK);
	86	+
	87	+ /* Tell the ngPIXIS to use this the bits in the SWx register for the
	88	+ * boot bank value, instead of the physical switch. We need to be
	89	+ * careful only to set the bits in SWx that correspond to the boot bank.
	90	+ */
	91	+ setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
	92	+}
	93	+
	94	+
	95	+int pixis_reset_cmd(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	96	+{
	97	+ unsigned int i;
	98	+ char *p_altbank = NULL;
	99	+ char *unknown_param = NULL;
	100	+
	101	+ /* No args is a simple reset request.
	102	+ */
	103	+ if (argc <= 1)
	104	+ pixis_reset();
	105	+
	106	+ for (i = 1; i < argc; i++) {
	107	+ if (strcmp(argv[i], "altbank") == 0) {
	108	+ p_altbank = argv[i];
	109	+ continue;
	110	+ }
	111	+
	112	+ unknown_param = argv[i];
	113	+ }
	114	+
	115	+ if (unknown_param) {
	116	+ printf("Invalid option: %s\n", unknown_param);
	117	+ return 1;
	118	+ }
	119	+
	120	+ if (p_altbank)
	121	+ set_altbank();
	122	+ else
	123	+ clear_altbank();
	124	+
	125	+ pixis_bank_reset();
	126	+
	127	+ /* Shouldn't be reached. */
	128	+ return 0;
	129	+}
	130	+
	131	+U_BOOT_CMD(
	132	+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
	133	+ "Reset the board using the FPGA sequencer",
	134	+ "- hard reset to default bank\n"
	135	+ "pixis_reset altbank - reset to alternate bank\n"
	136	+ );
...	...	@@ -38,6 +38,7 @@
38	38	#include <asm/mp.h>
39	39	#include <netdev.h>
40	40
	41	+#include "../common/ngpixis.h"
41	42	#include "../common/sgmii_riser.h"
42	43
43	44	DECLARE_GLOBAL_DATA_PTR;
44	45
45	46
46	47
...	...	@@ -46,31 +47,25 @@
46	47
47	48	int checkboard(void)
48	49	{
49		- u8 sw7;
50		- u8 pixis_base = (u8 )PIXIS_BASE;
	50	+ u8 sw;
51	51
52	52	puts("Board: P2020DS ");
53	53	#ifdef CONFIG_PHYS_64BIT
54	54	puts("(36-bit addrmap) ");
55	55	#endif
56	56
57		- printf("Sys ID: 0x%02x, "
58		- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
59		- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
60		- in_8(pixis_base + PIXIS_PVER));
	57	+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	58	+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
61	59
62		- sw7 = in_8(pixis_base + PIXIS_SW(7));
63		- switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
64		- case 0:
65		- case 1:
66		- printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
67		- break;
68		- case 2:
69		- case 3:
70		- puts ("Promjet\n");
71		- break;
72		- }
	60	+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
	61	+ sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
73	62
	63	+ if (sw < 0x8)
	64	+ /* The lower two bits are the actual vbank number */
	65	+ printf("vBank: %d\n", sw & 3);
	66	+ else
	67	+ puts("Promjet\n");
	68	+
74	69	return 0;
75	70	}
76	71
77	72
78	73
79	74
80	75
81	76
...	...	@@ -370,30 +365,22 @@
370	365	return gd->mem_clk;
371	366	}
372	367
373		-unsigned long
374		-calculate_board_sys_clk(ulong dummy)
	368	+unsigned long calculate_board_sys_clk(ulong dummy)
375	369	{
376	370	ulong val;
377		- u8 pixis_base = (u8 )PIXIS_BASE;
378	371
379		- val = ics307_clk_freq(
380		- in_8(pixis_base + PIXIS_VSYSCLK0),
381		- in_8(pixis_base + PIXIS_VSYSCLK1),
382		- in_8(pixis_base + PIXIS_VSYSCLK2));
	372	+ val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
	373	+ in_8(&pixis->sclk[2]));
383	374	debug("sysclk val = %lu\n", val);
384	375	return val;
385	376	}
386	377
387		-unsigned long
388		-calculate_board_ddr_clk(ulong dummy)
	378	+unsigned long calculate_board_ddr_clk(ulong dummy)
389	379	{
390	380	ulong val;
391		- u8 pixis_base = (u8 )PIXIS_BASE;
392	381
393		- val = ics307_clk_freq(
394		- in_8(pixis_base + PIXIS_VDDRCLK0),
395		- in_8(pixis_base + PIXIS_VDDRCLK1),
396		- in_8(pixis_base + PIXIS_VDDRCLK2));
	382	+ val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
	383	+ in_8(&pixis->dclk[2]));
397	384	debug("ddrclk val = %lu\n", val);
398	385	return val;
399	386	}
400	387
...	...	@@ -402,9 +389,8 @@
402	389	{
403	390	u8 i;
404	391	ulong val = 0;
405		- u8 pixis_base = (u8 )PIXIS_BASE;
406	392
407		- i = in_8(pixis_base + PIXIS_SPD);
	393	+ i = in_8(&pixis->spd);
408	394	i &= 0x07;
409	395
410	396	switch (i) {
411	397
...	...	@@ -441,9 +427,8 @@
441	427	{
442	428	u8 i;
443	429	ulong val = 0;
444		- u8 pixis_base = (u8 )PIXIS_BASE;
445	430
446		- i = in_8(pixis_base + PIXIS_SPD);
	431	+ i = in_8(&pixis->spd);
447	432	i &= 0x38;
448	433	i >>= 3;
449	434
...	...	@@ -238,7 +238,9 @@
238	238
239	239	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
240	240
241		-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
	241	+#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
	242	+
	243	+#ifdef CONFIG_FSL_NGPIXIS
242	244	#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
243	245	#ifdef CONFIG_PHYS_64BIT
244	246	#define PIXIS_BASE_PHYS 0xfffdf0000ull
...	...	@@ -249,59 +251,11 @@
249	251	#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \| BR_PS_8 \| BR_V)
250	252	#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
251	253
252		-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
253		-#define PIXIS_VER 0x1 /* Board version at offset 1 */
254		-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
255		-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
256		-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
257		-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
258		-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
259		-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
260		-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
261		-#define PIXIS_VCTL 0x10 /* VELA Control Register */
262		-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
263		-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
264		-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
265		-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
266		-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
267		-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
268		-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
269		-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
270		-#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
271		-#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
272		-#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
273		-#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
274		-#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
275		-#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
276		-
277		-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
278		-#define PIXIS_LED 0x25 /* LED Register */
279		-
280		-#define PIXIS_SW(x) 0x20 + (x - 1) * 2
281		-#define PIXIS_EN(x) 0x21 + (x - 1) * 2
282		-#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
283		-#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
284		-
285		-/* old pixis referenced names */
286		-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
287		-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
288		-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
289		-#define PIXIS_VSPEED2_TSEC1SER 0x8
290		-#define PIXIS_VSPEED2_TSEC2SER 0x4
291		-#define PIXIS_VSPEED2_TSEC3SER 0x2
292		-#define PIXIS_VSPEED2_TSEC4SER 0x1
293		-#define PIXIS_VCFGEN1_TSEC1SER 0x20
294		-#define PIXIS_VCFGEN1_TSEC2SER 0x20
295		-#define PIXIS_VCFGEN1_TSEC3SER 0x20
296		-#define PIXIS_VCFGEN1_TSEC4SER 0x20
297		-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
298		- \| PIXIS_VSPEED2_TSEC2SER \
299		- \| PIXIS_VSPEED2_TSEC3SER \
300		- \| PIXIS_VSPEED2_TSEC4SER)
301		-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
302		- \| PIXIS_VCFGEN1_TSEC2SER \
303		- \| PIXIS_VCFGEN1_TSEC3SER \
304		- \| PIXIS_VCFGEN1_TSEC4SER)
	254	+#define PIXIS_LBMAP_SWITCH 7
	255	+#define PIXIS_LBMAP_MASK 0xf0
	256	+#define PIXIS_LBMAP_SHIFT 4
	257	+#define PIXIS_LBMAP_ALTBANK 0x20
	258	+#endif
305	259
306	260	#define CONFIG_SYS_INIT_RAM_LOCK 1
307	261	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */