Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 5a9120439416a9101dec7c7dc65bb75a5ff09c4e

Authored by Albert ARIBAUD
2 parents 572886af59 4d6c96711b
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Showing 15 changed files Side-by-side Diff

... ... @@ -284,6 +284,7 @@
284 284 LIBS-y += drivers/pcmcia/libpcmcia.o
285 285 LIBS-y += drivers/power/libpower.o \
286 286 drivers/power/fuel_gauge/libfuel_gauge.o \
  287 + drivers/power/mfd/libmfd.o \
287 288 drivers/power/pmic/libpmic.o \
288 289 drivers/power/battery/libbattery.o
289 290 LIBS-y += drivers/spi/libspi.o
board/samsung/common/multi_i2c.c
Diff comments   View file @ 5a91204
... ... @@ -8,6 +8,14 @@
8 8 #include <common.h>
9 9 #include <i2c.h>
10 10  
  11 +#ifndef CONFIG_SOFT_I2C_I2C10_SCL
  12 +#define CONFIG_SOFT_I2C_I2C10_SCL 0
  13 +#endif
  14 +
  15 +#ifndef CONFIG_SOFT_I2C_I2C10_SDA
  16 +#define CONFIG_SOFT_I2C_I2C10_SDA 0
  17 +#endif
  18 +
11 19 /* Handle multiple I2C buses instances */
12 20 int get_multi_scl_pin(void)
13 21 {
... ... @@ -18,6 +26,8 @@
18 26 return CONFIG_SOFT_I2C_I2C5_SCL;
19 27 case I2C_1:
20 28 return CONFIG_SOFT_I2C_I2C9_SCL;
  29 + case I2C_2:
  30 + return CONFIG_SOFT_I2C_I2C10_SCL;
21 31 default:
22 32 printf("I2C_%d not supported!\n", bus);
23 33 };
... ... @@ -34,6 +44,8 @@
34 44 return CONFIG_SOFT_I2C_I2C5_SDA;
35 45 case I2C_1:
36 46 return CONFIG_SOFT_I2C_I2C9_SDA;
  47 + case I2C_2:
  48 + return CONFIG_SOFT_I2C_I2C10_SDA;
37 49 default:
38 50 printf("I2C_%d not supported!\n", bus);
39 51 };
board/samsung/trats2/Makefile
Diff comments   View file @ 5a91204
  1 +#
  2 +# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights reserved.
  3 +# Sanghee Kim <sh0130.kim@samsung.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +include $(TOPDIR)/config.mk
  9 +
  10 +LIB = $(obj)lib$(BOARD).o
  11 +
  12 +COBJS-y := trats2.o
  13 +
  14 +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
  15 +OBJS := $(addprefix $(obj),$(COBJS-y))
  16 +
  17 +
  18 +$(LIB): $(obj).depend $(OBJS)
  19 + $(call cmd_link_o_target, $(OBJS))
  20 +
  21 +clean:
  22 + rm -f $(OBJS)
  23 +
  24 +distclean: clean
  25 + rm -f $(LIB) core *.bak $(obj).depend
  26 +
  27 +#########################################################################
  28 +
  29 +# defines $(obj).depend target
  30 +include $(SRCTREE)/rules.mk
  31 +
  32 +sinclude $(obj).depend
  33 +
  34 +#########################################################################
board/samsung/trats2/trats2.c
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
  3 + * Sanghee Kim <sh0130.kim@samsung.com>
  4 + * Piotr Wilczek <p.wilczek@samsung.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <lcd.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/gpio.h>
  13 +#include <asm/arch/mmc.h>
  14 +#include <asm/arch/power.h>
  15 +#include <asm/arch/clk.h>
  16 +#include <asm/arch/clock.h>
  17 +#include <asm/arch/mipi_dsim.h>
  18 +#include <asm/arch/pinmux.h>
  19 +#include <asm/arch/power.h>
  20 +#include <power/pmic.h>
  21 +#include <power/max77686_pmic.h>
  22 +#include <power/battery.h>
  23 +#include <power/max77693_pmic.h>
  24 +#include <power/max77693_muic.h>
  25 +#include <power/max77693_fg.h>
  26 +#include <libtizen.h>
  27 +#include <errno.h>
  28 +
  29 +DECLARE_GLOBAL_DATA_PTR;
  30 +
  31 +static struct exynos4x12_gpio_part1 *gpio1;
  32 +static struct exynos4x12_gpio_part2 *gpio2;
  33 +
  34 +static unsigned int board_rev = -1;
  35 +
  36 +static inline u32 get_model_rev(void);
  37 +
  38 +static void check_hw_revision(void)
  39 +{
  40 + int modelrev = 0;
  41 + int i;
  42 +
  43 + gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  44 +
  45 + /*
  46 + * GPM1[1:0]: MODEL_REV[1:0]
  47 + * Don't set as pull-none for these N/C pin.
  48 + * TRM say that it may cause unexcepted state and leakage current.
  49 + * and pull-none is only for output function.
  50 + */
  51 + for (i = 0; i < 2; i++)
  52 + s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
  53 +
  54 + /* GPM1[5:2]: HW_REV[3:0] */
  55 + for (i = 2; i < 6; i++) {
  56 + s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
  57 + s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE);
  58 + }
  59 +
  60 + /* GPM1[1:0]: MODEL_REV[1:0] */
  61 + for (i = 0; i < 2; i++)
  62 + modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i);
  63 +
  64 + /* board_rev[15:8] = model */
  65 + board_rev = modelrev << 8;
  66 +}
  67 +
  68 +#ifdef CONFIG_DISPLAY_BOARDINFO
  69 +int checkboard(void)
  70 +{
  71 + puts("Board:\tTRATS2\n");
  72 + return 0;
  73 +}
  74 +#endif
  75 +
  76 +static void show_hw_revision(void)
  77 +{
  78 + printf("HW Revision:\t0x%04x\n", board_rev);
  79 +}
  80 +
  81 +u32 get_board_rev(void)
  82 +{
  83 + return board_rev;
  84 +}
  85 +
  86 +static inline u32 get_model_rev(void)
  87 +{
  88 + return (board_rev >> 8) & 0xff;
  89 +}
  90 +
  91 +static void board_external_gpio_init(void)
  92 +{
  93 + gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  94 +
  95 + /*
  96 + * some pins which in alive block are connected with external pull-up
  97 + * but it's default setting is pull-down.
  98 + * if that pin set as input then that floated
  99 + */
  100 +
  101 + s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */
  102 + s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */
  103 + s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
  104 + s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
  105 + s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */
  106 + s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */
  107 + s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */
  108 + s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */
  109 + s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */
  110 + s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */
  111 + s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */
  112 + s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */
  113 +}
  114 +
  115 +#ifdef CONFIG_SYS_I2C_INIT_BOARD
  116 +static void board_init_i2c(void)
  117 +{
  118 + gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
  119 + gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  120 +
  121 + /* I2C_7 */
  122 + s5p_gpio_direction_output(&gpio1->d0, 2, 1);
  123 + s5p_gpio_direction_output(&gpio1->d0, 3, 1);
  124 +
  125 + /* I2C_8 */
  126 + s5p_gpio_direction_output(&gpio1->f1, 4, 1);
  127 + s5p_gpio_direction_output(&gpio1->f1, 5, 1);
  128 +
  129 + /* I2C_9 */
  130 + s5p_gpio_direction_output(&gpio2->m2, 1, 1);
  131 + s5p_gpio_direction_output(&gpio2->m2, 0, 1);
  132 +}
  133 +#endif
  134 +
  135 +int board_early_init_f(void)
  136 +{
  137 + check_hw_revision();
  138 + board_external_gpio_init();
  139 +
  140 + gd->flags |= GD_FLG_DISABLE_CONSOLE;
  141 +
  142 + return 0;
  143 +}
  144 +
  145 +static int pmic_init_max77686(void);
  146 +
  147 +int board_init(void)
  148 +{
  149 + struct exynos4_power *pwr =
  150 + (struct exynos4_power *)EXYNOS4X12_POWER_BASE;
  151 +
  152 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  153 +
  154 + /* workaround: clear INFORM4..5 */
  155 + writel(0, (unsigned int)&pwr->inform4);
  156 + writel(0, (unsigned int)&pwr->inform5);
  157 +
  158 + return 0;
  159 +}
  160 +
  161 +int power_init_board(void)
  162 +{
  163 + int chrg;
  164 + struct power_battery *pb;
  165 + struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
  166 +
  167 +#ifdef CONFIG_SYS_I2C_INIT_BOARD
  168 + board_init_i2c();
  169 +#endif
  170 + pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */
  171 + pmic_init_max77686();
  172 + pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
  173 + power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
  174 + power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */
  175 + power_bat_init(0);
  176 +
  177 + p_chrg = pmic_get("MAX77693_PMIC");
  178 + if (!p_chrg) {
  179 + puts("MAX77693_PMIC: Not found\n");
  180 + return -ENODEV;
  181 + }
  182 +
  183 + p_muic = pmic_get("MAX77693_MUIC");
  184 + if (!p_muic) {
  185 + puts("MAX77693_MUIC: Not found\n");
  186 + return -ENODEV;
  187 + }
  188 +
  189 + p_fg = pmic_get("MAX77693_FG");
  190 + if (!p_fg) {
  191 + puts("MAX17042_FG: Not found\n");
  192 + return -ENODEV;
  193 + }
  194 +
  195 + if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0)
  196 + puts("No battery detected\n");
  197 +
  198 + p_bat = pmic_get("BAT_TRATS2");
  199 + if (!p_bat) {
  200 + puts("BAT_TRATS2: Not found\n");
  201 + return -ENODEV;
  202 + }
  203 +
  204 + p_fg->parent = p_bat;
  205 + p_chrg->parent = p_bat;
  206 + p_muic->parent = p_bat;
  207 +
  208 + p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
  209 +
  210 + pb = p_bat->pbat;
  211 + chrg = p_muic->chrg->chrg_type(p_muic);
  212 + debug("CHARGER TYPE: %d\n", chrg);
  213 +
  214 + if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
  215 + puts("No battery detected\n");
  216 + return -1;
  217 + }
  218 +
  219 + p_fg->fg->fg_battery_check(p_fg, p_bat);
  220 +
  221 + if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
  222 + puts("CHARGE Battery !\n");
  223 +
  224 + return 0;
  225 +}
  226 +
  227 +int dram_init(void)
  228 +{
  229 + u32 size_mb;
  230 +
  231 + size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
  232 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
  233 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
  234 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
  235 +
  236 + gd->ram_size = size_mb << 20;
  237 +
  238 + return 0;
  239 +}
  240 +
  241 +void dram_init_banksize(void)
  242 +{
  243 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  244 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  245 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  246 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  247 + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  248 + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  249 + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
  250 + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
  251 +}
  252 +
  253 +int board_mmc_init(bd_t *bis)
  254 +{
  255 + int err0, err2 = 0;
  256 +
  257 + gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
  258 +
  259 + /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
  260 + s5p_gpio_direction_output(&gpio2->k0, 2, 1);
  261 + s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
  262 +
  263 + /*
  264 + * eMMC GPIO:
  265 + * SDR 8-bit@48MHz at MMC0
  266 + * GPK0[0] SD_0_CLK(2)
  267 + * GPK0[1] SD_0_CMD(2)
  268 + * GPK0[2] SD_0_CDn -> Not used
  269 + * GPK0[3:6] SD_0_DATA[0:3](2)
  270 + * GPK1[3:6] SD_0_DATA[0:3](3)
  271 + *
  272 + * DDR 4-bit@26MHz at MMC4
  273 + * GPK0[0] SD_4_CLK(3)
  274 + * GPK0[1] SD_4_CMD(3)
  275 + * GPK0[2] SD_4_CDn -> Not used
  276 + * GPK0[3:6] SD_4_DATA[0:3](3)
  277 + * GPK1[3:6] SD_4_DATA[4:7](4)
  278 + */
  279 +
  280 + err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
  281 +
  282 + /*
  283 + * MMC device init
  284 + * mmc0 : eMMC (8-bit buswidth)
  285 + * mmc2 : SD card (4-bit buswidth)
  286 + */
  287 + if (err0)
  288 + debug("SDMMC0 not configured\n");
  289 + else
  290 + err0 = s5p_mmc_init(0, 8);
  291 +
  292 + /* T-flash detect */
  293 + s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
  294 + s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
  295 +
  296 + /*
  297 + * Check the T-flash detect pin
  298 + * GPX3[4] T-flash detect pin
  299 + */
  300 + if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
  301 + err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
  302 + if (err2)
  303 + debug("SDMMC2 not configured\n");
  304 + else
  305 + err2 = s5p_mmc_init(2, 4);
  306 + }
  307 +
  308 + return err0 & err2;
  309 +}
  310 +
  311 +static int pmic_init_max77686(void)
  312 +{
  313 + struct pmic *p = pmic_get("MAX77686_PMIC");
  314 +
  315 + if (pmic_probe(p))
  316 + return -1;
  317 +
  318 + /* BUCK/LDO Output Voltage */
  319 + max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */
  320 + max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/
  321 + max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */
  322 +
  323 + /* BUCK/LDO Output Mode */
  324 + max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */
  325 + max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */
  326 + max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */
  327 + max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */
  328 + max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */
  329 + max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/
  330 + max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */
  331 + max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */
  332 + max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/
  333 +
  334 + max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/
  335 + max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */
  336 + max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */
  337 + max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */
  338 + max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */
  339 + max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */
  340 + max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */
  341 + max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */
  342 + max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/
  343 + max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/
  344 + max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/
  345 + max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/
  346 + max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */
  347 + max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */
  348 + max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/
  349 + max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/
  350 + max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/
  351 + max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/
  352 + max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */
  353 + max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/
  354 + max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */
  355 + max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/
  356 + max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/
  357 + max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */
  358 + max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */
  359 + max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/
  360 +
  361 + return 0;
  362 +}
  363 +
  364 +/*
  365 + * LCD
  366 + */
  367 +
  368 +#ifdef CONFIG_LCD
  369 +static struct mipi_dsim_config dsim_config = {
  370 + .e_interface = DSIM_VIDEO,
  371 + .e_virtual_ch = DSIM_VIRTUAL_CH_0,
  372 + .e_pixel_format = DSIM_24BPP_888,
  373 + .e_burst_mode = DSIM_BURST_SYNC_EVENT,
  374 + .e_no_data_lane = DSIM_DATA_LANE_4,
  375 + .e_byte_clk = DSIM_PLL_OUT_DIV8,
  376 + .hfp = 1,
  377 +
  378 + .p = 3,
  379 + .m = 120,
  380 + .s = 1,
  381 +
  382 + /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
  383 + .pll_stable_time = 500,
  384 +
  385 + /* escape clk : 10MHz */
  386 + .esc_clk = 20 * 1000000,
  387 +
  388 + /* stop state holding counter after bta change count 0 ~ 0xfff */
  389 + .stop_holding_cnt = 0x7ff,
  390 + /* bta timeout 0 ~ 0xff */
  391 + .bta_timeout = 0xff,
  392 + /* lp rx timeout 0 ~ 0xffff */
  393 + .rx_timeout = 0xffff,
  394 +};
  395 +
  396 +static struct exynos_platform_mipi_dsim dsim_platform_data = {
  397 + .lcd_panel_info = NULL,
  398 + .dsim_config = &dsim_config,
  399 +};
  400 +
  401 +static struct mipi_dsim_lcd_device mipi_lcd_device = {
  402 + .name = "s6e8ax0",
  403 + .id = -1,
  404 + .bus_id = 0,
  405 + .platform_data = (void *)&dsim_platform_data,
  406 +};
  407 +
  408 +static int mipi_power(void)
  409 +{
  410 + struct pmic *p = pmic_get("MAX77686_PMIC");
  411 +
  412 + /* LDO8 VMIPI_1.0V_AP */
  413 + max77686_set_ldo_mode(p, 8, OPMODE_ON);
  414 + /* LDO10 VMIPI_1.8V_AP */
  415 + max77686_set_ldo_mode(p, 10, OPMODE_ON);
  416 +
  417 + return 0;
  418 +}
  419 +
  420 +void exynos_lcd_power_on(void)
  421 +{
  422 + struct pmic *p = pmic_get("MAX77686_PMIC");
  423 +
  424 + gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
  425 +
  426 + /* LCD_2.2V_EN: GPC0[1] */
  427 + s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
  428 + s5p_gpio_direction_output(&gpio1->c0, 1, 1);
  429 +
  430 + /* LDO25 VCC_3.1V_LCD */
  431 + pmic_probe(p);
  432 + max77686_set_ldo_voltage(p, 25, 3100000);
  433 + max77686_set_ldo_mode(p, 25, OPMODE_LPM);
  434 +}
  435 +
  436 +void exynos_reset_lcd(void)
  437 +{
  438 + gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
  439 +
  440 + /* reset lcd */
  441 + s5p_gpio_direction_output(&gpio1->f2, 1, 0);
  442 + udelay(10);
  443 + s5p_gpio_set_value(&gpio1->f2, 1, 1);
  444 +}
  445 +
  446 +vidinfo_t panel_info = {
  447 + .vl_freq = 60,
  448 + .vl_col = 720,
  449 + .vl_row = 1280,
  450 + .vl_width = 720,
  451 + .vl_height = 1280,
  452 + .vl_clkp = CONFIG_SYS_HIGH,
  453 + .vl_hsp = CONFIG_SYS_LOW,
  454 + .vl_vsp = CONFIG_SYS_LOW,
  455 + .vl_dp = CONFIG_SYS_LOW,
  456 + .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
  457 +
  458 + /* s6e8ax0 Panel infomation */
  459 + .vl_hspw = 5,
  460 + .vl_hbpd = 10,
  461 + .vl_hfpd = 10,
  462 +
  463 + .vl_vspw = 2,
  464 + .vl_vbpd = 1,
  465 + .vl_vfpd = 13,
  466 + .vl_cmd_allow_len = 0xf,
  467 + .mipi_enabled = 1,
  468 +
  469 + .dual_lcd_enabled = 0,
  470 +
  471 + .init_delay = 0,
  472 + .power_on_delay = 25,
  473 + .reset_delay = 0,
  474 + .interface_mode = FIMD_RGB_INTERFACE,
  475 +};
  476 +
  477 +void init_panel_info(vidinfo_t *vid)
  478 +{
  479 + vid->logo_on = 1;
  480 + vid->resolution = HD_RESOLUTION;
  481 + vid->rgb_mode = MODE_RGB_P;
  482 +
  483 + vid->power_on_delay = 30;
  484 +
  485 + mipi_lcd_device.reverse_panel = 1;
  486 +
  487 +#ifdef CONFIG_TIZEN
  488 + get_tizen_logo_info(vid);
  489 +#endif
  490 +
  491 + strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
  492 + dsim_platform_data.mipi_power = mipi_power;
  493 + dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
  494 + dsim_platform_data.lcd_panel_info = (void *)vid;
  495 + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
  496 +
  497 + s6e8ax0_init();
  498 +
  499 + exynos_set_dsim_platform_data(&dsim_platform_data);
  500 +}
  501 +#endif /* LCD */
  502 +
  503 +#ifdef CONFIG_MISC_INIT_R
  504 +int misc_init_r(void)
  505 +{
  506 + setenv("model", "GT-I8800");
  507 + setenv("board", "TRATS2");
  508 +
  509 + show_hw_revision();
  510 +
  511 + return 0;
  512 +}
  513 +#endif
... ... @@ -274,6 +274,7 @@
274 274 Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
275 275 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
276 276 Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
  277 +Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
277 278 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Minkyu Kang <mk7.kang@samsung.com>
278 279 Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
279 280 Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
drivers/power/battery/Makefile
Diff comments   View file @ 5a91204
... ... @@ -10,6 +10,7 @@
10 10 LIB := $(obj)libbattery.o
11 11  
12 12 COBJS-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o
  13 +COBJS-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o
13 14  
14 15 COBJS := $(COBJS-y)
15 16 SRCS := $(COBJS:.o=.c)
drivers/power/battery/bat_trats2.c
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <power/pmic.h>
  10 +#include <power/battery.h>
  11 +#include <power/max8997_pmic.h>
  12 +#include <errno.h>
  13 +
  14 +static struct battery battery_trats;
  15 +
  16 +static int power_battery_charge(struct pmic *bat)
  17 +{
  18 + struct power_battery *p_bat = bat->pbat;
  19 +
  20 + if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450))
  21 + return -1;
  22 +
  23 + return 0;
  24 +}
  25 +
  26 +static int power_battery_init_trats2(struct pmic *bat_,
  27 + struct pmic *fg_,
  28 + struct pmic *chrg_,
  29 + struct pmic *muic_)
  30 +{
  31 + bat_->pbat->fg = fg_;
  32 + bat_->pbat->chrg = chrg_;
  33 + bat_->pbat->muic = muic_;
  34 +
  35 + bat_->fg = fg_->fg;
  36 + bat_->chrg = chrg_->chrg;
  37 + bat_->chrg->chrg_type = muic_->chrg->chrg_type;
  38 + return 0;
  39 +}
  40 +
  41 +static struct power_battery power_bat_trats2 = {
  42 + .bat = &battery_trats,
  43 + .battery_init = power_battery_init_trats2,
  44 + .battery_charge = power_battery_charge,
  45 +};
  46 +
  47 +int power_bat_init(unsigned char bus)
  48 +{
  49 + static const char name[] = "BAT_TRATS2";
  50 + struct pmic *p = pmic_alloc();
  51 +
  52 + if (!p) {
  53 + printf("%s: POWER allocation error!\n", __func__);
  54 + return -ENOMEM;
  55 + }
  56 +
  57 + debug("Board BAT init\n");
  58 +
  59 + p->interface = PMIC_NONE;
  60 + p->name = name;
  61 + p->bus = bus;
  62 +
  63 + p->pbat = &power_bat_trats2;
  64 + return 0;
  65 +}
drivers/power/mfd/Makefile
Diff comments   View file @ 5a91204
  1 +#
  2 +# Copyright (C) 2013 Samsung Electronics
  3 +# Piotr Wilczek <p.wilczek@samsung.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +include $(TOPDIR)/config.mk
  9 +
  10 +LIB := $(obj)libmfd.o
  11 +
  12 +COBJS-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o
  13 +COBJS-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o
  14 +COBJS-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o
  15 +
  16 +COBJS := $(COBJS-y)
  17 +SRCS := $(COBJS:.o=.c)
  18 +OBJS := $(addprefix $(obj),$(COBJS))
  19 +
  20 +all: $(LIB)
  21 +
  22 +$(LIB): $(obj).depend $(OBJS)
  23 + $(call cmd_link_o_target, $(OBJS))
  24 +
  25 +
  26 +#########################################################################
  27 +
  28 +# defines $(obj).depend target
  29 +include $(SRCTREE)/rules.mk
  30 +
  31 +sinclude $(obj).depend
  32 +
  33 +########################################################################
drivers/power/mfd/fg_max77693.c
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <power/pmic.h>
  10 +#include <power/max77693_fg.h>
  11 +#include <i2c.h>
  12 +#include <power/power_chrg.h>
  13 +#include <power/battery.h>
  14 +#include <power/fg_battery_cell_params.h>
  15 +#include <errno.h>
  16 +
  17 +static int max77693_get_vcell(u32 *vcell)
  18 +{
  19 + u16 value;
  20 + u8 ret;
  21 +
  22 + ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VCELL, 1,
  23 + (u8 *)&value, 2);
  24 + if (ret)
  25 + return ret;
  26 +
  27 + *vcell = (u32)(value >> 3);
  28 + *vcell = *vcell * 625;
  29 +
  30 + return 0;
  31 +}
  32 +
  33 +static int max77693_get_soc(u32 *soc)
  34 +{
  35 + u16 value;
  36 + u8 ret;
  37 +
  38 + ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VFSOC, 1,
  39 + (u8 *)&value, 2);
  40 + if (ret)
  41 + return ret;
  42 +
  43 + *soc = (u32)(value >> 8);
  44 +
  45 + return 0;
  46 +}
  47 +
  48 +static int power_update_battery(struct pmic *p, struct pmic *bat)
  49 +{
  50 + struct power_battery *pb = bat->pbat;
  51 + int ret;
  52 +
  53 + if (pmic_probe(p)) {
  54 + puts("Can't find max77693 fuel gauge\n");
  55 + return -1;
  56 + }
  57 +
  58 + ret = max77693_get_soc(&pb->bat->state_of_chrg);
  59 + if (ret)
  60 + return ret;
  61 +
  62 + max77693_get_vcell(&pb->bat->voltage_uV);
  63 + if (ret)
  64 + return ret;
  65 +
  66 + return 0;
  67 +}
  68 +
  69 +static int power_check_battery(struct pmic *p, struct pmic *bat)
  70 +{
  71 + struct power_battery *pb = bat->pbat;
  72 + unsigned int val;
  73 + int ret = 0;
  74 +
  75 + if (pmic_probe(p)) {
  76 + puts("Can't find max77693 fuel gauge\n");
  77 + return -1;
  78 + }
  79 +
  80 + ret = pmic_reg_read(p, MAX77693_STATUS, &val);
  81 + if (ret)
  82 + return ret;
  83 + debug("fg status: 0x%x\n", val);
  84 +
  85 + ret = pmic_reg_read(p, MAX77693_VERSION, &pb->bat->version);
  86 + if (ret)
  87 + return ret;
  88 +
  89 + ret = power_update_battery(p, bat);
  90 + if (ret)
  91 + return ret;
  92 + debug("fg ver: 0x%x\n", pb->bat->version);
  93 + printf("BAT: state_of_charge(SOC):%d%%\n",
  94 + pb->bat->state_of_chrg);
  95 +
  96 + printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n",
  97 + pb->bat->voltage_uV / 1000000,
  98 + pb->bat->voltage_uV % 1000000,
  99 + pb->bat->capacity);
  100 +
  101 + if (pb->bat->voltage_uV > 3850000)
  102 + pb->bat->state = EXT_SOURCE;
  103 + else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5)
  104 + pb->bat->state = CHARGE;
  105 + else
  106 + pb->bat->state = NORMAL;
  107 +
  108 + return 0;
  109 +}
  110 +
  111 +static struct power_fg power_fg_ops = {
  112 + .fg_battery_check = power_check_battery,
  113 + .fg_battery_update = power_update_battery,
  114 +};
  115 +
  116 +int power_fg_init(unsigned char bus)
  117 +{
  118 + static const char name[] = "MAX77693_FG";
  119 + struct pmic *p = pmic_alloc();
  120 +
  121 + if (!p) {
  122 + printf("%s: POWER allocation error!\n", __func__);
  123 + return -ENOMEM;
  124 + }
  125 +
  126 + debug("Board Fuel Gauge init\n");
  127 +
  128 + p->name = name;
  129 + p->interface = PMIC_I2C;
  130 + p->number_of_regs = FG_NUM_OF_REGS;
  131 + p->hw.i2c.addr = MAX77693_FUEL_I2C_ADDR;
  132 + p->hw.i2c.tx_num = 2;
  133 + p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG;
  134 + p->bus = bus;
  135 +
  136 + p->fg = &power_fg_ops;
  137 +
  138 + return 0;
  139 +}
drivers/power/mfd/muic_max77693.c
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <power/pmic.h>
  10 +#include <power/power_chrg.h>
  11 +#include <power/max77693_muic.h>
  12 +#include <i2c.h>
  13 +#include <errno.h>
  14 +
  15 +static int power_chrg_get_type(struct pmic *p)
  16 +{
  17 + unsigned int val;
  18 + unsigned int charge_type, charger;
  19 +
  20 + /* if probe failed, return cable none */
  21 + if (pmic_probe(p))
  22 + return CHARGER_NO;
  23 +
  24 + pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val);
  25 +
  26 + charge_type = val & MAX77693_MUIC_CHG_MASK;
  27 +
  28 + switch (charge_type) {
  29 + case MAX77693_MUIC_CHG_NO:
  30 + charger = CHARGER_NO;
  31 + break;
  32 + case MAX77693_MUIC_CHG_USB:
  33 + case MAX77693_MUIC_CHG_USB_D:
  34 + charger = CHARGER_USB;
  35 + break;
  36 + case MAX77693_MUIC_CHG_TA:
  37 + case MAX77693_MUIC_CHG_TA_1A:
  38 + charger = CHARGER_TA;
  39 + break;
  40 + case MAX77693_MUIC_CHG_TA_500:
  41 + charger = CHARGER_TA_500;
  42 + break;
  43 + default:
  44 + charger = CHARGER_UNKNOWN;
  45 + break;
  46 + }
  47 +
  48 + return charger;
  49 +}
  50 +
  51 +static struct power_chrg power_chrg_muic_ops = {
  52 + .chrg_type = power_chrg_get_type,
  53 +};
  54 +
  55 +int power_muic_init(unsigned int bus)
  56 +{
  57 + static const char name[] = "MAX77693_MUIC";
  58 + struct pmic *p = pmic_alloc();
  59 +
  60 + if (!p) {
  61 + printf("%s: POWER allocation error!\n", __func__);
  62 + return -ENOMEM;
  63 + }
  64 +
  65 + debug("Board Micro USB Interface Controller init\n");
  66 +
  67 + p->name = name;
  68 + p->interface = PMIC_I2C;
  69 + p->number_of_regs = MUIC_NUM_OF_REGS;
  70 + p->hw.i2c.addr = MAX77693_MUIC_I2C_ADDR;
  71 + p->hw.i2c.tx_num = 1;
  72 + p->bus = bus;
  73 +
  74 + p->chrg = &power_chrg_muic_ops;
  75 +
  76 + return 0;
  77 +}
drivers/power/mfd/pmic_max77693.c
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <power/pmic.h>
  10 +#include <power/max77693_pmic.h>
  11 +#include <i2c.h>
  12 +#include <errno.h>
  13 +
  14 +static int max77693_charger_state(struct pmic *p, int state, int current)
  15 +{
  16 + unsigned int val;
  17 +
  18 + if (pmic_probe(p))
  19 + return -1;
  20 +
  21 + /* unlock write capability */
  22 + val = MAX77693_CHG_UNLOCK;
  23 + pmic_reg_write(p, MAX77693_CHG_CNFG_06, val);
  24 +
  25 + if (state == CHARGER_DISABLE) {
  26 + puts("Disable the charger.\n");
  27 + pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val);
  28 + val &= ~0x01;
  29 + pmic_reg_write(p, MAX77693_CHG_CNFG_00, val);
  30 + return -1;
  31 + }
  32 +
  33 + if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) {
  34 + printf("%s: Wrong charge current: %d [mA]\n",
  35 + __func__, current);
  36 + return -1;
  37 + }
  38 +
  39 + /* set charging current */
  40 + pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val);
  41 + val &= ~MAX77693_CHG_CC;
  42 + val |= current * 10 / 333; /* 0.1A/3 steps */
  43 + pmic_reg_write(p, MAX77693_CHG_CNFG_02, val);
  44 +
  45 + /* enable charging */
  46 + val = MAX77693_CHG_MODE_ON;
  47 + pmic_reg_write(p, MAX77693_CHG_CNFG_00, val);
  48 +
  49 + /* check charging current */
  50 + pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val);
  51 + val &= 0x3f;
  52 + printf("Enable the charger @ %d [mA]\n", val * 333 / 10);
  53 +
  54 + return 0;
  55 +}
  56 +
  57 +static int max77693_charger_bat_present(struct pmic *p)
  58 +{
  59 + unsigned int val;
  60 +
  61 + if (pmic_probe(p))
  62 + return -1;
  63 +
  64 + pmic_reg_read(p, MAX77693_CHG_INT_OK, &val);
  65 +
  66 + return !(val & MAX77693_CHG_DETBAT);
  67 +}
  68 +
  69 +static struct power_chrg power_chrg_pmic_ops = {
  70 + .chrg_bat_present = max77693_charger_bat_present,
  71 + .chrg_state = max77693_charger_state,
  72 +};
  73 +
  74 +int pmic_init_max77693(unsigned char bus)
  75 +{
  76 + static const char name[] = "MAX77693_PMIC";
  77 + struct pmic *p = pmic_alloc();
  78 +
  79 + if (!p) {
  80 + printf("%s: POWER allocation error!\n", __func__);
  81 + return -ENOMEM;
  82 + }
  83 +
  84 + debug("Board PMIC init\n");
  85 +
  86 + p->name = name;
  87 + p->interface = PMIC_I2C;
  88 + p->number_of_regs = PMIC_NUM_OF_REGS;
  89 + p->hw.i2c.addr = MAX77693_PMIC_I2C_ADDR;
  90 + p->hw.i2c.tx_num = 1;
  91 + p->bus = bus;
  92 +
  93 + p->chrg = &power_chrg_pmic_ops;
  94 +
  95 + return 0;
  96 +}
include/configs/trats2.h
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Sanghee Kim <sh0130.kim@samsung.com>
  4 + * Piotr Wilczek <p.wilczek@samsung.com>
  5 + *
  6 + * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef __CONFIG_H
  12 +#define __CONFIG_H
  13 +
  14 +/*
  15 + * High Level Configuration Options
  16 + * (easy to change)
  17 + */
  18 +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
  19 +#define CONFIG_S5P /* which is in a S5P Family */
  20 +#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
  21 +#define CONFIG_TIZEN /* TIZEN lib */
  22 +
  23 +#define PLATFORM_NO_UNALIGNED
  24 +
  25 +#include <asm/arch/cpu.h> /* get chip and board defs */
  26 +
  27 +#define CONFIG_ARCH_CPU_INIT
  28 +#define CONFIG_DISPLAY_CPUINFO
  29 +#define CONFIG_DISPLAY_BOARDINFO
  30 +
  31 +#define CONFIG_SKIP_LOWLEVEL_INIT
  32 +
  33 +#define CONFIG_SYS_CACHELINE_SIZE 32
  34 +
  35 +#ifndef CONFIG_SYS_L2CACHE_OFF
  36 +#define CONFIG_SYS_L2_PL310
  37 +#define CONFIG_SYS_PL310_BASE 0x10502000
  38 +#endif
  39 +
  40 +#define CONFIG_NR_DRAM_BANKS 4
  41 +#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
  42 +#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
  43 +#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
  44 +#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
  45 +#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
  46 +#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
  47 +#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
  48 +#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
  49 +#define PHYS_SDRAM_END 0x80000000
  50 +
  51 +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
  52 +
  53 +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
  54 +#define CONFIG_SYS_TEXT_BASE 0x78100000
  55 +
  56 +#define CONFIG_SYS_CLK_FREQ 24000000
  57 +
  58 +#define CONFIG_SETUP_MEMORY_TAGS
  59 +#define CONFIG_CMDLINE_TAG
  60 +#define CONFIG_REVISION_TAG
  61 +
  62 +/* MACH_TYPE_TRATS2 */
  63 +#define MACH_TYPE_TRATS2 3765
  64 +#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2
  65 +
  66 +#define CONFIG_DISPLAY_CPUINFO
  67 +
  68 +/*
  69 + * Size of malloc() pool
  70 + */
  71 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
  72 +
  73 +/* select serial console configuration */
  74 +#define CONFIG_SERIAL2
  75 +
  76 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  77 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  78 +
  79 +#define CONFIG_CMDLINE_EDITING
  80 +
  81 +#define CONFIG_BAUDRATE 115200
  82 +
  83 +/* It should define before config_cmd_default.h */
  84 +#define CONFIG_SYS_NO_FLASH
  85 +
  86 +/***********************************************************
  87 + * Command definition
  88 + ***********************************************************/
  89 +#include <config_cmd_default.h>
  90 +
  91 +#undef CONFIG_CMD_ECHO
  92 +#undef CONFIG_CMD_FPGA
  93 +#undef CONFIG_CMD_FLASH
  94 +#undef CONFIG_CMD_IMLS
  95 +#undef CONFIG_CMD_NAND
  96 +#undef CONFIG_CMD_MISC
  97 +#undef CONFIG_CMD_NFS
  98 +#undef CONFIG_CMD_SOURCE
  99 +#undef CONFIG_CMD_XIMG
  100 +#define CONFIG_CMD_CACHE
  101 +#define CONFIG_CMD_I2C
  102 +#define CONFIG_CMD_MMC
  103 +#define CONFIG_CMD_GPT
  104 +#define CONFIG_CMD_PMIC
  105 +
  106 +#define CONFIG_BOOTDELAY 3
  107 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  108 +
  109 +#define CONFIG_CMD_FAT
  110 +#define CONFIG_FAT_WRITE
  111 +
  112 +/* EXT4 */
  113 +#define CONFIG_CMD_EXT4
  114 +#define CONFIG_CMD_EXT4_WRITE
  115 +
  116 +/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
  117 +#undef CONFIG_CMD_NET
  118 +
  119 +/* MMC */
  120 +#define CONFIG_GENERIC_MMC
  121 +#define CONFIG_MMC
  122 +#define CONFIG_S5P_SDHCI
  123 +#define CONFIG_SDHCI
  124 +#define CONFIG_MMC_SDMA
  125 +#define CONFIG_MMC_DEFAULT_DEV 0
  126 +
  127 +/* PWM */
  128 +#define CONFIG_PWM
  129 +
  130 +#define CONFIG_BOOTARGS "Please use defined boot"
  131 +#define CONFIG_BOOTCOMMAND "run mmcboot"
  132 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
  133 +
  134 +#define CONFIG_ENV_OVERWRITE
  135 +#define CONFIG_SYS_CONSOLE_INFO_QUIET
  136 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  137 +
  138 +/* Tizen - partitions definitions */
  139 +#define PARTS_CSA "csa-mmc"
  140 +#define PARTS_BOOTLOADER "u-boot"
  141 +#define PARTS_BOOT "boot"
  142 +#define PARTS_ROOT "platform"
  143 +#define PARTS_DATA "data"
  144 +#define PARTS_CSC "csc"
  145 +#define PARTS_UMS "ums"
  146 +
  147 +#define PARTS_DEFAULT \
  148 + "uuid_disk=${uuid_gpt_disk};" \
  149 + "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
  150 + "name="PARTS_BOOTLOADER",size=60MiB," \
  151 + "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
  152 + "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
  153 + "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
  154 + "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
  155 + "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
  156 + "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
  157 +
  158 +#define CONFIG_EXTRA_ENV_SETTINGS \
  159 + "bootk=" \
  160 + "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
  161 + "updatemmc=" \
  162 + "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
  163 + "mmc boot 0 1 1 0\0" \
  164 + "updatebackup=" \
  165 + "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
  166 + " mmc boot 0 1 1 0\0" \
  167 + "updatebootb=" \
  168 + "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
  169 + "updateuboot=" \
  170 + "mmc write 0x50000000 0x80 0x400\0" \
  171 + "mmcboot=" \
  172 + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
  173 + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
  174 + "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
  175 + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
  176 + "boottrace=setenv opts initcall_debug; run bootcmd\0" \
  177 + "verify=n\0" \
  178 + "rootfstype=ext4\0" \
  179 + "console=" CONFIG_DEFAULT_CONSOLE \
  180 + "kernelname=uImage\0" \
  181 + "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
  182 + "0x40007FC0 ${kernelname}\0" \
  183 + "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
  184 + "${fdtfile}\0" \
  185 + "mmcdev=0\0" \
  186 + "mmcbootpart=2\0" \
  187 + "mmcrootpart=5\0" \
  188 + "opts=always_resume=1\0" \
  189 + "partitions=" PARTS_DEFAULT \
  190 + "uartpath=ap\0" \
  191 + "usbpath=ap\0" \
  192 + "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
  193 + "consoleoff=set console console=ram; save; reset\0" \
  194 + "spladdr=0x40000100\0" \
  195 + "splsize=0x200\0" \
  196 + "splfile=falcon.bin\0" \
  197 + "spl_export=" \
  198 + "setexpr spl_imgsize ${splsize} + 8 ;" \
  199 + "setenv spl_imgsize 0x${spl_imgsize};" \
  200 + "setexpr spl_imgaddr ${spladdr} - 8 ;" \
  201 + "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
  202 + "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
  203 + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
  204 + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
  205 + "spl export atags 0x40007FC0;" \
  206 + "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
  207 + "mw.l ${spl_addr_tmp} ${splsize};" \
  208 + "ext4write mmc ${mmcdev}:${mmcbootpart}" \
  209 + " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
  210 + "setenv spl_imgsize;" \
  211 + "setenv spl_imgaddr;" \
  212 + "setenv spl_addr_tmp;\0" \
  213 + "fdtaddr=40800000\0" \
  214 + "fdtfile=exynos4412-trats2.dtb\0"
  215 +
  216 +/*
  217 + * Miscellaneous configurable options
  218 + */
  219 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  220 +#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
  221 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  222 +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
  223 +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  224 +
  225 +/* Boot Argument Buffer Size */
  226 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  227 +
  228 +/* memtest works on */
  229 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  230 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
  231 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
  232 +
  233 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
  234 + - GENERATED_GBL_DATA_SIZE)
  235 +
  236 +#define CONFIG_SYS_HZ 1000
  237 +
  238 +/* valid baudrates */
  239 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  240 +
  241 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
  242 +
  243 +/*-----------------------------------------------------------------------
  244 + * FLASH and environment organization
  245 + */
  246 +
  247 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  248 +
  249 +#define CONFIG_ENV_IS_IN_MMC
  250 +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
  251 +#define CONFIG_ENV_SIZE 4096
  252 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
  253 +#define CONFIG_EFI_PARTITION
  254 +#define CONFIG_PARTITION_UUIDS
  255 +
  256 +#define CONFIG_MISC_INIT_R
  257 +#define CONFIG_BOARD_EARLY_INIT_F
  258 +
  259 +/* I2C */
  260 +#include <asm/arch/gpio.h>
  261 +
  262 +#define CONFIG_SYS_I2C
  263 +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  264 +#define CONFIG_SYS_I2C_SOFT_SPEED 50000
  265 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
  266 +#define I2C_SOFT_DECLARATIONS2
  267 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
  268 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
  269 +#define I2C_SOFT_DECLARATIONS3
  270 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
  271 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00
  272 +#define CONFIG_SOFT_I2C_READ_REPEATED_START
  273 +#define CONFIG_SYS_I2C_INIT_BOARD
  274 +#define CONFIG_I2C_MULTI_BUS
  275 +#define CONFIG_SOFT_I2C_MULTI_BUS
  276 +#define CONFIG_SYS_MAX_I2C_BUS 15
  277 +
  278 +#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
  279 +#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
  280 +#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
  281 +#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
  282 +#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
  283 +#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
  284 +#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
  285 +#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
  286 +#define I2C_INIT multi_i2c_init()
  287 +
  288 +/* POWER */
  289 +#define CONFIG_POWER
  290 +#define CONFIG_POWER_I2C
  291 +#define CONFIG_POWER_MAX77686
  292 +#define CONFIG_POWER_PMIC_MAX77693
  293 +#define CONFIG_POWER_MUIC_MAX77693
  294 +#define CONFIG_POWER_FG_MAX77693
  295 +#define CONFIG_POWER_BATTERY_TRATS2
  296 +
  297 +/* LCD */
  298 +#define CONFIG_EXYNOS_FB
  299 +#define CONFIG_LCD
  300 +#define CONFIG_CMD_BMP
  301 +#define CONFIG_BMP_32BPP
  302 +#define CONFIG_FB_ADDR 0x52504000
  303 +#define CONFIG_S6E8AX0
  304 +#define CONFIG_EXYNOS_MIPI_DSIM
  305 +#define CONFIG_VIDEO_BMP_GZIP
  306 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
  307 +
  308 +/* Pass open firmware flat tree */
  309 +#define CONFIG_OF_LIBFDT 1
  310 +
  311 +#endif /* __CONFIG_H */
include/power/max77693_fg.h
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __MAX77693_FG_H_
  9 +#define __MAX77693_FG_H_
  10 +
  11 +/* MAX 77693 registers */
  12 +enum {
  13 + MAX77693_STATUS = 0x00,
  14 + MAX77693_SOCREP = 0x06,
  15 + MAX77693_VCELL = 0x09,
  16 + MAX77693_CURRENT = 0x0A,
  17 + MAX77693_AVG_CURRENT = 0x0B,
  18 + MAX77693_SOCMIX = 0x0D,
  19 + MAX77693_SOCAV = 0x0E,
  20 + MAX77693_DESIGN_CAP = 0x18,
  21 + MAX77693_AVG_VCELL = 0x19,
  22 + MAX77693_CONFIG = 0x1D,
  23 + MAX77693_VERSION = 0x21,
  24 + MAX77693_LEARNCFG = 0x28,
  25 + MAX77693_FILTERCFG = 0x29,
  26 + MAX77693_RELAXCFG = 0x2A,
  27 + MAX77693_MISCCFG = 0x2B,
  28 + MAX77693_CGAIN = 0x2E,
  29 + MAX77693_COFF = 0x2F,
  30 + MAX77693_RCOMP0 = 0x38,
  31 + MAX77693_TEMPCO = 0x39,
  32 + MAX77693_FSTAT = 0x3D,
  33 + MAX77693_VFOCV = 0xEE,
  34 + MAX77693_VFSOC = 0xFF,
  35 +
  36 + FG_NUM_OF_REGS = 0x100,
  37 +};
  38 +
  39 +#define MAX77693_POR (1 << 1)
  40 +
  41 +#define MODEL_UNLOCK1 0x0059
  42 +#define MODEL_UNLOCK2 0x00c4
  43 +#define MODEL_LOCK1 0x0000
  44 +#define MODEL_LOCK2 0x0000
  45 +
  46 +#define MAX77693_FUEL_I2C_ADDR (0x6C >> 1)
  47 +
  48 +int power_fg_init(unsigned char bus);
  49 +#endif /* __MAX77693_FG_H_ */
include/power/max77693_muic.h
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __MAX77693_MUIC_H_
  9 +#define __MAX77693_MUIC_H_
  10 +
  11 +#include <power/power_chrg.h>
  12 +
  13 +/*
  14 + * MUIC REGISTER
  15 + */
  16 +
  17 +#define MAX77693_MUIC_PREFIX "max77693-muic:"
  18 +
  19 +/* MAX77693_MUIC_STATUS1 */
  20 +#define MAX77693_MUIC_ADC_MASK 0x1F
  21 +
  22 +/* MAX77693_MUIC_STATUS2 */
  23 +#define MAX77693_MUIC_CHG_NO 0x00
  24 +#define MAX77693_MUIC_CHG_USB 0x01
  25 +#define MAX77693_MUIC_CHG_USB_D 0x02
  26 +#define MAX77693_MUIC_CHG_TA 0x03
  27 +#define MAX77693_MUIC_CHG_TA_500 0x04
  28 +#define MAX77693_MUIC_CHG_TA_1A 0x05
  29 +#define MAX77693_MUIC_CHG_MASK 0x07
  30 +
  31 +/* MAX77693_MUIC_CONTROL1 */
  32 +#define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1)
  33 +#define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3)
  34 +#define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4)
  35 +#define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5)
  36 +#define MAX77693_MUIC_CTRL1_MASK 0xC0
  37 +
  38 +#define MUIC_PATH_USB 0
  39 +#define MUIC_PATH_UART 1
  40 +
  41 +#define MUIC_PATH_CP 0
  42 +#define MUIC_PATH_AP 1
  43 +
  44 +enum muic_path {
  45 + MUIC_PATH_USB_CP,
  46 + MUIC_PATH_USB_AP,
  47 + MUIC_PATH_UART_CP,
  48 + MUIC_PATH_UART_AP,
  49 +};
  50 +
  51 +/* MAX 777693 MUIC registers */
  52 +enum {
  53 + MAX77693_MUIC_ID = 0x00,
  54 + MAX77693_MUIC_INT1 = 0x01,
  55 + MAX77693_MUIC_INT2 = 0x02,
  56 + MAX77693_MUIC_INT3 = 0x03,
  57 + MAX77693_MUIC_STATUS1 = 0x04,
  58 + MAX77693_MUIC_STATUS2 = 0x05,
  59 + MAX77693_MUIC_STATUS3 = 0x06,
  60 + MAX77693_MUIC_INTMASK1 = 0x07,
  61 + MAX77693_MUIC_INTMASK2 = 0x08,
  62 + MAX77693_MUIC_INTMASK3 = 0x09,
  63 + MAX77693_MUIC_CDETCTRL = 0x0A,
  64 + MAX77693_MUIC_CONTROL1 = 0x0C,
  65 + MAX77693_MUIC_CONTROL2 = 0x0D,
  66 + MAX77693_MUIC_CONTROL3 = 0x0E,
  67 +
  68 + MUIC_NUM_OF_REGS = 0x0F,
  69 +};
  70 +
  71 +#define MAX77693_MUIC_I2C_ADDR (0x4A >> 1)
  72 +
  73 +int power_muic_init(unsigned int bus);
  74 +#endif /* __MAX77693_MUIC_H_ */
include/power/max77693_pmic.h
Diff comments   View file @ 5a91204
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + * Piotr Wilczek <p.wilczek@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __MAX77693_PMIC_H_
  9 +#define __MAX77693_PMIC_H_
  10 +
  11 +#include <power/power_chrg.h>
  12 +
  13 +enum {CHARGER_ENABLE, CHARGER_DISABLE};
  14 +
  15 +#define CHARGER_MIN_CURRENT 200
  16 +#define CHARGER_MAX_CURRENT 2000
  17 +
  18 +#define MAX77693_CHG_PREFIX "max77693-chg:"
  19 +
  20 +/* Registers */
  21 +
  22 +#define MAX77693_CHG_BASE 0xB0
  23 +#define MAX77693_CHG_INT_OK 0xB2
  24 +#define MAX77693_CHG_CNFG_00 0xB7
  25 +#define MAX77693_CHG_CNFG_02 0xB9
  26 +#define MAX77693_CHG_CNFG_06 0xBD
  27 +#define MAX77693_SAFEOUT 0xC6
  28 +
  29 +#define PMIC_NUM_OF_REGS 0xC7
  30 +
  31 +#define MAX77693_CHG_DETBAT (0x1 << 7) /* MAX77693_CHG_INT_OK */
  32 +#define MAX77693_CHG_MODE_ON 0x05 /* MAX77693_CHG_CNFG_00 */
  33 +#define MAX77693_CHG_CC 0x3F /* MAX77693_CHG_CNFG_02 */
  34 +#define MAX77693_CHG_LOCK (0x0 << 2) /* MAX77693_CHG_CNFG_06 */
  35 +#define MAX77693_CHG_UNLOCK (0x3 << 2) /* MAX77693_CHG_CNFG_06 */
  36 +
  37 +#define MAX77693_ENSAFEOUT1 (1 << 6)
  38 +#define MAX77693_ENSAFEOUT2 (1 << 7)
  39 +
  40 +#define MAX77693_PMIC_I2C_ADDR (0xCC >> 1)
  41 +
  42 +int pmic_init_max77693(unsigned char bus);
  43 +#endif /* __MAX77693_PMIC_H_ */