mpc85xx: Add support for the supplement configuration unit register

The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

mpc85xx: Add support for the supplement configuration unit register
The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian · York Sun
1 parent 349689b802
Showing 1 changed file with 22 additions and 0 deletions Side-by-side Diff
arch/powerpc/include/asm/immap_85xx.h
@@ -3156,5 +3156,27 @@
 #define	DCSR_DCFG_ECC_DISABLE_USB2	0x00004000
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
+	u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
+	u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
+	u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
+	u32 res1[4];
+	u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
+	u32 res2;
+	u32 pixclkcr;	/* 0x028 Pixel Clock Control register */
+	u32 res3[245];
+	u32 qeioclkcr;	/* 0x400 QUICC Engine IO Clock Control register */
+	u32 emiiocr;	/* 0x404 EMI MDIO Control Register */
+	u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
+	u32 qmifrstcr;	/* 0x40c QMAN Interface Reset Control register */
+	u32 res4[60];
+	u32 sparecr[8];	/* 0x500 Spare Control register(0-7) */
+};
 #endif /*__IMMAP_85xx__*/
...	...	@@ -3156,5 +3156,27 @@
3156	3156	#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3157	3157	u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3158	3158	};
	3159	+
	3160	+#define CONFIG_SYS_MPC85xx_SCFG \
	3161	+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
	3162	+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
	3163	+/* The supplement configuration unit register */
	3164	+struct ccsr_scfg {
	3165	+ u32 dpslpcr; /* 0x000 Deep Sleep Control register */
	3166	+ u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
	3167	+ u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
	3168	+ u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
	3169	+ u32 res1[4];
	3170	+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
	3171	+ u32 res2;
	3172	+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
	3173	+ u32 res3[245];
	3174	+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
	3175	+ u32 emiiocr; /* 0x404 EMI MDIO Control Register */
	3176	+ u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
	3177	+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
	3178	+ u32 res4[60];
	3179	+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
	3180	+};
3159	3181	#endif /__IMMAP_85xx__/