Eric Lee / smarc-uboot

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Commit 5b2e72f32721484d2dea3d0dcf8c020bf3cbe574

Authored by Jean-Jacques Hiblot
Committed by Jaehoon Chung
1 parent d6400c3f85
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

mmc: read ssr only if MMC write support is enabled 

The content of ssr is useful only for erase operations.
on ARM, removing sd_read_ssr() saves around 300 bytes.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

Showing 2 changed files with 16 additions and 11 deletions Side-by-side Diff

... ... @@ -22,14 +22,6 @@
22 22 #include <div64.h>
23 23 #include "mmc_private.h"
24 24  
25   -static const unsigned int sd_au_size[] = {
26   - 0, SZ_16K / 512, SZ_32K / 512,
27   - SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28   - SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29   - SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30   - SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31   -};
32   -
33 25 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
34 26 static int mmc_power_cycle(struct mmc *mmc);
35 27 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
36 28  
... ... @@ -1376,8 +1368,17 @@
1376 1368 return 0;
1377 1369 }
1378 1370  
  1371 +#if CONFIG_IS_ENABLED(MMC_WRITE)
1379 1372 static int sd_read_ssr(struct mmc *mmc)
1380 1373 {
  1374 + static const unsigned int sd_au_size[] = {
  1375 + 0, SZ_16K / 512, SZ_32K / 512,
  1376 + SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  1377 + SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  1378 + SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  1379 + SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
  1380 + SZ_64M / 512,
  1381 + };
1381 1382 int err, i;
1382 1383 struct mmc_cmd cmd;
1383 1384 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
... ... @@ -1431,7 +1432,7 @@
1431 1432  
1432 1433 return 0;
1433 1434 }
1434   -
  1435 +#endif
1435 1436 /* frequency bases */
1436 1437 /* divided by 10 to be nice to platforms without floating point */
1437 1438 static const int fbase[] = {
1438 1439  
1439 1440  
... ... @@ -1689,11 +1690,13 @@
1689 1690 }
1690 1691 #endif
1691 1692  
  1693 +#if CONFIG_IS_ENABLED(MMC_WRITE)
1692 1694 err = sd_read_ssr(mmc);
1693 1695 if (!err)
  1696 + pr_warn("unable to read ssr\n");
  1697 +#endif
  1698 + if (!err)
1694 1699 return 0;
1695   -
1696   - pr_warn("bad ssr\n");
1697 1700  
1698 1701 error:
1699 1702 /* revert to a safer bus speed */
... ... @@ -588,7 +588,9 @@
588 588 uint write_bl_len;
589 589 uint erase_grp_size; /* in 512-byte sectors */
590 590 uint hc_wp_grp_size; /* in 512-byte sectors */
  591 +#if CONFIG_IS_ENABLED(MMC_WRITE)
591 592 struct sd_ssr ssr; /* SD status register */
  593 +#endif
592 594 u64 capacity;
593 595 u64 capacity_user;
594 596 u64 capacity_boot;