ARM: imx: mx6ull: Add iMX6ULL VisionSOM SoM and EVK

Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support. The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier board has Ethernet, USB host port, USB OTG port. Signed-off-by: Arkadiusz Karas <arkadiusz.karas@somlabs.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>

ARM: imx: mx6ull: Add iMX6ULL VisionSOM SoM and EVK
Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support. The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier board has Ethernet, USB host port, USB OTG port. Signed-off-by: Arkadiusz Karas <arkadiusz.karas@somlabs.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Arkadiusz Karas · Stefano Babic
1 parent 9d12303322
Showing 10 changed files with 730 additions and 0 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/imx6ull-somlabs-visionsom.dts
arch/arm/mach-imx/mx6/Kconfig
board/somlabs/visionsom-6ull/Kconfig
board/somlabs/visionsom-6ull/MAINTAINERS
board/somlabs/visionsom-6ull/Makefile
board/somlabs/visionsom-6ull/imximage.cfg
board/somlabs/visionsom-6ull/visionsom-6ull.c
configs/somlabs_visionsom_6ull_defconfig
include/configs/somlabs_visionsom_6ull.h
@@ -676,6 +676,7 @@
 	imx6ull-colibri.dtb \
 	imx6ull-phytec-segin-ff-rdk-emmc.dtb \
 	imx6ull-dart-6ul.dtb \
+	imx6ull-somlabs-visionsom.dtb \
 	imx6ulz-14x14-evk.dtb
  
 dtb-$(CONFIG_ARCH_MX6) += \
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2019 SoMLabs
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "SoMLabs VisionSOM-6ULL";
+	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		usr0 {
+			label = "usr0";
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		usr1 {
+			label = "usr1";
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+		};
+
+		usr2 {
+			label = "usr2";
+			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc1";
+		};
+
+		usr3 {
+			label = "usr3";
+			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg1>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg2>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+	};
+};
+
+&cpu0 {
+	arm-supply = <&reg_arm>;
+	soc-supply = <&reg_soc>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+
+};
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0x1>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+
+};
+
+&i2c2 {
+	clock_frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	pinctrl_hog_1: hoggrp-1 {
+		fsl,pins = <
+			/* 32kHz low power reference clock for WiFi */
+			MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT	0x17099
+			/* LED 0..3 */
+			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x17099
+			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x17099
+			MX6UL_PAD_JTAG_TDI__GPIO1_IO13		0x17099
+			MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x17099
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1F829
+
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x400010a9
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
+			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
+		>;
+	};
+
+	pinctrl_tsc: tscgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
+			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
+			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
+			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY	0x30b0
+		>;
+	};
+
+	pinctrl_usb_otg1: usbotg1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+			MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12	0x10b0
+		>;
+	};
+
+	pinctrl_usb_otg2: usbotg2grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x10b0
+		>;
+	};
+};
+
+&tsc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_tsc>;
+	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+	measure-delay-time = <0xffff>;
+	pre-charge-time = <0xfff>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbphy1 {
+	tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+	tx-d-cal = <0x5>;
+};
+
+&usdhc2 {
+	non-removable;
+	disable-wp;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,wdog_b;
+};
@@ -540,6 +540,18 @@
 	bool "sks-imx6"
 	select SUPPORT_SPL
  
+config TARGET_SOMLABS_VISIONSOM_6ULL
+	bool "visionsom-6ull"
+	select MX6ULL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_MMC
+	select DM_SERIAL
+	select DM_THERMAL
+	imply CMD_DM
+
 config TARGET_TBS2910
 	bool "TBS2910 Matrix ARM mini PC"
  
@@ -694,6 +706,7 @@
 source "board/seco/Kconfig"
 source "board/sks-kinkel/sksimx6/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/somlabs/visionsom-6ull/Kconfig"
 source "board/technexion/pico-imx6/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
+if TARGET_SOMLABS_VISIONSOM_6ULL
+
+config SYS_BOARD
+	default "visionsom-6ull"
+
+config SYS_VENDOR
+	default "somlabs"
+
+config SYS_CONFIG_NAME
+	default "somlabs_visionsom_6ull"
+
+endif
+VISIONSOM-6ULL BOARD
+M:	Arkadiusz Karas <arkadiusz.karas@somlabs.com>
+S:	Maintained
+F:	board/somlabs/visionsom-6ull/
+F:	include/configs/somlabs_visionsom_6ull.h
+F:	configs/somlabs_visionsom_6ull_defconfig
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas@somlabs.com>
+
+obj-y  := visionsom-6ull.o
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 A. Karas
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Micron MT41K256M16TW-107 */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x41570155
+DATA 4 0x021B0848 0x4040474A
+DATA 4 0x021B0850 0x40405550
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x23400A38
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2019 A. Karas, SomLabs
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	if (is_cpu_type(MXC_CPU_MX6ULL))
+		env_set("board", "visionsom-6ull");
+	else
+		env_set("board", "visionsom-6ul");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: SoMLabs VisionSOM-6UL%s\n",
+	       is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
+
+	return 0;
+}
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017-2019 A. Karas, SomLabs
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the SoMlabs VisionSOM 6ULL board.
+ */
+#ifndef __SOMLABS_VISIONSOM_6ULL_H
+#define __SOMLABS_VISIONSOM_6ULL_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/mach-imx/gpio.h>
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#endif /* CONFIG_FSL_USDHC */
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"console=ttymxc0\0" \
+	"initrd_addr=0x86800000\0" \
+	"fdt_addr=0x83000000\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"splashimage=0x80000000\0" \
+	"splashfile=/boot/splash.bmp\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p1 rootwait rw\0" \
+	"setrootmmc=setenv rootspec root=${mmcroot}\0" \
+	"setbootscriptmmc=setenv loadbootscript " \
+		"load mmc ${mmcdev}:${mmcpart} " \
+		"${loadaddr} /boot/${script};\0" \
+	"setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \
+		"${loadaddr} /boot/${image}; " \
+		"setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \
+		"${fdt_addr} /boot/${fdt_file};\0" \
+	"setbootargs=setenv bootargs console=${console},${baudrate} " \
+		"${rootspec}\0" \
+	"execbootscript=echo Running bootscript...; source\0" \
+	"setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \
+	"checkbootdev=run setbootscriptmmc; " \
+		"run setrootmmc; " \
+		"run setloadmmc; " \
+
+#define CONFIG_BOOTCOMMAND \
+	"run setfdtfile; " \
+	"run checkbootdev; " \
+	"run loadfdt;" \
+	"if run loadbootscript; then " \
+		"run bootscript; " \
+	"else " \
+		"if run loadimage; then " \
+			"run setbootargs; " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"fi; " \
+	"fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"eth0"
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#endif
...	...	@@ -676,6 +676,7 @@
676	676	imx6ull-colibri.dtb \
677	677	imx6ull-phytec-segin-ff-rdk-emmc.dtb \
678	678	imx6ull-dart-6ul.dtb \
	679	+ imx6ull-somlabs-visionsom.dtb \
679	680	imx6ulz-14x14-evk.dtb
680	681
681	682	dtb-$(CONFIG_ARCH_MX6) += \
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * Copyright (C) 2017-2019 SoMLabs
	4	+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
	5	+ */
	6	+
	7	+/dts-v1/;
	8	+
	9	+#include <dt-bindings/input/input.h>
	10	+#include "imx6ull.dtsi"
	11	+
	12	+/ {
	13	+ model = "SoMLabs VisionSOM-6ULL";
	14	+ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
	15	+
	16	+ chosen {
	17	+ stdout-path = &uart1;
	18	+ };
	19	+
	20	+ memory {
	21	+ reg = <0x80000000 0x20000000>;
	22	+ };
	23	+
	24	+ leds {
	25	+ compatible = "gpio-leds";
	26	+
	27	+ usr0 {
	28	+ label = "usr0";
	29	+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	30	+ linux,default-trigger = "heartbeat";
	31	+ };
	32	+
	33	+ usr1 {
	34	+ label = "usr1";
	35	+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
	36	+ linux,default-trigger = "mmc0";
	37	+ };
	38	+
	39	+ usr2 {
	40	+ label = "usr2";
	41	+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	42	+ linux,default-trigger = "mmc1";
	43	+ };
	44	+
	45	+ usr3 {
	46	+ label = "usr3";
	47	+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	48	+ };
	49	+ };
	50	+
	51	+ regulators {
	52	+ compatible = "simple-bus";
	53	+ #address-cells = <1>;
	54	+ #size-cells = <0>;
	55	+
	56	+ reg_usb_otg1_vbus: regulator@2 {
	57	+ compatible = "regulator-fixed";
	58	+ reg = <2>;
	59	+ pinctrl-names = "default";
	60	+ pinctrl-0 = <&pinctrl_usb_otg1>;
	61	+ regulator-name = "usb_otg1_vbus";
	62	+ regulator-min-microvolt = <5000000>;
	63	+ regulator-max-microvolt = <5000000>;
	64	+ gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	65	+ enable-active-high;
	66	+ };
	67	+
	68	+ reg_usb_otg2_vbus: regulator@3 {
	69	+ compatible = "regulator-fixed";
	70	+ reg = <3>;
	71	+ pinctrl-names = "default";
	72	+ pinctrl-0 = <&pinctrl_usb_otg2>;
	73	+ regulator-name = "usb_otg2_vbus";
	74	+ regulator-min-microvolt = <5000000>;
	75	+ regulator-max-microvolt = <5000000>;
	76	+ gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
	77	+ enable-active-high;
	78	+ };
	79	+
	80	+ };
	81	+};
	82	+
	83	+&cpu0 {
	84	+ arm-supply = <&reg_arm>;
	85	+ soc-supply = <&reg_soc>;
	86	+};
	87	+
	88	+&clks {
	89	+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	90	+ assigned-clock-rates = <786432000>;
	91	+};
	92	+
	93	+&fec1 {
	94	+ pinctrl-names = "default";
	95	+ pinctrl-0 = <&pinctrl_enet1>;
	96	+ phy-mode = "rmii";
	97	+ phy-handle = <&ethphy0>;
	98	+ status = "okay";
	99	+
	100	+ mdio {
	101	+ #address-cells = <1>;
	102	+ #size-cells = <0>;
	103	+
	104	+ ethphy0: ethernet-phy@1 {
	105	+ compatible = "ethernet-phy-ieee802.3-c22";
	106	+ reg = <1>;
	107	+ };
	108	+ };
	109	+
	110	+};
	111	+
	112	+&gpc {
	113	+ fsl,cpu_pupscr_sw2iso = <0x1>;
	114	+ fsl,cpu_pupscr_sw = <0x0>;
	115	+ fsl,cpu_pdnscr_iso2sw = <0x1>;
	116	+ fsl,cpu_pdnscr_iso = <0x1>;
	117	+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
	118	+};
	119	+
	120	+&i2c1 {
	121	+ clock-frequency = <100000>;
	122	+ pinctrl-names = "default";
	123	+ pinctrl-0 = <&pinctrl_i2c1>;
	124	+
	125	+};
	126	+
	127	+&i2c2 {
	128	+ clock_frequency = <100000>;
	129	+ pinctrl-names = "default";
	130	+ pinctrl-0 = <&pinctrl_i2c2>;
	131	+};
	132	+
	133	+&iomuxc {
	134	+ pinctrl-names = "default";
	135	+ pinctrl-0 = <&pinctrl_hog_1>;
	136	+
	137	+ pinctrl_hog_1: hoggrp-1 {
	138	+ fsl,pins = <
	139	+ /* 32kHz low power reference clock for WiFi */
	140	+ MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
	141	+ /* LED 0..3 */
	142	+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
	143	+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
	144	+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
	145	+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
	146	+ >;
	147	+ };
	148	+
	149	+ pinctrl_enet1: enet1grp {
	150	+ fsl,pins = <
	151	+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
	152	+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
	153	+
	154	+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
	155	+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
	156	+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
	157	+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
	158	+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
	159	+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
	160	+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
	161	+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
	162	+ >;
	163	+ };
	164	+
	165	+ pinctrl_i2c1: i2c1grp {
	166	+ fsl,pins = <
	167	+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
	168	+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
	169	+ >;
	170	+ };
	171	+
	172	+ pinctrl_i2c2: i2c2grp {
	173	+ fsl,pins = <
	174	+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
	175	+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
	176	+ >;
	177	+ };
	178	+
	179	+ pinctrl_tsc: tscgrp {
	180	+ fsl,pins = <
	181	+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
	182	+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
	183	+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
	184	+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
	185	+ >;
	186	+ };
	187	+
	188	+ pinctrl_uart1: uart1grp {
	189	+ fsl,pins = <
	190	+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
	191	+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
	192	+ >;
	193	+ };
	194	+
	195	+ pinctrl_usdhc2: usdhc2grp {
	196	+ fsl,pins = <
	197	+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
	198	+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
	199	+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
	200	+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
	201	+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
	202	+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
	203	+ >;
	204	+ };
	205	+
	206	+ pinctrl_wdog: wdoggrp {
	207	+ fsl,pins = <
	208	+ MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
	209	+ >;
	210	+ };
	211	+
	212	+ pinctrl_usb_otg1: usbotg1grp {
	213	+ fsl,pins = <
	214	+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
	215	+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
	216	+ >;
	217	+ };
	218	+
	219	+ pinctrl_usb_otg2: usbotg2grp {
	220	+ fsl,pins = <
	221	+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
	222	+ >;
	223	+ };
	224	+};
	225	+
	226	+&tsc {
	227	+ pinctrl-names = "default";
	228	+ pinctrl-0 = <&pinctrl_tsc>;
	229	+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	230	+ measure-delay-time = <0xffff>;
	231	+ pre-charge-time = <0xfff>;
	232	+ status = "okay";
	233	+};
	234	+
	235	+&uart1 {
	236	+ pinctrl-names = "default";
	237	+ pinctrl-0 = <&pinctrl_uart1>;
	238	+ status = "okay";
	239	+};
	240	+
	241	+&usbotg1 {
	242	+ vbus-supply = <&reg_usb_otg1_vbus>;
	243	+ pinctrl-names = "default";
	244	+ pinctrl-0 = <&pinctrl_usb_otg1>;
	245	+ dr_mode = "otg";
	246	+ srp-disable;
	247	+ hnp-disable;
	248	+ adp-disable;
	249	+ status = "okay";
	250	+};
	251	+
	252	+&usbotg2 {
	253	+ vbus-supply = <&reg_usb_otg2_vbus>;
	254	+ dr_mode = "host";
	255	+ status = "okay";
	256	+};
	257	+
	258	+&usbphy1 {
	259	+ tx-d-cal = <0x5>;
	260	+};
	261	+
	262	+&usbphy2 {
	263	+ tx-d-cal = <0x5>;
	264	+};
	265	+
	266	+&usdhc2 {
	267	+ non-removable;
	268	+ disable-wp;
	269	+ status = "okay";
	270	+};
	271	+
	272	+&wdog1 {
	273	+ pinctrl-names = "default";
	274	+ pinctrl-0 = <&pinctrl_wdog>;
	275	+ fsl,wdog_b;
	276	+};
...	...	@@ -540,6 +540,18 @@
540	540	bool "sks-imx6"
541	541	select SUPPORT_SPL
542	542
	543	+config TARGET_SOMLABS_VISIONSOM_6ULL
	544	+ bool "visionsom-6ull"
	545	+ select MX6ULL
	546	+ select BOARD_LATE_INIT
	547	+ select DM
	548	+ select DM_ETH
	549	+ select DM_GPIO
	550	+ select DM_MMC
	551	+ select DM_SERIAL
	552	+ select DM_THERMAL
	553	+ imply CMD_DM
	554	+
543	555	config TARGET_TBS2910
544	556	bool "TBS2910 Matrix ARM mini PC"
545	557
...	...	@@ -694,6 +706,7 @@
694	706	source "board/seco/Kconfig"
695	707	source "board/sks-kinkel/sksimx6/Kconfig"
696	708	source "board/solidrun/mx6cuboxi/Kconfig"
	709	+source "board/somlabs/visionsom-6ull/Kconfig"
697	710	source "board/technexion/pico-imx6/Kconfig"
698	711	source "board/technexion/pico-imx6ul/Kconfig"
699	712	source "board/tbs/tbs2910/Kconfig"
	1	+if TARGET_SOMLABS_VISIONSOM_6ULL
	2	+
	3	+config SYS_BOARD
	4	+ default "visionsom-6ull"
	5	+
	6	+config SYS_VENDOR
	7	+ default "somlabs"
	8	+
	9	+config SYS_CONFIG_NAME
	10	+ default "somlabs_visionsom_6ull"
	11	+
	12	+endif
	1	+VISIONSOM-6ULL BOARD
	2	+M: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
	3	+S: Maintained
	4	+F: board/somlabs/visionsom-6ull/
	5	+F: include/configs/somlabs_visionsom_6ull.h
	6	+F: configs/somlabs_visionsom_6ull_defconfig
	1	+# SPDX-License-Identifier: GPL-2.0+
	2	+# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas@somlabs.com>
	3	+
	4	+obj-y := visionsom-6ull.o
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * Copyright (C) 2017 A. Karas
	4	+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
	5	+ *
	6	+ * Refer docs/README.imxmage for more details about how-to configure
	7	+ * and create imximage boot image
	8	+ *
	9	+ * The syntax is taken as close as possible with the kwbimage
	10	+ */
	11	+
	12	+#define __ASSEMBLY__
	13	+#include <config.h>
	14	+
	15	+/* image version */
	16	+
	17	+IMAGE_VERSION 2
	18	+
	19	+/*
	20	+ * Boot Device : sd
	21	+ */
	22	+
	23	+BOOT_FROM sd
	24	+
	25	+/*
	26	+ * Secure boot support
	27	+ */
	28	+#ifdef CONFIG_IMX_HAB
	29	+CSF CONFIG_CSF_SIZE
	30	+#endif
	31	+
	32	+/*
	33	+ * Device Configuration Data (DCD)
	34	+ *
	35	+ * Each entry must have the format:
	36	+ * Addr-type Address Value
	37	+ *
	38	+ * where:
	39	+ * Addr-type register length (1,2 or 4 bytes)
	40	+ * Address absolute address of the register
	41	+ * value value to be stored in the register
	42	+ */
	43	+
	44	+/* Micron MT41K256M16TW-107 */
	45	+
	46	+/* Enable all clocks */
	47	+DATA 4 0x020c4068 0xffffffff
	48	+DATA 4 0x020c406c 0xffffffff
	49	+DATA 4 0x020c4070 0xffffffff
	50	+DATA 4 0x020c4074 0xffffffff
	51	+DATA 4 0x020c4078 0xffffffff
	52	+DATA 4 0x020c407c 0xffffffff
	53	+DATA 4 0x020c4080 0xffffffff
	54	+
	55	+DATA 4 0x020E04B4 0x000C0000
	56	+DATA 4 0x020E04AC 0x00000000
	57	+DATA 4 0x020E027C 0x00000030
	58	+DATA 4 0x020E0250 0x00000030
	59	+DATA 4 0x020E024C 0x00000030
	60	+DATA 4 0x020E0490 0x00000030
	61	+DATA 4 0x020E0288 0x00000030
	62	+DATA 4 0x020E0270 0x00000000
	63	+DATA 4 0x020E0260 0x00000030
	64	+DATA 4 0x020E0264 0x00000030
	65	+DATA 4 0x020E04A0 0x00000030
	66	+DATA 4 0x020E0494 0x00020000
	67	+DATA 4 0x020E0280 0x00000030
	68	+DATA 4 0x020E0284 0x00000030
	69	+DATA 4 0x020E04B0 0x00020000
	70	+DATA 4 0x020E0498 0x00000030
	71	+DATA 4 0x020E04A4 0x00000030
	72	+DATA 4 0x020E0244 0x00000030
	73	+DATA 4 0x020E0248 0x00000030
	74	+DATA 4 0x021B001C 0x00008000
	75	+DATA 4 0x021B0800 0xA1390003
	76	+DATA 4 0x021B080C 0x00000000
	77	+DATA 4 0x021B083C 0x41570155
	78	+DATA 4 0x021B0848 0x4040474A
	79	+DATA 4 0x021B0850 0x40405550
	80	+DATA 4 0x021B081C 0x33333333
	81	+DATA 4 0x021B0820 0x33333333
	82	+DATA 4 0x021B082C 0xf3333333
	83	+DATA 4 0x021B0830 0xf3333333
	84	+DATA 4 0x021B08C0 0x00921012
	85	+DATA 4 0x021B08b8 0x00000800
	86	+DATA 4 0x021B0004 0x0002002D
	87	+DATA 4 0x021B0008 0x1B333030
	88	+DATA 4 0x021B000C 0x676B52F3
	89	+DATA 4 0x021B0010 0xB66D0B63
	90	+DATA 4 0x021B0014 0x01FF00DB
	91	+DATA 4 0x021B0018 0x00201740
	92	+DATA 4 0x021B001C 0x00008000
	93	+DATA 4 0x021B002C 0x000026D2
	94	+DATA 4 0x021B0030 0x006B1023
	95	+DATA 4 0x021B0040 0x0000004F
	96	+DATA 4 0x021B0000 0x84180000
	97	+DATA 4 0x021B0890 0x23400A38
	98	+DATA 4 0x021B001C 0x02008032
	99	+DATA 4 0x021B001C 0x00008033
	100	+DATA 4 0x021B001C 0x00048031
	101	+DATA 4 0x021B001C 0x15208030
	102	+DATA 4 0x021B001C 0x04008040
	103	+DATA 4 0x021B0020 0x00000800
	104	+DATA 4 0x021B0818 0x00000227
	105	+DATA 4 0x021B0004 0x0002552D
	106	+DATA 4 0x021B0404 0x00011006
	107	+DATA 4 0x021B001C 0x00000000
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * Copyright (C) 2017-2019 A. Karas, SomLabs
	4	+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
	5	+ */
	6	+
	7	+#include <init.h>
	8	+#include <asm/arch/clock.h>
	9	+#include <asm/arch/crm_regs.h>
	10	+#include <asm/arch/imx-regs.h>
	11	+#include <asm/arch/iomux.h>
	12	+#include <asm/arch/mx6-pins.h>
	13	+#include <asm/arch/sys_proto.h>
	14	+#include <asm/gpio.h>
	15	+#include <asm/mach-imx/boot_mode.h>
	16	+#include <asm/mach-imx/iomux-v3.h>
	17	+#include <asm/mach-imx/mxc_i2c.h>
	18	+#include <asm/io.h>
	19	+#include <common.h>
	20	+#include <env.h>
	21	+#include <fsl_esdhc_imx.h>
	22	+#include <i2c.h>
	23	+#include <miiphy.h>
	24	+#include <linux/sizes.h>
	25	+#include <mmc.h>
	26	+#include <netdev.h>
	27	+
	28	+DECLARE_GLOBAL_DATA_PTR;
	29	+
	30	+#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	31	+ PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	32	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	33	+
	34	+int dram_init(void)
	35	+{
	36	+ gd->ram_size = imx_ddr_size();
	37	+
	38	+ return 0;
	39	+}
	40	+
	41	+static iomux_v3_cfg_t const uart1_pads[] = {
	42	+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	43	+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	44	+};
	45	+
	46	+static void setup_iomux_uart(void)
	47	+{
	48	+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	49	+}
	50	+
	51	+#ifdef CONFIG_FEC_MXC
	52	+static int setup_fec(void)
	53	+{
	54	+ struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	55	+ int ret;
	56	+
	57	+ /*
	58	+ * Use 50M anatop loopback REF_CLK1 for ENET1,
	59	+ * clear gpr1[13], set gpr1[17].
	60	+ */
	61	+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
	62	+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	63	+
	64	+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	65	+ if (ret)
	66	+ return ret;
	67	+
	68	+ enable_enet_clk(1);
	69	+
	70	+ return 0;
	71	+}
	72	+
	73	+int board_phy_config(struct phy_device *phydev)
	74	+{
	75	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
	76	+
	77	+ if (phydev->drv->config)
	78	+ phydev->drv->config(phydev);
	79	+
	80	+ return 0;
	81	+}
	82	+#endif
	83	+
	84	+int board_mmc_get_env_dev(int devno)
	85	+{
	86	+ return devno;
	87	+}
	88	+
	89	+int mmc_map_to_kernel_blk(int devno)
	90	+{
	91	+ return devno;
	92	+}
	93	+
	94	+int board_early_init_f(void)
	95	+{
	96	+ setup_iomux_uart();
	97	+
	98	+ return 0;
	99	+}
	100	+
	101	+int board_init(void)
	102	+{
	103	+ /* Address of boot parameters */
	104	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	105	+
	106	+#ifdef CONFIG_SYS_I2C
	107	+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	108	+#endif
	109	+
	110	+#ifdef CONFIG_FEC_MXC
	111	+ setup_fec();
	112	+#endif
	113	+
	114	+ return 0;
	115	+}
	116	+
	117	+#ifdef CONFIG_CMD_BMODE
	118	+static const struct boot_mode board_boot_modes[] = {
	119	+ /* 4 bit bus width */
	120	+ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
	121	+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	122	+ {NULL, 0},
	123	+};
	124	+#endif
	125	+
	126	+int board_late_init(void)
	127	+{
	128	+#ifdef CONFIG_CMD_BMODE
	129	+ add_board_boot_modes(board_boot_modes);
	130	+#endif
	131	+
	132	+ if (is_cpu_type(MXC_CPU_MX6ULL))
	133	+ env_set("board", "visionsom-6ull");
	134	+ else
	135	+ env_set("board", "visionsom-6ul");
	136	+
	137	+ return 0;
	138	+}
	139	+
	140	+int checkboard(void)
	141	+{
	142	+ printf("Board: SoMLabs VisionSOM-6UL%s\n",
	143	+ is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
	144	+
	145	+ return 0;
	146	+}
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_MX6=y
	3	+CONFIG_SYS_TEXT_BASE=0x87800000
	4	+CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
	5	+CONFIG_ENV_SIZE=0x2000
	6	+CONFIG_ENV_OFFSET=0xC0000
	7	+CONFIG_NR_DRAM_BANKS=1
	8	+CONFIG_FIT=y
	9	+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
	10	+CONFIG_SUPPORT_RAW_INITRD=y
	11	+CONFIG_BOUNCE_BUFFER=y
	12	+CONFIG_BOARD_EARLY_INIT_F=y
	13	+CONFIG_HUSH_PARSER=y
	14	+CONFIG_CMD_BOOTZ=y
	15	+CONFIG_CMD_MEMTEST=y
	16	+CONFIG_CMD_GPIO=y
	17	+CONFIG_CMD_MMC=y
	18	+CONFIG_CMD_USB=y
	19	+CONFIG_CMD_DHCP=y
	20	+CONFIG_CMD_MII=y
	21	+# CONFIG_CMD_MDIO is not set
	22	+CONFIG_CMD_PING=y
	23	+CONFIG_CMD_CACHE=y
	24	+CONFIG_CMD_EXT2=y
	25	+CONFIG_CMD_EXT4=y
	26	+CONFIG_CMD_EXT4_WRITE=y
	27	+CONFIG_CMD_FAT=y
	28	+CONFIG_CMD_FS_GENERIC=y
	29	+CONFIG_OF_CONTROL=y
	30	+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
	31	+CONFIG_ENV_IS_IN_MMC=y
	32	+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
	33	+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
	34	+CONFIG_NET_RANDOM_ETHADDR=y
	35	+CONFIG_FSL_USDHC=y
	36	+CONFIG_PHYLIB=y
	37	+CONFIG_PHY_MICREL=y
	38	+CONFIG_PHY_MICREL_KSZ8XXX=y
	39	+CONFIG_MII=y
	40	+CONFIG_PINCTRL=y
	41	+CONFIG_PINCTRL_IMX6=y
	42	+CONFIG_DM_REGULATOR=y
	43	+CONFIG_DM_REGULATOR_FIXED=y
	44	+CONFIG_DM_REGULATOR_GPIO=y
	45	+CONFIG_USB=y
	46	+CONFIG_DM_USB=y
	47	+CONFIG_USB_STORAGE=y
	48	+CONFIG_LZO=y
	49	+# CONFIG_EFI_LOADER is not set