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Commit 5ba6616130008392349492cef893f48fb1305282

Authored by Suman Anna
Committed by Lokesh Vutla
1 parent f52e668e65
Exists in v2016.05-smarct4x and in 3 other branches v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc

ARM: DRA7: Fix DSP OPP_HIGH clock rates on DRA722 SoCs 

The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") defined different clock rates for
DSP at OPP_HIGH between DRA75x/AM572x and DRA72x/AM571x family
of SoCs. The DRA72x OPP_HIGH clock rate was based on the current
DRA72x Data Manual. The OPP_HIGH clock rate for AM571x is though
defined to be as the same as the AM572x SoCs - 750 MHz. The DRA7xx
DMs will be updated soon to mark the highest supported frequency
as 750 MHz. So, fixup the DSP OPP_HIGH clock rate accordingly.
The clock rates are also consolidated since they are identical
across all the DRA75x/AM572x, DRA72x/AM571x family of SoCs.

While at this, fix couple of minor typos, one a fix for the
IVA clock number macro in the IVA clock names definition, and
another a trace correction.

Fixes: 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock frequencies based on OPP")
Signed-off-by: Suman Anna <s-anna@ti.com>

Showing 1 changed file with 6 additions and 19 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/fdt.c
Diff comments   View file @ 5ba6616
... ... @@ -182,36 +182,24 @@
182 182 "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck",
183 183 };
184 184  
185   -const char *dra7_opp_iva_clk_names[OPP_DSP_CLK_NUM] = {
  185 +const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
186 186 "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck",
187 187 "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck",
188 188 };
189 189  
190 190 /* DSPEVE voltage domain */
191 191 #if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH) /* OPP_HIGH */
192   -u32 dra752_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
  192 +u32 dra7_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
193 193 750000000, 750000000, 500000000,
194 194 };
195   -
196   -u32 dra722_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
197   - 700000000, 700000000, 466666667,
198   -};
199 195 #elif defined(CONFIG_DRA7_DSPEVE_OPP_OD) /* OPP_OD */
200   -u32 dra722_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
  196 +u32 dra7_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
201 197 700000000, 700000000, 466666667,
202 198 };
203   -
204   -u32 dra752_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
205   - 700000000, 700000000, 466666667,
206   -};
207 199 #else /* OPP_NOM */
208   -u32 dra752_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
  200 +u32 dra7_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
209 201 600000000, 600000000, 400000000,
210 202 };
211   -
212   -u32 dra722_opp_dsp_clk_rates[OPP_DSP_CLK_NUM] = {
213   - 600000000, 600000000, 400000000,
214   -};
215 203 #endif
216 204  
217 205 /* IVA voltage domain */
... ... @@ -244,7 +232,7 @@
244 232 ret = fdt_setprop_u32(fdt, offs, "assigned-clock-rates",
245 233 rates[i]);
246 234 if (ret < 0) {
247   - debug("Could not add reg property to node %s: %s\n",
  235 + debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
248 236 paths[i], fdt_strerror(ret));
249 237 return ret;
250 238 }
... ... @@ -264,8 +252,7 @@
264 252  
265 253 /* fixup DSP clocks */
266 254 clk_names = dra7_opp_dsp_clk_names;
267   - clk_rates = is_dra72x() ? dra722_opp_dsp_clk_rates :
268   - dra752_opp_dsp_clk_rates;
  255 + clk_rates = dra7_opp_dsp_clk_rates;
269 256 ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
270 257 if (ret) {
271 258 printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",