Commit 5bbeea86eb6afb872374cd23217cb3c1018443ed
Committed by
Kim Phillips
Kim Phillips
1 parent
fc549c871f
Exists in
master
and in
54 other branches
mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.
The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Showing 3 changed files with 28 additions and 14 deletions Side-by-side Diff
cpu/mpc83xx/cpu_init.c
| ... | ... | @@ -79,6 +79,12 @@ |
| 79 | 79 | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); |
| 80 | 80 | #endif |
| 81 | 81 | |
| 82 | +#ifdef CFG_SPCR_OPT | |
| 83 | + /* Optimize transactions between CSB and other devices */ | |
| 84 | + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | | |
| 85 | + (CFG_SPCR_OPT << SPCR_OPT_SHIFT); | |
| 86 | +#endif | |
| 87 | + | |
| 82 | 88 | #ifdef CFG_SPCR_TSECEP |
| 83 | 89 | /* all eTSEC's Emergency priority */ |
| 84 | 90 | im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | |
include/configs/MPC8323ERDB.h
| ... | ... | @@ -66,6 +66,13 @@ |
| 66 | 66 | #define CFG_IMMR 0xE0000000 |
| 67 | 67 | |
| 68 | 68 | /* |
| 69 | + * System performance | |
| 70 | + */ | |
| 71 | +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
| 72 | +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
| 73 | +#define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ | |
| 74 | + | |
| 75 | +/* | |
| 69 | 76 | * DDR Setup |
| 70 | 77 | */ |
| 71 | 78 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ |
| 72 | 79 | |
| ... | ... | @@ -83,10 +90,9 @@ |
| 83 | 90 | */ |
| 84 | 91 | #define CFG_DDR_SIZE 64 /* MB */ |
| 85 | 92 | #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ |
| 86 | - | CSCONFIG_AP \ | |
| 87 | - | 0x00040000 /* TODO */ \ | |
| 93 | + | CSCONFIG_ODT_WR_ACS \ | |
| 88 | 94 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) |
| 89 | - /* 0x80840101 */ | |
| 95 | + /* 0x80010101 */ | |
| 90 | 96 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ |
| 91 | 97 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ |
| 92 | 98 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ |
| 93 | 99 | |
| 94 | 100 | |
| 95 | 101 | |
| 96 | 102 | |
| 97 | 103 | |
| ... | ... | @@ -96,28 +102,29 @@ |
| 96 | 102 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ |
| 97 | 103 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) |
| 98 | 104 | /* 0x00220802 */ |
| 99 | -#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
| 100 | - | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | |
| 101 | - | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
| 105 | +#define CFG_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
| 106 | + | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | |
| 107 | + | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
| 102 | 108 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ |
| 103 | - | (13 << TIMING_CFG1_REFREC_SHIFT ) \ | |
| 104 | - | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | |
| 109 | + | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ | |
| 110 | + | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | |
| 105 | 111 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ |
| 106 | 112 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) |
| 107 | - /* 0x3935d322 */ | |
| 108 | -#define CFG_DDR_TIMING_2 ( (31 << TIMING_CFG2_CPO_SHIFT ) \ | |
| 113 | + /* 0x26253222 */ | |
| 114 | +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | |
| 115 | + | (31 << TIMING_CFG2_CPO_SHIFT ) \ | |
| 109 | 116 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ |
| 110 | 117 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ |
| 111 | 118 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ |
| 112 | 119 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ |
| 113 | - | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
| 114 | - /* 0x0f9048ca */ | |
| 120 | + | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
| 121 | + /* 0x1f9048c7 */ | |
| 115 | 122 | #define CFG_DDR_TIMING_3 0x00000000 |
| 116 | 123 | #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
| 117 | 124 | /* 0x02000000 */ |
| 118 | -#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ | |
| 125 | +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ | |
| 119 | 126 | | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) |
| 120 | - /* 0x44400232 */ | |
| 127 | + /* 0x44480232 */ | |
| 121 | 128 | #define CFG_DDR_MODE2 0x8000c000 |
| 122 | 129 | #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
| 123 | 130 | | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
include/mpc83xx.h
| ... | ... | @@ -121,6 +121,7 @@ |
| 121 | 121 | #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ |
| 122 | 122 | #define SPCR_PCIPR_SHIFT (31-7) |
| 123 | 123 | #define SPCR_OPT 0x00800000 /* Optimize */ |
| 124 | +#define SPCR_OPT_SHIFT (31-8) | |
| 124 | 125 | #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ |
| 125 | 126 | #define SPCR_TBEN_SHIFT (31-9) |
| 126 | 127 | #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ |